Re: [PATCH 02/13] dt-bindings: clock: qcom,sm8550-dispcc: Add display CESTA support on SM8750

[Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>]

On 4/20/2026 11:15 PM, Dmitry Baryshkov wrote:
> On Mon, Apr 20, 2026 at 09:58:55PM +0530, Jagadeesh Kona wrote:
>> On SM8750, a subset of DISPCC clocks is controlled by the display CESTA
>> (Client State Aggregator) hardware. These clocks can be scaled to the
>> desired frequency by sending votes to the display CRM(CESTA Resource
>> manager) instead of programming DISPCC registers directly.
>>
>> Add bindings to allow the DISPCC node to reference the display CRM node
>> for sending votes to CESTA hardware and the CRMC syscon regmap node
>> which is used to read the frequency look up tables provided by CRM and
>> populate this data in RCG's frequency tables for CESTA controlled clocks.
>>
>> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
>> ---
>>  .../bindings/clock/qcom,sm8550-dispcc.yaml         | 48 ++++++++++++++++++++++
>>  1 file changed, 48 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
>> index 591ce91b8d54dd6f78a66d029882bcd94b53beda..3e049b2160a1781c866bb30b29f0da5c9e156b61 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
>> @@ -60,6 +60,18 @@ properties:
>>        A phandle to an OPP node describing required MMCX performance point.
>>      maxItems: 1
>>  
>> +  qcom,crm:
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +    description:
>> +      Phandle to the display CRM (CESTA Resource Manager) node, used to communicate
>> +      with the display CESTA (Client State Aggregator) hardware.
> 
> Is it going to be shared by several entities? If not, can be make a part
> of the dispcc and get rid of the extra CC <-> CRM API?
> 

Thanks Dmitry for your review.

Yes, clock is one of the consumer of CRM, but CRM can be used by interconnect drivers also
for BW voting via CESTA.

>> +
>> +  qcom,crmc-regmap:
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +    description:
>> +      Phandle to the syscon providing the CRMC (CRM clock) regmap used
>> +      to read frequency LUTs (lookup tables) populated by the CRM.
> 
> Why is this coming as a syscon? Why isn't it just a register region of
> the dispcc?
> 

The CRMC block is not part of the DISPCC register region; it is a separate sub‑block within the
CRM(CESTA) address space. It contains clocks frequency lookup tables that the clock driver reads
to populate RCG frequency tables. Since CRMC block is outside of DISPCC region and DISPCC driver
doesn't own or manage the CRMC block and uses it just to read CRM controlled RCG's frequency
tables, marked it as a syscon device.

Thanks,
Jagadeesh