From: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Lee Jones <lee@kernel.org>,
Ajit Pandey <ajit.pandey@oss.qualcomm.com>,
Imran Shaik <imran.shaik@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
Maulik Shah <maulik.shah@oss.qualcomm.com>,
Taniya Das <taniya.das@oss.qualcomm.com>
Subject: Re: [PATCH 07/13] clk: qcom: clk-alpha-pll: Add support to skip PLL configuration
Date: Tue, 28 Apr 2026 22:52:17 +0530 [thread overview]
Message-ID: <de7a2958-e431-4162-b0a0-d58bbebb600d@oss.qualcomm.com> (raw)
In-Reply-To: <269bdec3-6340-4b27-9b38-3fc1dfc958c8@oss.qualcomm.com>
On 4/23/2026 4:43 PM, Konrad Dybcio wrote:
> On 4/22/26 8:28 PM, Dmitry Baryshkov wrote:
>> On Mon, Apr 20, 2026 at 09:59:00PM +0530, Jagadeesh Kona wrote:
>>> Some PLLs are already configured as part of CRM(CESTA Resource
>>> manager) initialization. Add support to skip PLL reconfiguration
>>> for such PLLs that are already configured.
>>>
>>> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
>>> ---
>>> drivers/clk/qcom/clk-alpha-pll.c | 8 +++++++-
>>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
>>> index 67fc97739d0d4c26aec0bac5d43d1b87d297bc6a..2f4ebf4d3884b92c981dbe0e67245704a88881ad 100644
>>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>>> @@ -2332,7 +2332,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
>>> void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>>> const struct alpha_pll_config *config)
>>> {
>>> - u32 lval = config->l;
>>> + u32 lval = config->l, regval;
>>>
>>> /*
>>> * If the bootloader left the PLL enabled it's likely that there are
>>> @@ -2343,6 +2343,12 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
>>> return;
>>> }
>>>
>>> + /* Return early if PLL is already configured */
>>> + regmap_read(regmap, PLL_L_VAL(pll), ®val);
>>> + regval &= LUCID_EVO_PLL_L_VAL_MASK;
>>> + if (regval)
>>> + return;
>>> +
>>
>> Why is it being applied only to Lucid EVO PLLs?
>
Thanks Dmitry and Konrad for your reviews.
This is the function used to configure all Taycan PLLs, currently all the PLLs
configured during CESTA initialization belong to Taycan type only. I will recheck
if similar logic is required for any additional PLL types also.
> These clocks already have a an .is_enabled() callback, could that be
> treated as equivalent?
>
We already have is_enabled check to avoid configuring PLL's that are already enabled.
There can be case where PLL is configured from bootloader but not enabled during bootup.
This check avoids re-configuring such PLLs that are already configured by bootloader but
not enabled.
Thanks,
Jagadeesh
next prev parent reply other threads:[~2026-04-28 17:22 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-20 16:28 [PATCH 00/13] Add support to control clocks using CESTA Resource manager Jagadeesh Kona
2026-04-20 16:28 ` [PATCH 01/13] dt-bindings: soc: Introduce device bindings for CESTA Resource Manager Jagadeesh Kona
2026-04-20 17:39 ` Dmitry Baryshkov
2026-04-22 7:37 ` Krzysztof Kozlowski
2026-04-20 16:28 ` [PATCH 02/13] dt-bindings: clock: qcom,sm8550-dispcc: Add display CESTA support on SM8750 Jagadeesh Kona
2026-04-20 17:45 ` Dmitry Baryshkov
2026-04-28 17:21 ` Jagadeesh Kona
2026-04-28 18:56 ` Dmitry Baryshkov
2026-04-22 7:41 ` Krzysztof Kozlowski
2026-04-24 9:09 ` Krzysztof Kozlowski
2026-04-28 17:25 ` Jagadeesh Kona
2026-04-20 16:28 ` [PATCH 03/13] dt-bindings: mfd: syscon: Add qcom,crmc-syscon compatible Jagadeesh Kona
2026-04-22 7:39 ` Krzysztof Kozlowski
2026-04-20 16:28 ` [PATCH 04/13] soc: qcom: Introduce CESTA resource manager driver Jagadeesh Kona
2026-04-22 7:50 ` Krzysztof Kozlowski
2026-04-20 16:28 ` [PATCH 05/13] clk: qcom: common: Add helpers to control clocks using CRM Jagadeesh Kona
2026-04-20 16:28 ` [PATCH 06/13] clk: qcom: clk-alpha-pll: Add support for CRM based PLL ops Jagadeesh Kona
2026-04-22 18:25 ` Dmitry Baryshkov
2026-04-20 16:29 ` [PATCH 07/13] clk: qcom: clk-alpha-pll: Add support to skip PLL configuration Jagadeesh Kona
2026-04-22 18:28 ` Dmitry Baryshkov
2026-04-23 11:13 ` Konrad Dybcio
2026-04-28 17:22 ` Jagadeesh Kona [this message]
2026-04-20 16:29 ` [PATCH 08/13] clk: qcom: clk-rcg2: Add support for CRM based RCG ops Jagadeesh Kona
2026-04-20 16:29 ` [PATCH 09/13] clk: qcom: common: Add support to register and control clocks using CRM Jagadeesh Kona
2026-04-20 16:29 ` [PATCH 10/13] clk: qcom: dispcc-sm8750: Add support to control MDP clocks using CESTA Jagadeesh Kona
2026-04-22 18:33 ` Dmitry Baryshkov
2026-04-28 17:21 ` Jagadeesh Kona
2026-04-28 18:54 ` Dmitry Baryshkov
2026-04-20 17:24 ` [PATCH 11/13] arm64: dts: qcom: sm8750: Add Display CRM device Jagadeesh Kona
2026-04-20 17:28 ` [PATCH 12/13] arm64: dts: qcom: sm8750: Add disp_crmc node and CRM properties to dispcc Jagadeesh Kona
2026-04-20 17:28 ` [PATCH 13/13] arm64: defconfig: Enable Qualcomm CESTA Resource Manager Jagadeesh Kona
2026-04-20 17:47 ` Dmitry Baryshkov
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