From: Krzysztof Kozlowski <krzk@kernel.org>
To: Qiang Yu <qiang.yu@oss.qualcomm.com>
Cc: Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for glymur Gen5 x8 bifurcation mode
Date: Wed, 22 Apr 2026 08:27:31 +0200 [thread overview]
Message-ID: <3b21c15e-942a-4a01-a083-8fbe33197690@kernel.org> (raw)
In-Reply-To: <aeXUZ1uSEJ9InUtw@hu-qianyu-lv.qualcomm.com>
On 20/04/2026 09:23, Qiang Yu wrote:
>>> It is not the same as the 5x4 PHY. In DT, we model three PHY nodes:
>>> phy_3a (1x4), phy_3b (1x4), and a separate phy_1x8 node for x8 mode.
>>
>> OK, that's what I wanted to hear. And that's what should not be done,
>>
>> You should not have a separate node for the same hardware. First, DTC
>> will give you a W=1 warning, although warning itself should be moved to
>> W=2.
>>
>> Second, the warning tells important story - same hardware is described
>> twice.
>>
>> You only need phy_3a and phy_3b, so only two in total.
>
> We can keep only phy_3a and phy_3b, but still add new compatible
> qcom,glymur-qmp-gen5x8-pcie-phy in binding, right?
No, you cannot. You cannot create fake device nodes.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-04-22 6:27 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-13 6:25 [PATCH v3 0/5] phy: qcom: qmp-pcie: Add PCIe Gen5 8-lane bifurcation support for Glymur Qiang Yu
2026-04-13 6:25 ` [PATCH v3 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for glymur Gen5 x8 bifurcation mode Qiang Yu
2026-04-15 7:50 ` Krzysztof Kozlowski
2026-04-16 2:58 ` Qiang Yu
2026-04-17 9:18 ` Krzysztof Kozlowski
2026-04-20 7:23 ` Qiang Yu
2026-04-20 13:23 ` Krzysztof Kozlowski
2026-04-22 6:19 ` Qiang Yu
2026-04-22 6:27 ` Krzysztof Kozlowski [this message]
2026-04-22 6:27 ` Krzysztof Kozlowski
2026-04-23 6:29 ` Qiang Yu
2026-04-13 6:25 ` [PATCH v3 2/5] phy: qcom: qmp-pcie: Add multiple power-domains support Qiang Yu
2026-04-13 6:25 ` [PATCH v3 3/5] phy: qcom: qmp-pcie: Support multiple nocsr resets Qiang Yu
2026-04-13 8:10 ` Philipp Zabel
2026-04-16 3:02 ` Qiang Yu
2026-04-13 6:25 ` [PATCH v3 4/5] phy: qcom: qmp-pcie: Add Gen5 8-lanes mode for Glymur Qiang Yu
2026-04-13 6:26 ` [PATCH v3 5/5] arch: arm64: dts: qcom: Add support for PCIe3a Qiang Yu
2026-04-15 7:44 ` Krzysztof Kozlowski
2026-04-16 3:24 ` Qiang Yu
2026-04-16 6:19 ` Krzysztof Kozlowski
2026-04-20 7:30 ` Qiang Yu
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