From: Umang Chheda <umang.chheda@oss.qualcomm.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
Trilok Soni <trilokkumar.soni@oss.qualcomm.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Ruidong Tian <tianruidong@linux.alibaba.com>,
Tony Luck <tony.luck@intel.com>, Borislav Petkov <bp@alien8.de>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org,
faruque.ansari@oss.qualcomm.com,
avaneesh.dwivedi@oss.qualcomm.com
Subject: Re: [PATCH v2 1/4] dt-bindings: arm: ras: Introduce bindings for ARM RAS error sources
Date: Fri, 14 Aug 2026 16:35:43 +0530 [thread overview]
Message-ID: <3d8101b2-558b-48e0-badd-a8e439c74dd0@oss.qualcomm.com> (raw)
In-Reply-To: <20260728-determined-lorikeet-from-tartarus-cf124e@quoll>
Hello Krzysztof, Trilok,
On 7/28/2026 2:17 PM, Krzysztof Kozlowski wrote:
> On Mon, Jul 27, 2026 at 01:51:08PM -0700, Trilok Soni wrote:
>> On 7/20/2026 1:19 AM, Umang Chheda wrote:
>>> new file mode 100644
>>> index 000000000000..c2f4e1f8243e
>>> --- /dev/null
>>> +++ b/include/dt-bindings/arm/arm-ras.h
>>> @@ -0,0 +1,11 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>>> +
>>> +#ifndef _DT_BINDINGS_ARM_RAS_H
>>> +#define _DT_BINDINGS_ARM_RAS_H
>>> +
>>> +/* arm,group-format - error record group register window page size */
>>> +#define ARM_RAS_GROUP_4K 0 /* 4 KiB, 1 ERRGSR */
>>> +#define ARM_RAS_GROUP_16K 1 /* 16 KiB, 4 ERRGSRs */
>>> +#define ARM_RAS_GROUP_64K 2 /* 64 KiB, 14 ERRGSRs */
>>
>> Do you want me to have different DT for 4k and 16k and 64k? This is not a right approach.
>>
>
> Is this page size or register window page size? If the latter, why would
> device registers be a binding?
Thanks for the review. To clarify both points:
On "page size" vs "register window page size":
The comment in arm-ras.h is misleading — I will fix it. It is neither a
memory page size nor a kernel page granularity. The 4K/16K/64K values
refer to the three fixed error record group register window layouts
defined by the ARM RAS architecture specification. The naming comes from
the ARM spec itself which uses these sizes to describe the three
possible layouts of the MMIO window. I will update the comment to make
this clear.
On "why would device registers be a binding":
This is a static hardware property — it describes which of the three
fixed register layouts the hardware block implements, and it is not
self-discoverable at runtime. There is no register within the window
that encodes the layout. The driver needs it upfront to:
- Determine the correct ioremap size
- Know how many ERRGSR registers to scan
- Know the array length for arm,record-impl and arm,status-reporting
I will also fix the misleading comment in arm-ras.h from "register
window page size" to "error record group register window layout" in v3.
>
> Best regards,
> Krzysztof
>
Thanks,
Umang
next prev parent reply other threads:[~2026-08-14 11:05 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-20 8:19 [PATCH v2 0/4] arm: ras: Add DT frontend support for ARM RAS Umang Chheda
2026-07-20 8:19 ` [PATCH v2 1/4] dt-bindings: arm: ras: Introduce bindings for ARM RAS error sources Umang Chheda
2026-07-27 20:51 ` Trilok Soni
2026-07-28 8:47 ` Krzysztof Kozlowski
2026-08-14 11:05 ` Umang Chheda [this message]
2026-07-28 8:53 ` Krzysztof Kozlowski
2026-07-31 20:35 ` Rob Herring
2026-08-17 19:58 ` Umang Chheda
2026-07-20 8:19 ` [PATCH v2 2/4] arm64: ras: Add Device Tree frontend Umang Chheda
2026-07-20 8:19 ` [PATCH v2 3/4] arm64: dts: qcom: monaco: add RAS error source nodes Umang Chheda
2026-08-02 3:49 ` Bjorn Andersson
2026-08-24 9:11 ` Umang Chheda
2026-07-20 8:19 ` [PATCH v2 4/4] arm64: dts: qcom: lemans: " Umang Chheda
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