* [PATCH 01/16] media: iris: Skip UBWC configuration when not supported
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 8:02 ` Konrad Dybcio
` (2 more replies)
2026-05-07 6:42 ` [PATCH 02/16] media: iris: Filter UBWC raw formats based on hardware capabilities Dmitry Baryshkov
` (15 subsequent siblings)
16 siblings, 3 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
UBWC configuration is not applicable to all SoCs. Add a check to avoid
configuring UBWC during sys init on unsupported platforms.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
index 0d05dd2afc07..6e04175eb904 100644
--- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
+++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
@@ -140,6 +140,9 @@ void iris_hfi_gen2_packet_sys_init(struct iris_core *core, struct iris_hfi_heade
&payload,
sizeof(u32));
+ if (!ubwc->ubwc_enc_version)
+ return;
+
payload = qcom_ubwc_macrotile_mode(ubwc) ? 8 : 4;
iris_hfi_gen2_create_packet(hdr,
HFI_PROP_UBWC_MAX_CHANNELS,
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 01/16] media: iris: Skip UBWC configuration when not supported
2026-05-07 6:42 ` [PATCH 01/16] media: iris: Skip UBWC configuration when not supported Dmitry Baryshkov
@ 2026-05-07 8:02 ` Konrad Dybcio
2026-05-07 13:03 ` Vikash Garodia
2026-05-11 5:31 ` Vishnu Reddy
2 siblings, 0 replies; 36+ messages in thread
From: Konrad Dybcio @ 2026-05-07 8:02 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/26 8:42 AM, Dmitry Baryshkov wrote:
> From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
>
> UBWC configuration is not applicable to all SoCs. Add a check to avoid
> configuring UBWC during sys init on unsupported platforms.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 01/16] media: iris: Skip UBWC configuration when not supported
2026-05-07 6:42 ` [PATCH 01/16] media: iris: Skip UBWC configuration when not supported Dmitry Baryshkov
2026-05-07 8:02 ` Konrad Dybcio
@ 2026-05-07 13:03 ` Vikash Garodia
2026-05-11 5:31 ` Vishnu Reddy
2 siblings, 0 replies; 36+ messages in thread
From: Vikash Garodia @ 2026-05-07 13:03 UTC (permalink / raw)
To: Dmitry Baryshkov, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> From: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
>
> UBWC configuration is not applicable to all SoCs. Add a check to avoid
> configuring UBWC during sys init on unsupported platforms.
>
> Reviewed-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 01/16] media: iris: Skip UBWC configuration when not supported
2026-05-07 6:42 ` [PATCH 01/16] media: iris: Skip UBWC configuration when not supported Dmitry Baryshkov
2026-05-07 8:02 ` Konrad Dybcio
2026-05-07 13:03 ` Vikash Garodia
@ 2026-05-11 5:31 ` Vishnu Reddy
2 siblings, 0 replies; 36+ messages in thread
From: Vishnu Reddy @ 2026-05-11 5:31 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
> index 0d05dd2afc07..6e04175eb904 100644
> --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
> +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c
> @@ -140,6 +140,9 @@ void iris_hfi_gen2_packet_sys_init(struct iris_core *core, struct iris_hfi_heade
> &payload,
> sizeof(u32));
>
> + if (!ubwc->ubwc_enc_version)
> + return;
> +
> payload = qcom_ubwc_macrotile_mode(ubwc) ? 8 : 4;
> iris_hfi_gen2_create_packet(hdr,
> HFI_PROP_UBWC_MAX_CHANNELS,
Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 02/16] media: iris: Filter UBWC raw formats based on hardware capabilities
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
2026-05-07 6:42 ` [PATCH 01/16] media: iris: Skip UBWC configuration when not supported Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 13:04 ` Vikash Garodia
2026-05-11 5:36 ` Vishnu Reddy
2026-05-07 6:42 ` [PATCH 03/16] media: iris: Introduce set_preset_register as a vpu_op Dmitry Baryshkov
` (14 subsequent siblings)
16 siblings, 2 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
The raw formats supported by Iris were previously advertised
unconditionally, assuming UBWC support on all platforms. However, some
platforms do not support UBWC which results in incorrect format
capability exposure.
Use the UBWC configuration provided by the platform to dynamically
filter raw formats at runtime. If UBWC is not supported, UBWC-based
formats are omitted from the advertised capability list, while linear
formats remain available.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vdec.c | 9 +++++++++
drivers/media/platform/qcom/iris/iris_venc.c | 9 +++++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/platform/qcom/iris/iris_vdec.c
index ff8d664558af..bd44e6437480 100644
--- a/drivers/media/platform/qcom/iris/iris_vdec.c
+++ b/drivers/media/platform/qcom/iris/iris_vdec.c
@@ -3,6 +3,7 @@
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
+#include <linux/soc/qcom/ubwc.h>
#include <media/v4l2-event.h>
#include <media/v4l2-mem2mem.h>
@@ -74,6 +75,7 @@ static const u32 iris_vdec_formats_cap[] = {
static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type)
{
+ const struct qcom_ubwc_cfg_data *ubwc = inst->core->ubwc_cfg;
unsigned int size, i;
const u32 *fmt;
@@ -85,6 +87,9 @@ static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type)
case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
fmt = iris_vdec_formats_cap;
size = ARRAY_SIZE(iris_vdec_formats_cap);
+ /* Last format is UBWC; drop it if UBWC is unsupported */
+ if (!ubwc->ubwc_enc_version)
+ size--;
break;
default:
return false;
@@ -100,6 +105,7 @@ static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type)
static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 type)
{
+ const struct qcom_ubwc_cfg_data *ubwc = inst->core->ubwc_cfg;
unsigned int size;
const u32 *fmt;
@@ -111,6 +117,9 @@ static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 type)
case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
fmt = iris_vdec_formats_cap;
size = ARRAY_SIZE(iris_vdec_formats_cap);
+ /* Last format is UBWC; drop it if UBWC is unsupported */
+ if (!ubwc->ubwc_enc_version)
+ size--;
break;
default:
return 0;
diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/platform/qcom/iris/iris_venc.c
index 2398992d0596..c41f4103ccc3 100644
--- a/drivers/media/platform/qcom/iris/iris_venc.c
+++ b/drivers/media/platform/qcom/iris/iris_venc.c
@@ -3,6 +3,7 @@
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
+#include <linux/soc/qcom/ubwc.h>
#include <media/v4l2-event.h>
#include <media/v4l2-mem2mem.h>
@@ -97,6 +98,7 @@ static const u32 iris_venc_formats_out[] = {
static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type)
{
+ const struct qcom_ubwc_cfg_data *ubwc = inst->core->ubwc_cfg;
unsigned int size, i;
const u32 *fmt;
@@ -104,6 +106,9 @@ static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type)
case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
fmt = iris_venc_formats_out;
size = ARRAY_SIZE(iris_venc_formats_out);
+ /* Last format is UBWC; drop it if UBWC is unsupported */
+ if (!ubwc->ubwc_enc_version)
+ size--;
break;
case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
fmt = iris_venc_formats_cap;
@@ -123,6 +128,7 @@ static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type)
static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 type)
{
+ const struct qcom_ubwc_cfg_data *ubwc = inst->core->ubwc_cfg;
unsigned int size;
const u32 *fmt;
@@ -130,6 +136,9 @@ static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 type)
case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
fmt = iris_venc_formats_out;
size = ARRAY_SIZE(iris_venc_formats_out);
+ /* Last format is UBWC; drop it if UBWC is unsupported */
+ if (!ubwc->ubwc_enc_version)
+ size--;
break;
case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
fmt = iris_venc_formats_cap;
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 02/16] media: iris: Filter UBWC raw formats based on hardware capabilities
2026-05-07 6:42 ` [PATCH 02/16] media: iris: Filter UBWC raw formats based on hardware capabilities Dmitry Baryshkov
@ 2026-05-07 13:04 ` Vikash Garodia
2026-05-11 5:36 ` Vishnu Reddy
1 sibling, 0 replies; 36+ messages in thread
From: Vikash Garodia @ 2026-05-07 13:04 UTC (permalink / raw)
To: Dmitry Baryshkov, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> From: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
>
> The raw formats supported by Iris were previously advertised
> unconditionally, assuming UBWC support on all platforms. However, some
> platforms do not support UBWC which results in incorrect format
> capability exposure.
>
> Use the UBWC configuration provided by the platform to dynamically
> filter raw formats at runtime. If UBWC is not supported, UBWC-based
> formats are omitted from the advertised capability list, while linear
> formats remain available.
>
> Reviewed-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vdec.c | 9 +++++++++
> drivers/media/platform/qcom/iris/iris_venc.c | 9 +++++++++
> 2 files changed, 18 insertions(+)
Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 02/16] media: iris: Filter UBWC raw formats based on hardware capabilities
2026-05-07 6:42 ` [PATCH 02/16] media: iris: Filter UBWC raw formats based on hardware capabilities Dmitry Baryshkov
2026-05-07 13:04 ` Vikash Garodia
@ 2026-05-11 5:36 ` Vishnu Reddy
1 sibling, 0 replies; 36+ messages in thread
From: Vishnu Reddy @ 2026-05-11 5:36 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> @@ -100,6 +105,7 @@ static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type)
>
> static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 type)
> {
> + const struct qcom_ubwc_cfg_data *ubwc = inst->core->ubwc_cfg;
> unsigned int size;
> const u32 *fmt;
>
> @@ -111,6 +117,9 @@ static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 type)
> case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
> fmt = iris_vdec_formats_cap;
> size = ARRAY_SIZE(iris_vdec_formats_cap);
> + /* Last format is UBWC; drop it if UBWC is unsupported */
> + if (!ubwc->ubwc_enc_version)
> + size--;
> break;
> default:
> return 0;
> diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/platform/qcom/iris/iris_venc.c
> index 2398992d0596..c41f4103ccc3 100644
> --- a/drivers/media/platform/qcom/iris/iris_venc.c
> +++ b/drivers/media/platform/qcom/iris/iris_venc.c
> @@ -3,6 +3,7 @@
> * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> +#include <linux/soc/qcom/ubwc.h>
> #include <media/v4l2-event.h>
> #include <media/v4l2-mem2mem.h>
>
> @@ -97,6 +98,7 @@ static const u32 iris_venc_formats_out[] = {
>
> static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type)
> {
> + const struct qcom_ubwc_cfg_data *ubwc = inst->core->ubwc_cfg;
> unsigned int size, i;
> const u32 *fmt;
>
> @@ -104,6 +106,9 @@ static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type)
> case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
> fmt = iris_venc_formats_out;
> size = ARRAY_SIZE(iris_venc_formats_out);
> + /* Last format is UBWC; drop it if UBWC is unsupported */
> + if (!ubwc->ubwc_enc_version)
> + size--;
> break;
> case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
> fmt = iris_venc_formats_cap;
> @@ -123,6 +128,7 @@ static bool check_format(struct iris_inst *inst, u32 pixfmt, u32 type)
>
> static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 type)
> {
> + const struct qcom_ubwc_cfg_data *ubwc = inst->core->ubwc_cfg;
> unsigned int size;
> const u32 *fmt;
>
> @@ -130,6 +136,9 @@ static u32 find_format_by_index(struct iris_inst *inst, u32 index, u32 type)
> case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
> fmt = iris_venc_formats_out;
> size = ARRAY_SIZE(iris_venc_formats_out);
> + /* Last format is UBWC; drop it if UBWC is unsupported */
> + if (!ubwc->ubwc_enc_version)
> + size--;
> break;
> case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
> fmt = iris_venc_formats_cap;
Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 03/16] media: iris: Introduce set_preset_register as a vpu_op
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
2026-05-07 6:42 ` [PATCH 01/16] media: iris: Skip UBWC configuration when not supported Dmitry Baryshkov
2026-05-07 6:42 ` [PATCH 02/16] media: iris: Filter UBWC raw formats based on hardware capabilities Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 13:07 ` Vikash Garodia
2026-05-11 6:36 ` Vishnu Reddy
2026-05-07 6:42 ` [PATCH 04/16] media: iris: Introduce interrupt_init " Dmitry Baryshkov
` (13 subsequent siblings)
16 siblings, 2 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
The set_preset_registers sequence is currently shared across all
supported devices. Starting with Qualcomm QCM2290 (AR50LT), the register
programming would differ.
Move set_preset_register into a vpu_op to allow per-device
customization.
This change prepares the driver for upcoming hardware variants.
No functional change so far for existing devices.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu2.c | 1 +
drivers/media/platform/qcom/iris/iris_vpu3x.c | 3 +++
drivers/media/platform/qcom/iris/iris_vpu4x.c | 1 +
drivers/media/platform/qcom/iris/iris_vpu_common.c | 2 +-
drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 +
5 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c
index 01ef40f38957..d61902c9a213 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu2.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu2.c
@@ -45,4 +45,5 @@ const struct vpu_ops iris_vpu2_ops = {
.power_on_controller = iris_vpu_power_on_controller,
.calc_freq = iris_vpu2_calc_freq,
.set_hwmode = iris_vpu_set_hwmode,
+ .set_preset_registers = iris_vpu_set_preset_registers,
};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index 3dad47be78b5..dc02ced1b931 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -261,6 +261,7 @@ const struct vpu_ops iris_vpu3_ops = {
.power_on_controller = iris_vpu_power_on_controller,
.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
.set_hwmode = iris_vpu_set_hwmode,
+ .set_preset_registers = iris_vpu_set_preset_registers,
};
const struct vpu_ops iris_vpu33_ops = {
@@ -270,6 +271,7 @@ const struct vpu_ops iris_vpu33_ops = {
.power_on_controller = iris_vpu_power_on_controller,
.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
.set_hwmode = iris_vpu_set_hwmode,
+ .set_preset_registers = iris_vpu_set_preset_registers,
};
const struct vpu_ops iris_vpu35_ops = {
@@ -280,4 +282,5 @@ const struct vpu_ops iris_vpu35_ops = {
.program_bootup_registers = iris_vpu35_vpu4x_program_bootup_registers,
.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
.set_hwmode = iris_vpu_set_hwmode,
+ .set_preset_registers = iris_vpu_set_preset_registers,
};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c
index 02e100a4045f..f608a297d4a3 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu4x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c
@@ -368,4 +368,5 @@ const struct vpu_ops iris_vpu4x_ops = {
.program_bootup_registers = iris_vpu35_vpu4x_program_bootup_registers,
.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
.set_hwmode = iris_vpu4x_set_hwmode,
+ .set_preset_registers = iris_vpu_set_preset_registers,
};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index 7bba3b6209c2..ff0070c85ccf 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -472,7 +472,7 @@ int iris_vpu_power_on(struct iris_core *core)
iris_opp_set_rate(core->dev, freq);
- iris_vpu_set_preset_registers(core);
+ core->iris_platform_data->vpu_ops->set_preset_registers(core);
iris_vpu_interrupt_init(core);
core->intr_status = 0;
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
index 09799a375c14..21ed4c9bd5e3 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
@@ -22,6 +22,7 @@ struct vpu_ops {
void (*program_bootup_registers)(struct iris_core *core);
u64 (*calc_freq)(struct iris_inst *inst, size_t data_size);
int (*set_hwmode)(struct iris_core *core);
+ void (*set_preset_registers)(struct iris_core *core);
};
int iris_vpu_boot_firmware(struct iris_core *core);
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 03/16] media: iris: Introduce set_preset_register as a vpu_op
2026-05-07 6:42 ` [PATCH 03/16] media: iris: Introduce set_preset_register as a vpu_op Dmitry Baryshkov
@ 2026-05-07 13:07 ` Vikash Garodia
2026-05-11 6:36 ` Vishnu Reddy
1 sibling, 0 replies; 36+ messages in thread
From: Vikash Garodia @ 2026-05-07 13:07 UTC (permalink / raw)
To: Dmitry Baryshkov, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> From: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
>
> The set_preset_registers sequence is currently shared across all
> supported devices. Starting with Qualcomm QCM2290 (AR50LT), the register
> programming would differ.
>
> Move set_preset_register into a vpu_op to allow per-device
> customization.
>
> This change prepares the driver for upcoming hardware variants.
> No functional change so far for existing devices.
>
> Reviewed-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vpu2.c | 1 +
> drivers/media/platform/qcom/iris/iris_vpu3x.c | 3 +++
> drivers/media/platform/qcom/iris/iris_vpu4x.c | 1 +
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 2 +-
> drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 +
> 5 files changed, 7 insertions(+), 1 deletion(-)
Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 03/16] media: iris: Introduce set_preset_register as a vpu_op
2026-05-07 6:42 ` [PATCH 03/16] media: iris: Introduce set_preset_register as a vpu_op Dmitry Baryshkov
2026-05-07 13:07 ` Vikash Garodia
@ 2026-05-11 6:36 ` Vishnu Reddy
1 sibling, 0 replies; 36+ messages in thread
From: Vishnu Reddy @ 2026-05-11 6:36 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c
> index 02e100a4045f..f608a297d4a3 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c
> @@ -368,4 +368,5 @@ const struct vpu_ops iris_vpu4x_ops = {
> .program_bootup_registers = iris_vpu35_vpu4x_program_bootup_registers,
> .calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
> .set_hwmode = iris_vpu4x_set_hwmode,
> + .set_preset_registers = iris_vpu_set_preset_registers,
> };
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index 7bba3b6209c2..ff0070c85ccf 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -472,7 +472,7 @@ int iris_vpu_power_on(struct iris_core *core)
>
> iris_opp_set_rate(core->dev, freq);
>
> - iris_vpu_set_preset_registers(core);
> + core->iris_platform_data->vpu_ops->set_preset_registers(core);
>
> iris_vpu_interrupt_init(core);
> core->intr_status = 0;
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
> index 09799a375c14..21ed4c9bd5e3 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
> @@ -22,6 +22,7 @@ struct vpu_ops {
> void (*program_bootup_registers)(struct iris_core *core);
> u64 (*calc_freq)(struct iris_inst *inst, size_t data_size);
> int (*set_hwmode)(struct iris_core *core);
> + void (*set_preset_registers)(struct iris_core *core);
> };
>
> int iris_vpu_boot_firmware(struct iris_core *core);
Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 04/16] media: iris: Introduce interrupt_init as a vpu_op
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (2 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 03/16] media: iris: Introduce set_preset_register as a vpu_op Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 13:08 ` Vikash Garodia
2026-05-07 6:42 ` [PATCH 05/16] media: iris: add vpu op hook to disable ARP buffer Dmitry Baryshkov
` (12 subsequent siblings)
16 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
The interrupt_init sequence is currently shared across all supported
devices. Starting with Qualcomm QCM2290 (AR50LT), the register
programming would differ.
Move interrupt_init into a vpu_op to allow per-device customization.
This change prepares the driver for upcoming hardware variants.
No functional change so far for existing devices.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu2.c | 1 +
drivers/media/platform/qcom/iris/iris_vpu3x.c | 3 +++
drivers/media/platform/qcom/iris/iris_vpu4x.c | 1 +
drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++--
drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++
5 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c
index d61902c9a213..d49d22b14753 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu2.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu2.c
@@ -46,4 +46,5 @@ const struct vpu_ops iris_vpu2_ops = {
.calc_freq = iris_vpu2_calc_freq,
.set_hwmode = iris_vpu_set_hwmode,
.set_preset_registers = iris_vpu_set_preset_registers,
+ .interrupt_init = iris_vpu_interrupt_init,
};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
index dc02ced1b931..c3b760730c98 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
@@ -262,6 +262,7 @@ const struct vpu_ops iris_vpu3_ops = {
.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
.set_hwmode = iris_vpu_set_hwmode,
.set_preset_registers = iris_vpu_set_preset_registers,
+ .interrupt_init = iris_vpu_interrupt_init,
};
const struct vpu_ops iris_vpu33_ops = {
@@ -272,6 +273,7 @@ const struct vpu_ops iris_vpu33_ops = {
.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
.set_hwmode = iris_vpu_set_hwmode,
.set_preset_registers = iris_vpu_set_preset_registers,
+ .interrupt_init = iris_vpu_interrupt_init,
};
const struct vpu_ops iris_vpu35_ops = {
@@ -283,4 +285,5 @@ const struct vpu_ops iris_vpu35_ops = {
.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
.set_hwmode = iris_vpu_set_hwmode,
.set_preset_registers = iris_vpu_set_preset_registers,
+ .interrupt_init = iris_vpu_interrupt_init,
};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c
index f608a297d4a3..90ccdc0d2a07 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu4x.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c
@@ -369,4 +369,5 @@ const struct vpu_ops iris_vpu4x_ops = {
.calc_freq = iris_vpu3x_vpu4x_calculate_frequency,
.set_hwmode = iris_vpu4x_set_hwmode,
.set_preset_registers = iris_vpu_set_preset_registers,
+ .interrupt_init = iris_vpu_interrupt_init,
};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index ff0070c85ccf..59e4d68d042f 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -31,7 +31,7 @@
#define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64)
#define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68)
-static void iris_vpu_interrupt_init(struct iris_core *core)
+void iris_vpu_interrupt_init(struct iris_core *core)
{
u32 mask_val;
@@ -474,7 +474,7 @@ int iris_vpu_power_on(struct iris_core *core)
core->iris_platform_data->vpu_ops->set_preset_registers(core);
- iris_vpu_interrupt_init(core);
+ core->iris_platform_data->vpu_ops->interrupt_init(core);
core->intr_status = 0;
enable_irq(core->irq);
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
index 21ed4c9bd5e3..9151545065cd 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
@@ -23,6 +23,7 @@ struct vpu_ops {
u64 (*calc_freq)(struct iris_inst *inst, size_t data_size);
int (*set_hwmode)(struct iris_core *core);
void (*set_preset_registers)(struct iris_core *core);
+ void (*interrupt_init)(struct iris_core *core);
};
int iris_vpu_boot_firmware(struct iris_core *core);
@@ -44,5 +45,6 @@ void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core);
u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size);
void iris_vpu_set_preset_registers(struct iris_core *core);
+void iris_vpu_interrupt_init(struct iris_core *core);
#endif
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 04/16] media: iris: Introduce interrupt_init as a vpu_op
2026-05-07 6:42 ` [PATCH 04/16] media: iris: Introduce interrupt_init " Dmitry Baryshkov
@ 2026-05-07 13:08 ` Vikash Garodia
0 siblings, 0 replies; 36+ messages in thread
From: Vikash Garodia @ 2026-05-07 13:08 UTC (permalink / raw)
To: Dmitry Baryshkov, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> From: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
>
> The interrupt_init sequence is currently shared across all supported
> devices. Starting with Qualcomm QCM2290 (AR50LT), the register
> programming would differ.
>
> Move interrupt_init into a vpu_op to allow per-device customization.
>
> This change prepares the driver for upcoming hardware variants.
> No functional change so far for existing devices.
>
> Reviewed-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vpu2.c | 1 +
> drivers/media/platform/qcom/iris/iris_vpu3x.c | 3 +++
> drivers/media/platform/qcom/iris/iris_vpu4x.c | 1 +
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++--
> drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++
> 5 files changed, 9 insertions(+), 2 deletions(-)
Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 05/16] media: iris: add vpu op hook to disable ARP buffer
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (3 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 04/16] media: iris: Introduce interrupt_init " Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 13:14 ` Vikash Garodia
2026-05-11 5:52 ` Vishnu Reddy
2026-05-07 6:42 ` [PATCH 06/16] media: iris: Add platform data field for watchdog interrupt mask Dmitry Baryshkov
` (11 subsequent siblings)
16 siblings, 2 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
On AR50LT platforms AbsolutelyPerfectRouting (ARP) needs to be disabled
so firmware can configure the ARP internal buffer as non-secure for
encoder usage. In preparation of adding support for AR50LT platforms,
add an optional disable_arp callback to the VPU ops and invoke it from
core init and resume paths.
No functional change for existing platforms.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_core.c | 4 ++++
drivers/media/platform/qcom/iris/iris_hfi_common.c | 4 ++++
drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/platform/qcom/iris/iris_core.c
index 52bf56e517f9..bd22076f3557 100644
--- a/drivers/media/platform/qcom/iris/iris_core.c
+++ b/drivers/media/platform/qcom/iris/iris_core.c
@@ -45,6 +45,7 @@ static int iris_wait_for_system_response(struct iris_core *core)
int iris_core_init(struct iris_core *core)
{
+ const struct vpu_ops *vpu_ops = core->iris_platform_data->vpu_ops;
int ret;
mutex_lock(&core->lock);
@@ -78,6 +79,9 @@ int iris_core_init(struct iris_core *core)
if (ret)
goto error_unload_fw;
+ if (vpu_ops->disable_arp)
+ vpu_ops->disable_arp(core);
+
core->iris_firmware_data->init_hfi_ops(core);
ret = iris_hfi_core_init(core);
diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.c b/drivers/media/platform/qcom/iris/iris_hfi_common.c
index 8769ec61f117..8f04f3793d9a 100644
--- a/drivers/media/platform/qcom/iris/iris_hfi_common.c
+++ b/drivers/media/platform/qcom/iris/iris_hfi_common.c
@@ -144,6 +144,7 @@ int iris_hfi_pm_suspend(struct iris_core *core)
int iris_hfi_pm_resume(struct iris_core *core)
{
+ const struct vpu_ops *vpu_ops = core->iris_platform_data->vpu_ops;
const struct iris_hfi_sys_ops *ops = core->hfi_sys_ops;
int ret;
@@ -163,6 +164,9 @@ int iris_hfi_pm_resume(struct iris_core *core)
if (ret)
goto err_suspend_hw;
+ if (vpu_ops->disable_arp)
+ vpu_ops->disable_arp(core);
+
ret = ops->sys_interframe_powercollapse(core);
if (ret)
goto err_suspend_hw;
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
index 9151545065cd..71d96921ed37 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
@@ -24,6 +24,7 @@ struct vpu_ops {
int (*set_hwmode)(struct iris_core *core);
void (*set_preset_registers)(struct iris_core *core);
void (*interrupt_init)(struct iris_core *core);
+ void (*disable_arp)(struct iris_core *core);
};
int iris_vpu_boot_firmware(struct iris_core *core);
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 05/16] media: iris: add vpu op hook to disable ARP buffer
2026-05-07 6:42 ` [PATCH 05/16] media: iris: add vpu op hook to disable ARP buffer Dmitry Baryshkov
@ 2026-05-07 13:14 ` Vikash Garodia
2026-05-11 5:52 ` Vishnu Reddy
1 sibling, 0 replies; 36+ messages in thread
From: Vikash Garodia @ 2026-05-07 13:14 UTC (permalink / raw)
To: Dmitry Baryshkov, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> From: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
>
> On AR50LT platforms AbsolutelyPerfectRouting (ARP) needs to be disabled
> so firmware can configure the ARP internal buffer as non-secure for
> encoder usage. In preparation of adding support for AR50LT platforms,
> add an optional disable_arp callback to the VPU ops and invoke it from
> core init and resume paths.
>
> No functional change for existing platforms.
>
> Reviewed-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_core.c | 4 ++++
> drivers/media/platform/qcom/iris/iris_hfi_common.c | 4 ++++
> drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 +
> 3 files changed, 9 insertions(+)
Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 05/16] media: iris: add vpu op hook to disable ARP buffer
2026-05-07 6:42 ` [PATCH 05/16] media: iris: add vpu op hook to disable ARP buffer Dmitry Baryshkov
2026-05-07 13:14 ` Vikash Garodia
@ 2026-05-11 5:52 ` Vishnu Reddy
1 sibling, 0 replies; 36+ messages in thread
From: Vishnu Reddy @ 2026-05-11 5:52 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> @@ -144,6 +144,7 @@ int iris_hfi_pm_suspend(struct iris_core *core)
>
> int iris_hfi_pm_resume(struct iris_core *core)
> {
> + const struct vpu_ops *vpu_ops = core->iris_platform_data->vpu_ops;
> const struct iris_hfi_sys_ops *ops = core->hfi_sys_ops;
> int ret;
>
> @@ -163,6 +164,9 @@ int iris_hfi_pm_resume(struct iris_core *core)
> if (ret)
> goto err_suspend_hw;
>
> + if (vpu_ops->disable_arp)
> + vpu_ops->disable_arp(core);
> +
> ret = ops->sys_interframe_powercollapse(core);
> if (ret)
> goto err_suspend_hw;
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
> index 9151545065cd..71d96921ed37 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
> @@ -24,6 +24,7 @@ struct vpu_ops {
> int (*set_hwmode)(struct iris_core *core);
> void (*set_preset_registers)(struct iris_core *core);
> void (*interrupt_init)(struct iris_core *core);
> + void (*disable_arp)(struct iris_core *core);
> };
>
> int iris_vpu_boot_firmware(struct iris_core *core);
Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 06/16] media: iris: Add platform data field for watchdog interrupt mask
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (4 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 05/16] media: iris: add vpu op hook to disable ARP buffer Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 13:16 ` Vikash Garodia
2026-05-11 6:14 ` Vishnu Reddy
2026-05-07 6:42 ` [PATCH 07/16] media: iris: Add platform flag for instantaneous bandwidth voting Dmitry Baryshkov
` (10 subsequent siblings)
16 siblings, 2 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
For AR50LT core, the value of WRAPPER_INTR_STATUS_A2HWD_BMASK differs
from the currently supported VPUs. In preparation for adding AR50LT
support in subsequent patches, introduce a platform data field,
wd_intr_mask, to capture the watchdog interrupt bitmask per platform.
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_platform_common.h | 1 +
drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 4 ++++
drivers/media/platform/qcom/iris/iris_platform_vpu3x.c | 6 ++++++
drivers/media/platform/qcom/iris/iris_vpu_common.c | 8 +++++---
drivers/media/platform/qcom/iris/iris_vpu_register_defines.h | 1 -
5 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 7acb073f7197..51d8faf6fd1a 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -283,6 +283,7 @@ struct iris_platform_data {
u32 tz_cp_config_data_size;
u32 num_vpp_pipe;
bool no_aon;
+ u32 wd_intr_mask;
u32 max_session_count;
/* max number of macroblocks per frame supported */
u32 max_core_mbpf;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
index 8259709ba203..238c7b17ed4f 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
@@ -16,6 +16,8 @@
#include "iris_platform_sc7280.h"
#include "iris_platform_sm8250.h"
+#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
+
const struct iris_firmware_desc iris_vpu20_p1_gen1_desc = {
.firmware_data = &iris_hfi_gen1_data,
.get_vpu_buffer_size = iris_vpu_buf_size,
@@ -94,6 +96,7 @@ const struct iris_platform_data sc7280_data = {
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
.num_vpp_pipe = 1,
.no_aon = true,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
.max_session_count = 16,
.max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256,
/* max spec for SC7280 is 4096x2176@60fps */
@@ -124,6 +127,7 @@ const struct iris_platform_data sm8250_data = {
.tz_cp_config_data = tz_cp_config_vpu2,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
.num_vpp_pipe = 4,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
index 829dc37b4058..6e63f279efbe 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
@@ -17,6 +17,8 @@
#include "iris_platform_sm8650.h"
#include "iris_platform_sm8750.h"
+#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
+
const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = {
.firmware_data = &iris_hfi_gen2_data,
.get_vpu_buffer_size = iris_vpu_buf_size,
@@ -106,6 +108,7 @@ const struct iris_platform_data qcs8300_data = {
.tz_cp_config_data = tz_cp_config_vpu3,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
.num_vpp_pipe = 2,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
.max_session_count = 16,
.max_core_mbpf = ((4096 * 2176) / 256) * 4,
.max_core_mbps = (((3840 * 2176) / 256) * 120),
@@ -135,6 +138,7 @@ const struct iris_platform_data sm8550_data = {
.tz_cp_config_data = tz_cp_config_vpu3,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
.num_vpp_pipe = 4,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
@@ -172,6 +176,7 @@ const struct iris_platform_data sm8650_data = {
.tz_cp_config_data = tz_cp_config_vpu3,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
.num_vpp_pipe = 4,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
@@ -201,6 +206,7 @@ const struct iris_platform_data sm8750_data = {
.tz_cp_config_data = tz_cp_config_vpu3,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
.num_vpp_pipe = 4,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index 59e4d68d042f..b8300195a43b 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -109,11 +109,11 @@ void iris_vpu_raise_interrupt(struct iris_core *core)
void iris_vpu_clear_interrupt(struct iris_core *core)
{
+ u32 wd_intr_mask = core->iris_platform_data->wd_intr_mask;
u32 intr_status, mask;
intr_status = readl(core->reg_base + WRAPPER_INTR_STATUS);
- mask = (WRAPPER_INTR_STATUS_A2H_BMSK |
- WRAPPER_INTR_STATUS_A2HWD_BMSK |
+ mask = (WRAPPER_INTR_STATUS_A2H_BMSK | wd_intr_mask |
CTRL_INIT_IDLE_MSG_BMSK);
if (intr_status & mask)
@@ -124,7 +124,9 @@ void iris_vpu_clear_interrupt(struct iris_core *core)
int iris_vpu_watchdog(struct iris_core *core, u32 intr_status)
{
- if (intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK) {
+ u32 wd_intr_mask = core->iris_platform_data->wd_intr_mask;
+
+ if (intr_status & wd_intr_mask) {
dev_err(core->dev, "received watchdog interrupt\n");
return -ETIME;
}
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
index 72168b9ffa73..4fffa094c52f 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
@@ -41,7 +41,6 @@
#define MSK_CORE_POWER_ON BIT(1)
#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C)
-#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2)
#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10)
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 06/16] media: iris: Add platform data field for watchdog interrupt mask
2026-05-07 6:42 ` [PATCH 06/16] media: iris: Add platform data field for watchdog interrupt mask Dmitry Baryshkov
@ 2026-05-07 13:16 ` Vikash Garodia
2026-05-11 6:14 ` Vishnu Reddy
1 sibling, 0 replies; 36+ messages in thread
From: Vikash Garodia @ 2026-05-07 13:16 UTC (permalink / raw)
To: Dmitry Baryshkov, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> From: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
>
> For AR50LT core, the value of WRAPPER_INTR_STATUS_A2HWD_BMASK differs
> from the currently supported VPUs. In preparation for adding AR50LT
> support in subsequent patches, introduce a platform data field,
> wd_intr_mask, to capture the watchdog interrupt bitmask per platform.
>
> Signed-off-by: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_platform_common.h | 1 +
> drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 4 ++++
> drivers/media/platform/qcom/iris/iris_platform_vpu3x.c | 6 ++++++
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 8 +++++---
> drivers/media/platform/qcom/iris/iris_vpu_register_defines.h | 1 -
> 5 files changed, 16 insertions(+), 4 deletions(-)
Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 06/16] media: iris: Add platform data field for watchdog interrupt mask
2026-05-07 6:42 ` [PATCH 06/16] media: iris: Add platform data field for watchdog interrupt mask Dmitry Baryshkov
2026-05-07 13:16 ` Vikash Garodia
@ 2026-05-11 6:14 ` Vishnu Reddy
1 sibling, 0 replies; 36+ messages in thread
From: Vishnu Reddy @ 2026-05-11 6:14 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> @@ -124,6 +127,7 @@ const struct iris_platform_data sm8250_data = {
> .tz_cp_config_data = tz_cp_config_vpu2,
> .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
> .num_vpp_pipe = 4,
> + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
> .max_session_count = 16,
> .max_core_mbpf = NUM_MBS_8K,
> .max_core_mbps = ((7680 * 4320) / 256) * 60,
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
> index 829dc37b4058..6e63f279efbe 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
> @@ -17,6 +17,8 @@
> #include "iris_platform_sm8650.h"
> #include "iris_platform_sm8750.h"
>
> +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
> +
> const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = {
> .firmware_data = &iris_hfi_gen2_data,
> .get_vpu_buffer_size = iris_vpu_buf_size,
> @@ -106,6 +108,7 @@ const struct iris_platform_data qcs8300_data = {
> .tz_cp_config_data = tz_cp_config_vpu3,
> .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
> .num_vpp_pipe = 2,
> + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
> .max_session_count = 16,
> .max_core_mbpf = ((4096 * 2176) / 256) * 4,
> .max_core_mbps = (((3840 * 2176) / 256) * 120),
> @@ -135,6 +138,7 @@ const struct iris_platform_data sm8550_data = {
> .tz_cp_config_data = tz_cp_config_vpu3,
> .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
> .num_vpp_pipe = 4,
> + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
> .max_session_count = 16,
> .max_core_mbpf = NUM_MBS_8K * 2,
> .max_core_mbps = ((7680 * 4320) / 256) * 60,
> @@ -172,6 +176,7 @@ const struct iris_platform_data sm8650_data = {
> .tz_cp_config_data = tz_cp_config_vpu3,
> .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
> .num_vpp_pipe = 4,
> + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
> .max_session_count = 16,
> .max_core_mbpf = NUM_MBS_8K * 2,
> .max_core_mbps = ((7680 * 4320) / 256) * 60,
> @@ -201,6 +206,7 @@ const struct iris_platform_data sm8750_data = {
> .tz_cp_config_data = tz_cp_config_vpu3,
> .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
> .num_vpp_pipe = 4,
> + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
> .max_session_count = 16,
> .max_core_mbpf = NUM_MBS_8K * 2,
> .max_core_mbps = ((7680 * 4320) / 256) * 60,
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index 59e4d68d042f..b8300195a43b 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -109,11 +109,11 @@ void iris_vpu_raise_interrupt(struct iris_core *core)
>
> void iris_vpu_clear_interrupt(struct iris_core *core)
> {
> + u32 wd_intr_mask = core->iris_platform_data->wd_intr_mask;
> u32 intr_status, mask;
>
> intr_status = readl(core->reg_base + WRAPPER_INTR_STATUS);
> - mask = (WRAPPER_INTR_STATUS_A2H_BMSK |
> - WRAPPER_INTR_STATUS_A2HWD_BMSK |
> + mask = (WRAPPER_INTR_STATUS_A2H_BMSK | wd_intr_mask |
> CTRL_INIT_IDLE_MSG_BMSK);
>
> if (intr_status & mask)
> @@ -124,7 +124,9 @@ void iris_vpu_clear_interrupt(struct iris_core *core)
>
> int iris_vpu_watchdog(struct iris_core *core, u32 intr_status)
> {
> - if (intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK) {
> + u32 wd_intr_mask = core->iris_platform_data->wd_intr_mask;
> +
> + if (intr_status & wd_intr_mask) {
> dev_err(core->dev, "received watchdog interrupt\n");
> return -ETIME;
> }
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> index 72168b9ffa73..4fffa094c52f 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> @@ -41,7 +41,6 @@
> #define MSK_CORE_POWER_ON BIT(1)
>
> #define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C)
> -#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
> #define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2)
>
> #define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10)
Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 07/16] media: iris: Add platform flag for instantaneous bandwidth voting
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (5 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 06/16] media: iris: Add platform data field for watchdog interrupt mask Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 13:21 ` Vikash Garodia
2026-05-07 6:42 ` [PATCH 08/16] media: iris: skip PIPE if it is not supported by the platform Dmitry Baryshkov
` (9 subsequent siblings)
16 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
AR50LT require explicit instantaneous bandwidth (IB) voting in addition
to average bandwidth (AB) when configuring interconnect QoS. This
requirement is due to QSB (Qualcomm System Bus) 128b to
QNS ( Qualcomm Network Switch) 256b conversion at video noc in AR50LT
which is not needed for other IRIS cores.
In preparation of adding support for AR50LT core, introduce
platform-configurable IB multiplier and enable IB voting for all SoCs.
Existing platforms default to IB == AB, while AR50LT requires 2x peak
bandwidth.
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_platform_common.h | 1 +
drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 2 ++
drivers/media/platform/qcom/iris/iris_platform_vpu3x.c | 4 ++++
drivers/media/platform/qcom/iris/iris_resources.c | 2 ++
4 files changed, 9 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 51d8faf6fd1a..e1dc226066c1 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -284,6 +284,7 @@ struct iris_platform_data {
u32 num_vpp_pipe;
bool no_aon;
u32 wd_intr_mask;
+ u32 icc_ib_multiplier;
u32 max_session_count;
/* max number of macroblocks per frame supported */
u32 max_core_mbpf;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
index 238c7b17ed4f..c7e6550e964a 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c
@@ -97,6 +97,7 @@ const struct iris_platform_data sc7280_data = {
.num_vpp_pipe = 1,
.no_aon = true,
.wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
+ .icc_ib_multiplier = 1,
.max_session_count = 16,
.max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256,
/* max spec for SC7280 is 4096x2176@60fps */
@@ -128,6 +129,7 @@ const struct iris_platform_data sm8250_data = {
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
.num_vpp_pipe = 4,
.wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
+ .icc_ib_multiplier = 1,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
index 6e63f279efbe..9cd438939e53 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c
@@ -109,6 +109,7 @@ const struct iris_platform_data qcs8300_data = {
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
.num_vpp_pipe = 2,
.wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
+ .icc_ib_multiplier = 1,
.max_session_count = 16,
.max_core_mbpf = ((4096 * 2176) / 256) * 4,
.max_core_mbps = (((3840 * 2176) / 256) * 120),
@@ -139,6 +140,7 @@ const struct iris_platform_data sm8550_data = {
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
.num_vpp_pipe = 4,
.wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
+ .icc_ib_multiplier = 1,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
@@ -177,6 +179,7 @@ const struct iris_platform_data sm8650_data = {
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
.num_vpp_pipe = 4,
.wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
+ .icc_ib_multiplier = 1,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
@@ -207,6 +210,7 @@ const struct iris_platform_data sm8750_data = {
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3),
.num_vpp_pipe = 4,
.wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
+ .icc_ib_multiplier = 1,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K * 2,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c
index 773f6548370a..caeaf199cef7 100644
--- a/drivers/media/platform/qcom/iris/iris_resources.c
+++ b/drivers/media/platform/qcom/iris/iris_resources.c
@@ -18,6 +18,7 @@
int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw)
{
+ u32 icc_ib_multiplier = core->iris_platform_data->icc_ib_multiplier;
unsigned long bw_kbps = 0, bw_prev = 0;
const struct icc_info *icc_tbl;
int ret = 0, i;
@@ -36,6 +37,7 @@ int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw)
return ret;
core->icc_tbl[i].avg_bw = bw_kbps;
+ core->icc_tbl[i].peak_bw = bw_kbps * icc_ib_multiplier;
core->power.icc_bw = bw_kbps;
break;
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 07/16] media: iris: Add platform flag for instantaneous bandwidth voting
2026-05-07 6:42 ` [PATCH 07/16] media: iris: Add platform flag for instantaneous bandwidth voting Dmitry Baryshkov
@ 2026-05-07 13:21 ` Vikash Garodia
0 siblings, 0 replies; 36+ messages in thread
From: Vikash Garodia @ 2026-05-07 13:21 UTC (permalink / raw)
To: Dmitry Baryshkov, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> From: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
>
> AR50LT require explicit instantaneous bandwidth (IB) voting in addition
> to average bandwidth (AB) when configuring interconnect QoS. This
> requirement is due to QSB (Qualcomm System Bus) 128b to
> QNS ( Qualcomm Network Switch) 256b conversion at video noc in AR50LT
> which is not needed for other IRIS cores.
>
> In preparation of adding support for AR50LT core, introduce
> platform-configurable IB multiplier and enable IB voting for all SoCs.
> Existing platforms default to IB == AB, while AR50LT requires 2x peak
> bandwidth.
>
> Signed-off-by: Dikshita Agarwal<dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_platform_common.h | 1 +
> drivers/media/platform/qcom/iris/iris_platform_vpu2.c | 2 ++
> drivers/media/platform/qcom/iris/iris_platform_vpu3x.c | 4 ++++
> drivers/media/platform/qcom/iris/iris_resources.c | 2 ++
> 4 files changed, 9 insertions(+)
Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 08/16] media: iris: skip PIPE if it is not supported by the platform
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (6 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 07/16] media: iris: Add platform flag for instantaneous bandwidth voting Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 13:23 ` Vikash Garodia
2026-05-11 6:17 ` Vishnu Reddy
2026-05-07 6:42 ` [PATCH 09/16] media: iris: Add framework support for AR50_LITE video core Dmitry Baryshkov
` (8 subsequent siblings)
16 siblings, 2 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
AR50Lt doesn't support HFI_PROPERTY_PARAM_WORK_ROUTE. Tables for AR50LT
won't have corresponding entry in the capability tables. Let
iris_set_pipe() silently skip propgramming the property if there is no
corresponding capability.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_ctrls.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c
index ef7adac3764d..f438dddc19ba 100644
--- a/drivers/media/platform/qcom/iris/iris_ctrls.c
+++ b/drivers/media/platform/qcom/iris/iris_ctrls.c
@@ -450,6 +450,9 @@ int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
u32 work_route = inst->fw_caps[PIPE].value;
u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
+ if (!hfi_id)
+ return 0;
+
return hfi_ops->session_set_property(inst, hfi_id,
HFI_HOST_FLAGS_NONE,
iris_get_port_info(inst, cap_id),
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 08/16] media: iris: skip PIPE if it is not supported by the platform
2026-05-07 6:42 ` [PATCH 08/16] media: iris: skip PIPE if it is not supported by the platform Dmitry Baryshkov
@ 2026-05-07 13:23 ` Vikash Garodia
2026-05-11 6:17 ` Vishnu Reddy
1 sibling, 0 replies; 36+ messages in thread
From: Vikash Garodia @ 2026-05-07 13:23 UTC (permalink / raw)
To: Dmitry Baryshkov, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> AR50Lt doesn't support HFI_PROPERTY_PARAM_WORK_ROUTE. Tables for AR50LT
> won't have corresponding entry in the capability tables. Let
> iris_set_pipe() silently skip propgramming the property if there is no
> corresponding capability.
>
> Signed-off-by: Dmitry Baryshkov<dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_ctrls.c | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 08/16] media: iris: skip PIPE if it is not supported by the platform
2026-05-07 6:42 ` [PATCH 08/16] media: iris: skip PIPE if it is not supported by the platform Dmitry Baryshkov
2026-05-07 13:23 ` Vikash Garodia
@ 2026-05-11 6:17 ` Vishnu Reddy
1 sibling, 0 replies; 36+ messages in thread
From: Vishnu Reddy @ 2026-05-11 6:17 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/platform/qcom/iris/iris_ctrls.c
> index ef7adac3764d..f438dddc19ba 100644
> --- a/drivers/media/platform/qcom/iris/iris_ctrls.c
> +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c
> @@ -450,6 +450,9 @@ int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
> u32 work_route = inst->fw_caps[PIPE].value;
> u32 hfi_id = inst->fw_caps[cap_id].hfi_id;
>
> + if (!hfi_id)
> + return 0;
> +
> return hfi_ops->session_set_property(inst, hfi_id,
> HFI_HOST_FLAGS_NONE,
> iris_get_port_info(inst, cap_id),
Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 09/16] media: iris: Add framework support for AR50_LITE video core
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (7 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 08/16] media: iris: skip PIPE if it is not supported by the platform Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-11 6:34 ` Vishnu Reddy
2026-05-07 6:42 ` [PATCH 10/16] media: iris: add minimal GET_PROPERTY implementation Dmitry Baryshkov
` (7 subsequent siblings)
16 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Add power sequence for ar5lt core.
Add register handling for ar50lt by hooking up vpu op with ar50lt
specific implemtation or resue from earlier generation wherever
feasible.
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/Makefile | 1 +
.../platform/qcom/iris/iris_platform_common.h | 2 +
drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c | 156 +++++++++++++++++++++
drivers/media/platform/qcom/iris/iris_vpu_common.c | 3 +-
drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 +
5 files changed, 162 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
index 48e415cbc439..f1b204b95694 100644
--- a/drivers/media/platform/qcom/iris/Makefile
+++ b/drivers/media/platform/qcom/iris/Makefile
@@ -26,6 +26,7 @@ qcom-iris-objs += iris_buffer.o \
iris_vpu2.o \
iris_vpu3x.o \
iris_vpu4x.o \
+ iris_vpu_ar50lt.o \
iris_vpu_buffer.o \
iris_vpu_common.o \
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index e1dc226066c1..4a0895bf5720 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -63,6 +63,7 @@ enum platform_clk_type {
IRIS_VPP0_HW_CLK,
IRIS_VPP1_HW_CLK,
IRIS_APV_HW_CLK,
+ IRIS_THROTTLE_CLK,
};
struct platform_clk_data {
@@ -283,6 +284,7 @@ struct iris_platform_data {
u32 tz_cp_config_data_size;
u32 num_vpp_pipe;
bool no_aon;
+ bool no_rpmh;
u32 wd_intr_mask;
u32 icc_ib_multiplier;
u32 max_session_count;
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c
new file mode 100644
index 000000000000..688b57291a81
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/bits.h>
+#include <linux/iopoll.h>
+#include <linux/reset.h>
+
+#include "iris_instance.h"
+#include "iris_vpu_common.h"
+
+#include "iris_vpu_register_defines.h"
+
+#define WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT BIT(3)
+
+#define WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT 0xb0080
+
+#define CPU_CS_VCICMD 0xa0020
+#define CPU_CS_VCICMD_ARP_OFF 0x1
+
+static void iris_vpu_ar50lt_set_preset_registers(struct iris_core *core)
+{
+ writel(0x0, core->reg_base + WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT);
+}
+
+static void iris_vpu_ar50lt_interrupt_init(struct iris_core *core)
+{
+ writel(WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT, core->reg_base + WRAPPER_INTR_MASK);
+}
+
+static void iris_vpu_ar50lt_disable_arp(struct iris_core *core)
+{
+ writel(CPU_CS_VCICMD_ARP_OFF, core->reg_base + CPU_CS_VCICMD);
+}
+
+static int iris_vpu_ar50lt_power_off_controller(struct iris_core *core)
+{
+ iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
+ iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+ iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+
+ return 0;
+}
+
+static void iris_vpu_ar50lt_power_off_hw(struct iris_core *core)
+{
+ dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false);
+ iris_disable_unprepare_clock(core, IRIS_THROTTLE_CLK);
+ iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
+ iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+}
+
+static int iris_vpu_ar50lt_power_on_controller(struct iris_core *core)
+{
+ int ret;
+
+ ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+ if (ret)
+ return ret;
+
+ ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);
+ if (ret)
+ goto err_disable_power;
+
+ ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
+ if (ret && ret != -ENOENT)
+ goto err_disable_ctrl_clock;
+
+ ret = iris_prepare_enable_clock(core, IRIS_AHB_CLK);
+ if (ret)
+ goto err_disable_axi_clock;
+
+ return 0;
+
+err_disable_axi_clock:
+ iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
+err_disable_ctrl_clock:
+ iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
+err_disable_power:
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
+
+ return ret;
+}
+
+static int iris_vpu_ar50lt_power_on_hw(struct iris_core *core)
+{
+ int ret;
+
+ ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+ if (ret)
+ return ret;
+
+ ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
+ if (ret)
+ goto err_disable_power;
+
+ ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK);
+ if (ret)
+ goto err_disable_hw_clock;
+
+ ret = iris_prepare_enable_clock(core, IRIS_THROTTLE_CLK);
+ if (ret && ret != -ENOENT)
+ goto err_disable_hw_ahb_clock;
+
+ return 0;
+
+err_disable_hw_ahb_clock:
+ iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
+err_disable_hw_clock:
+ iris_disable_unprepare_clock(core, IRIS_HW_CLK);
+err_disable_power:
+ iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+
+ return ret;
+}
+
+static u64 iris_vpu_ar50lt_calc_freq(struct iris_inst *inst, size_t data_size)
+{
+ struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
+ struct v4l2_format *inp_f = inst->fmt_src;
+ u32 mbs_per_second, mbpf, height, width;
+ unsigned long vpp_freq, vsp_freq;
+ u32 fps = DEFAULT_FPS;
+
+ width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
+ height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
+
+ mbpf = NUM_MBS_PER_FRAME(height, width);
+ mbs_per_second = mbpf * fps;
+
+ vpp_freq = mbs_per_second * caps->mb_cycles_vpp;
+
+ /* 21 / 20 is overhead factor */
+ vpp_freq += vpp_freq / 20;
+ vsp_freq = mbs_per_second * caps->mb_cycles_vsp;
+
+ /* 10 / 7 is overhead factor */
+ vsp_freq += ((fps * data_size * 8) * 10) / 7;
+
+ return max(vpp_freq, vsp_freq);
+}
+
+const struct vpu_ops iris_vpu_ar50lt_ops = {
+ .power_off_hw = iris_vpu_ar50lt_power_off_hw,
+ .power_on_hw = iris_vpu_ar50lt_power_on_hw,
+ .power_off_controller = iris_vpu_ar50lt_power_off_controller,
+ .power_on_controller = iris_vpu_ar50lt_power_on_controller,
+ .calc_freq = iris_vpu_ar50lt_calc_freq,
+ .set_hwmode = iris_vpu_set_hwmode,
+ .set_preset_registers = iris_vpu_ar50lt_set_preset_registers,
+ .interrupt_init = iris_vpu_ar50lt_interrupt_init,
+ .disable_arp = iris_vpu_ar50lt_disable_arp,
+};
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index b8300195a43b..f3607c0ca847 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -97,7 +97,8 @@ int iris_vpu_boot_firmware(struct iris_core *core)
}
writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN);
- writel(0x0, core->reg_base + CPU_CS_X2RPMH);
+ if (!core->iris_platform_data->no_rpmh)
+ writel(0x0, core->reg_base + CPU_CS_X2RPMH);
return 0;
}
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
index 71d96921ed37..f00e2de5fa53 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
@@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops;
extern const struct vpu_ops iris_vpu33_ops;
extern const struct vpu_ops iris_vpu35_ops;
extern const struct vpu_ops iris_vpu4x_ops;
+extern const struct vpu_ops iris_vpu_ar50lt_ops;
struct vpu_ops {
void (*power_off_hw)(struct iris_core *core);
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 09/16] media: iris: Add framework support for AR50_LITE video core
2026-05-07 6:42 ` [PATCH 09/16] media: iris: Add framework support for AR50_LITE video core Dmitry Baryshkov
@ 2026-05-11 6:34 ` Vishnu Reddy
0 siblings, 0 replies; 36+ messages in thread
From: Vishnu Reddy @ 2026-05-11 6:34 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
>
> Add power sequence for ar5lt core.
> Add register handling for ar50lt by hooking up vpu op with ar50lt
> specific implemtation or resue from earlier generation wherever
> feasible.
>
> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/Makefile | 1 +
> .../platform/qcom/iris/iris_platform_common.h | 2 +
> drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c | 156 +++++++++++++++++++++
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 3 +-
> drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 +
> 5 files changed, 162 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
> index 48e415cbc439..f1b204b95694 100644
> --- a/drivers/media/platform/qcom/iris/Makefile
> +++ b/drivers/media/platform/qcom/iris/Makefile
> @@ -26,6 +26,7 @@ qcom-iris-objs += iris_buffer.o \
> iris_vpu2.o \
> iris_vpu3x.o \
> iris_vpu4x.o \
> + iris_vpu_ar50lt.o \
> iris_vpu_buffer.o \
> iris_vpu_common.o \
>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index e1dc226066c1..4a0895bf5720 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -63,6 +63,7 @@ enum platform_clk_type {
> IRIS_VPP0_HW_CLK,
> IRIS_VPP1_HW_CLK,
> IRIS_APV_HW_CLK,
> + IRIS_THROTTLE_CLK,
> };
>
> struct platform_clk_data {
> @@ -283,6 +284,7 @@ struct iris_platform_data {
> u32 tz_cp_config_data_size;
> u32 num_vpp_pipe;
> bool no_aon;
> + bool no_rpmh;
> u32 wd_intr_mask;
> u32 icc_ib_multiplier;
> u32 max_session_count;
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c
> new file mode 100644
> index 000000000000..688b57291a81
> --- /dev/null
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c
> @@ -0,0 +1,156 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/iopoll.h>
> +#include <linux/reset.h>
> +
> +#include "iris_instance.h"
> +#include "iris_vpu_common.h"
> +
> +#include "iris_vpu_register_defines.h"
> +
> +#define WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT BIT(3)
> +
> +#define WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT 0xb0080
> +
> +#define CPU_CS_VCICMD 0xa0020
> +#define CPU_CS_VCICMD_ARP_OFF 0x1
> +
> +static void iris_vpu_ar50lt_set_preset_registers(struct iris_core *core)
> +{
> + writel(0x0, core->reg_base + WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT);
> +}
> +
> +static void iris_vpu_ar50lt_interrupt_init(struct iris_core *core)
> +{
> + writel(WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT, core->reg_base + WRAPPER_INTR_MASK);
> +}
> +
> +static void iris_vpu_ar50lt_disable_arp(struct iris_core *core)
> +{
> + writel(CPU_CS_VCICMD_ARP_OFF, core->reg_base + CPU_CS_VCICMD);
> +}
> +
> +static int iris_vpu_ar50lt_power_off_controller(struct iris_core *core)
> +{
> + iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
> + iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
> + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> +
> + return 0;
> +}
> +
> +static void iris_vpu_ar50lt_power_off_hw(struct iris_core *core)
> +{
> + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false);
> + iris_disable_unprepare_clock(core, IRIS_THROTTLE_CLK);
> + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
> + iris_disable_unprepare_clock(core, IRIS_HW_CLK);
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
> +}
> +
> +static int iris_vpu_ar50lt_power_on_controller(struct iris_core *core)
> +{
> + int ret;
> +
> + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> + if (ret)
> + return ret;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);
> + if (ret)
> + goto err_disable_power;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
> + if (ret && ret != -ENOENT)
> + goto err_disable_ctrl_clock;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_AHB_CLK);
> + if (ret)
> + goto err_disable_axi_clock;
> +
> + return 0;
> +
> +err_disable_axi_clock:
> + iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
> +err_disable_ctrl_clock:
> + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
> +err_disable_power:
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> +
> + return ret;
> +}
> +
> +static int iris_vpu_ar50lt_power_on_hw(struct iris_core *core)
> +{
> + int ret;
> +
> + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
> + if (ret)
> + return ret;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
> + if (ret)
> + goto err_disable_power;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK);
> + if (ret)
> + goto err_disable_hw_clock;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_THROTTLE_CLK);
> + if (ret && ret != -ENOENT)
> + goto err_disable_hw_ahb_clock;
> +
Why the additional ret != -ENOENT check here? This function is hooked via
iris_vpu_ar50lt_ops and IRIS_THROTTLE_CLK is explicitly defined in the
qcm2290_data clock table, making it a mandatory clock for this platform.
Is there any other platform that uses this same vpu hook but does not have the
throttle clock?
> + return 0;
> +
> +err_disable_hw_ahb_clock:
> + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
> +err_disable_hw_clock:
> + iris_disable_unprepare_clock(core, IRIS_HW_CLK);
> +err_disable_power:
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
> +
> + return ret;
> +}
> +
> +static u64 iris_vpu_ar50lt_calc_freq(struct iris_inst *inst, size_t data_size)
> +{
> + struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
> + struct v4l2_format *inp_f = inst->fmt_src;
> + u32 mbs_per_second, mbpf, height, width;
> + unsigned long vpp_freq, vsp_freq;
> + u32 fps = DEFAULT_FPS;
> +
> + width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
> + height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
> +
> + mbpf = NUM_MBS_PER_FRAME(height, width);
> + mbs_per_second = mbpf * fps;
> +
> + vpp_freq = mbs_per_second * caps->mb_cycles_vpp;
> +
> + /* 21 / 20 is overhead factor */
> + vpp_freq += vpp_freq / 20;
> + vsp_freq = mbs_per_second * caps->mb_cycles_vsp;
> +
> + /* 10 / 7 is overhead factor */
> + vsp_freq += ((fps * data_size * 8) * 10) / 7;
> +
> + return max(vpp_freq, vsp_freq);
> +}
> +
> +const struct vpu_ops iris_vpu_ar50lt_ops = {
> + .power_off_hw = iris_vpu_ar50lt_power_off_hw,
> + .power_on_hw = iris_vpu_ar50lt_power_on_hw,
> + .power_off_controller = iris_vpu_ar50lt_power_off_controller,
> + .power_on_controller = iris_vpu_ar50lt_power_on_controller,
> + .calc_freq = iris_vpu_ar50lt_calc_freq,
> + .set_hwmode = iris_vpu_set_hwmode,
> + .set_preset_registers = iris_vpu_ar50lt_set_preset_registers,
> + .interrupt_init = iris_vpu_ar50lt_interrupt_init,
> + .disable_arp = iris_vpu_ar50lt_disable_arp,
> +};
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index b8300195a43b..f3607c0ca847 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -97,7 +97,8 @@ int iris_vpu_boot_firmware(struct iris_core *core)
> }
>
> writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN);
> - writel(0x0, core->reg_base + CPU_CS_X2RPMH);
> + if (!core->iris_platform_data->no_rpmh)
> + writel(0x0, core->reg_base + CPU_CS_X2RPMH);
>
> return 0;
> }
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
> index 71d96921ed37..f00e2de5fa53 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
> @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops;
> extern const struct vpu_ops iris_vpu33_ops;
> extern const struct vpu_ops iris_vpu35_ops;
> extern const struct vpu_ops iris_vpu4x_ops;
> +extern const struct vpu_ops iris_vpu_ar50lt_ops;
>
> struct vpu_ops {
> void (*power_off_hw)(struct iris_core *core);
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 10/16] media: iris: add minimal GET_PROPERTY implementation
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (8 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 09/16] media: iris: Add framework support for AR50_LITE video core Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 6:42 ` [PATCH 11/16] media: iris: update buffer requirements based on received info Dmitry Baryshkov
` (6 subsequent siblings)
16 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
AR50Lt with the Gen1 firmware requires host to read
HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS property, otherwie it doesn't
update internal data and fails the HFI_CMD_SESSION_LOAD_RESOURCES
command. Implement minimal support for querying the properties from the
firmware.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_hfi_common.h | 1 +
.../platform/qcom/iris/iris_hfi_gen1_command.c | 21 +++++++++++++++++++++
.../platform/qcom/iris/iris_hfi_gen1_defines.h | 15 +++++++++++++++
.../platform/qcom/iris/iris_hfi_gen1_response.c | 6 ++++++
4 files changed, 43 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/media/platform/qcom/iris/iris_hfi_common.h
index a27447eb2519..16099f9a25b6 100644
--- a/drivers/media/platform/qcom/iris/iris_hfi_common.h
+++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h
@@ -121,6 +121,7 @@ struct iris_hfi_session_ops {
int (*session_set_property)(struct iris_inst *inst,
u32 packet_type, u32 flag, u32 plane, u32 payload_type,
void *payload, u32 payload_size);
+ int (*session_get_property)(struct iris_inst *inst, u32 packet_type);
int (*session_open)(struct iris_inst *inst);
int (*session_start)(struct iris_inst *inst, u32 plane);
int (*session_queue_buf)(struct iris_inst *inst, struct iris_buffer *buffer);
diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
index 83373862655f..4e17fa3c602f 100644
--- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
+++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c
@@ -1063,10 +1063,31 @@ static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst, u32 p
return 0;
}
+static int iris_hfi_gen1_session_get_property(struct iris_inst *inst, u32 packet_type)
+{
+ struct hfi_session_get_property_pkt pkt;
+ int ret;
+
+ pkt.shdr.hdr.size = sizeof(pkt);
+ pkt.shdr.hdr.pkt_type = HFI_CMD_SESSION_GET_PROPERTY;
+ pkt.shdr.session_id = inst->session_id;
+ pkt.num_properties = 1;
+ pkt.data = packet_type;
+
+ reinit_completion(&inst->completion);
+
+ ret = iris_hfi_queue_cmd_write(inst->core, &pkt, pkt.shdr.hdr.size);
+ if (ret)
+ return ret;
+
+ return iris_wait_for_session_response(inst, false);
+}
+
static const struct iris_hfi_session_ops iris_hfi_gen1_session_ops = {
.session_open = iris_hfi_gen1_session_open,
.session_set_config_params = iris_hfi_gen1_session_set_config_params,
.session_set_property = iris_hfi_gen1_session_set_property,
+ .session_get_property = iris_hfi_gen1_session_get_property,
.session_start = iris_hfi_gen1_session_start,
.session_queue_buf = iris_hfi_gen1_session_queue_buffer,
.session_release_buf = iris_hfi_gen1_session_unset_buffers,
diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h
index 42226ccee3d9..1b770e830c58 100644
--- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h
+++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h
@@ -35,6 +35,7 @@
#define HFI_CMD_SESSION_EMPTY_BUFFER 0x211004
#define HFI_CMD_SESSION_FILL_BUFFER 0x211005
#define HFI_CMD_SESSION_FLUSH 0x211008
+#define HFI_CMD_SESSION_GET_PROPERTY 0x211009
#define HFI_CMD_SESSION_RELEASE_BUFFERS 0x21100b
#define HFI_CMD_SESSION_RELEASE_RESOURCES 0x21100c
#define HFI_CMD_SESSION_CONTINUE 0x21100d
@@ -113,6 +114,7 @@
#define HFI_MSG_SESSION_FLUSH 0x221006
#define HFI_MSG_SESSION_EMPTY_BUFFER 0x221007
#define HFI_MSG_SESSION_FILL_BUFFER 0x221008
+#define HFI_MSG_SESSION_PROPERTY_INFO 0x221009
#define HFI_MSG_SESSION_RELEASE_RESOURCES 0x22100a
#define HFI_MSG_SESSION_RELEASE_BUFFERS 0x22100c
@@ -186,6 +188,12 @@ struct hfi_session_set_property_pkt {
u32 data[];
};
+struct hfi_session_get_property_pkt {
+ struct hfi_session_hdr_pkt shdr;
+ u32 num_properties;
+ u32 data;
+};
+
struct hfi_sys_pc_prep_pkt {
struct hfi_pkt_hdr hdr;
};
@@ -525,6 +533,13 @@ struct hfi_msg_session_fbd_uncompressed_plane0_pkt {
u32 data[];
};
+struct hfi_msg_session_property_info_pkt {
+ struct hfi_session_hdr_pkt shdr;
+ u32 num_properties;
+ u32 property;
+ u8 data[];
+};
+
struct hfi_msg_session_release_buffers_done_pkt {
struct hfi_msg_session_hdr_pkt shdr;
u32 num_buffers;
diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
index bfd7495bf44f..23fc7194b1e3 100644
--- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
+++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
@@ -591,6 +591,10 @@ static const struct iris_hfi_gen1_response_pkt_info pkt_infos[] = {
.pkt = HFI_MSG_SESSION_RELEASE_BUFFERS,
.pkt_sz = sizeof(struct hfi_msg_session_release_buffers_done_pkt),
},
+ {
+ .pkt = HFI_MSG_SESSION_PROPERTY_INFO,
+ .pkt_sz = sizeof(struct hfi_msg_session_property_info_pkt),
+ },
};
static void iris_hfi_gen1_handle_response(struct iris_core *core, void *response)
@@ -652,6 +656,8 @@ static void iris_hfi_gen1_handle_response(struct iris_core *core, void *response
iris_hfi_gen1_session_etb_done(inst, hdr);
} else if (hdr->pkt_type == HFI_MSG_SESSION_FILL_BUFFER) {
iris_hfi_gen1_session_ftb_done(inst, hdr);
+ } else if (hdr->pkt_type == HFI_MSG_SESSION_PROPERTY_INFO) {
+ complete(&inst->completion);
} else {
struct hfi_msg_session_hdr_pkt *shdr;
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 11/16] media: iris: update buffer requirements based on received info
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (9 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 10/16] media: iris: add minimal GET_PROPERTY implementation Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 6:42 ` [PATCH 12/16] media: iris: implement support for the Agatti platform Dmitry Baryshkov
` (5 subsequent siblings)
16 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
Upon receiving data for HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS the
driver should update buffer sizes and counts from the received data.
Implement corresponding functionality updating buffers data. This will
be used for upcoming support of AR50Lt platforms with Gen1 firmware.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
.../platform/qcom/iris/iris_hfi_gen1_response.c | 74 +++++++++++++++++++++-
1 file changed, 73 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
index 23fc7194b1e3..ee996eb1f41f 100644
--- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
+++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c
@@ -533,6 +533,78 @@ static void iris_hfi_gen1_session_ftb_done(struct iris_inst *inst, void *packet)
dev_err(core->dev, "error in ftb done\n");
}
+static enum iris_buffer_type iris_hfi_gen1_buf_type(struct iris_inst *inst, u32 type)
+{
+ switch (type) {
+ case HFI_BUFFER_INPUT:
+ return BUF_INPUT;
+ case HFI_BUFFER_OUTPUT:
+ if (iris_split_mode_enabled(inst))
+ return BUF_DPB;
+ return BUF_OUTPUT;
+ case HFI_BUFFER_OUTPUT2:
+ if (iris_split_mode_enabled(inst))
+ return BUF_OUTPUT;
+ return BUF_DPB;
+ case HFI_BUFFER_INTERNAL_PERSIST_1:
+ return BUF_PERSIST;
+ case HFI_BUFFER_INTERNAL_SCRATCH:
+ return BUF_BIN;
+ case HFI_BUFFER_INTERNAL_SCRATCH_1:
+ return BUF_SCRATCH_1;
+ case HFI_BUFFER_INTERNAL_SCRATCH_2:
+ return BUF_SCRATCH_2;
+ case HFI_BUFFER_INTERNAL_PERSIST:
+ return BUF_ARP;
+ default:
+ return -EINVAL;
+ }
+}
+
+static void iris_hfi_gen1_session_buffer_requirements(struct iris_inst *inst,
+ void *data, size_t size)
+{
+ struct hfi_buffer_requirements *req;
+
+ if (!size || size % sizeof(*req))
+ return;
+
+ for (req = data; size; size -= sizeof(*req), req++) {
+ enum iris_buffer_type type = iris_hfi_gen1_buf_type(inst, req->type);
+
+ if (type == -EINVAL)
+ continue;
+
+ inst->buffers[type].min_count = req->hold_count;
+ inst->buffers[type].size = req->size;
+
+ if (type == BUF_OUTPUT)
+ inst->fw_min_count = req->count_actual;
+ }
+}
+
+static void iris_hfi_gen1_session_property_info(struct iris_inst *inst, void *packet)
+{
+ struct hfi_msg_session_property_info_pkt *pkt = packet;
+
+ if (!pkt->num_properties) {
+ dev_err(inst->core->dev, "error, no properties\n");
+ goto out;
+ }
+
+ switch (pkt->property) {
+ case HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS:
+ iris_hfi_gen1_session_buffer_requirements(inst, pkt->data,
+ pkt->shdr.hdr.size - sizeof(*pkt));
+ break;
+ default:
+ dev_warn(inst->core->dev, "unknown property id: %x\n", pkt->property);
+ }
+
+out:
+ complete(&inst->completion);
+}
+
struct iris_hfi_gen1_response_pkt_info {
u32 pkt;
u32 pkt_sz;
@@ -657,7 +729,7 @@ static void iris_hfi_gen1_handle_response(struct iris_core *core, void *response
} else if (hdr->pkt_type == HFI_MSG_SESSION_FILL_BUFFER) {
iris_hfi_gen1_session_ftb_done(inst, hdr);
} else if (hdr->pkt_type == HFI_MSG_SESSION_PROPERTY_INFO) {
- complete(&inst->completion);
+ iris_hfi_gen1_session_property_info(inst, hdr);
} else {
struct hfi_msg_session_hdr_pkt *shdr;
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 12/16] media: iris: implement support for the Agatti platform
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (10 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 11/16] media: iris: update buffer requirements based on received info Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-08 7:27 ` Vishnu Reddy
2026-05-07 6:42 ` [PATCH 13/16] media: iris: Introduce buffer size calculations for AR50LT Dmitry Baryshkov
` (4 subsequent siblings)
16 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
Port support for the AR50Lt video codec core (present for example on the
Agatti platform) to the Iris driver. Unlike more recent cores this
generation doesn't have the PIPE property (as it always has only one
pipe). Also, unlike newer platforms, buffer sizes are requested from the
firmware instead of being calculated by the driver.
Co-developed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/Makefile | 1 +
drivers/media/platform/qcom/iris/iris_hfi_gen1.c | 227 +++++++++++++++++++++
.../platform/qcom/iris/iris_platform_common.h | 6 +
.../platform/qcom/iris/iris_platform_vpu_ar50lt.c | 111 ++++++++++
drivers/media/platform/qcom/iris/iris_probe.c | 4 +
drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 13 ++
drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 1 +
7 files changed, 363 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
index f1b204b95694..bbd1f724963e 100644
--- a/drivers/media/platform/qcom/iris/Makefile
+++ b/drivers/media/platform/qcom/iris/Makefile
@@ -14,6 +14,7 @@ qcom-iris-objs += iris_buffer.o \
iris_hfi_queue.o \
iris_platform_vpu2.o \
iris_platform_vpu3x.o \
+ iris_platform_vpu_ar50lt.o \
iris_power.o \
iris_probe.o \
iris_resources.o \
diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c
index 60f51a1ba941..39f757b6e0a3 100644
--- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c
+++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c
@@ -284,3 +284,230 @@ const struct iris_firmware_data iris_hfi_gen1_data = {
.enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
.enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
};
+
+static struct platform_inst_fw_cap iris_inst_fw_cap_gen1_ar50lt_dec[] = {
+ {
+ .cap_id = STAGE,
+ .min = STAGE_1,
+ .max = STAGE_2,
+ .step_or_mask = 1,
+ .value = STAGE_2,
+ .hfi_id = HFI_PROPERTY_PARAM_WORK_MODE,
+ .set = iris_set_stage,
+ },
+};
+
+static const struct platform_inst_fw_cap inst_fw_cap_gen1_ar50lt_enc[] = {
+ {
+ .cap_id = STAGE,
+ .min = STAGE_1,
+ .max = STAGE_2,
+ .step_or_mask = 1,
+ .value = STAGE_2,
+ .hfi_id = HFI_PROPERTY_PARAM_WORK_MODE,
+ .set = iris_set_stage,
+ },
+ {
+ .cap_id = PROFILE_H264,
+ .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
+ .max = V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH),
+ .value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
+ .hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_profile_level_gen1,
+ },
+ {
+ .cap_id = PROFILE_HEVC,
+ .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
+ .value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ .hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_profile_level_gen1,
+ },
+ {
+ .cap_id = LEVEL_H264,
+ .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
+ .max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2),
+ .value = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
+ .hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_profile_level_gen1,
+ },
+ {
+ .cap_id = LEVEL_HEVC,
+ .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
+ .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1),
+ .value = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
+ .hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_profile_level_gen1,
+ },
+ {
+ .cap_id = HEADER_MODE,
+ .min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
+ .max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) |
+ BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
+ .value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
+ .hfi_id = HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_header_mode_gen1,
+ },
+ {
+ .cap_id = BITRATE,
+ .min = BITRATE_MIN,
+ .max = BITRATE_MAX_AR50LT,
+ .step_or_mask = BITRATE_STEP,
+ .value = BITRATE_DEFAULT_AR50LT,
+ .hfi_id = HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+ CAP_FLAG_DYNAMIC_ALLOWED,
+ .set = iris_set_bitrate,
+ },
+ {
+ .cap_id = BITRATE_MODE,
+ .min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
+ .max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
+ BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR),
+ .value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
+ .hfi_id = HFI_PROPERTY_PARAM_VENC_RATE_CONTROL,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_bitrate_mode_gen1,
+ },
+ {
+ .cap_id = FRAME_SKIP_MODE,
+ .min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
+ .max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) |
+ BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT),
+ .value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ },
+ {
+ .cap_id = FRAME_RC_ENABLE,
+ .min = 0,
+ .max = 1,
+ .step_or_mask = 1,
+ .value = 1,
+ },
+ {
+ .cap_id = GOP_SIZE,
+ .min = 0,
+ .max = (1 << 16) - 1,
+ .step_or_mask = 1,
+ .value = 30,
+ .set = iris_set_u32
+ },
+ {
+ .cap_id = ENTROPY_MODE,
+ .min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
+ .max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
+ BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC),
+ .value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
+ .hfi_id = HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_entropy_mode_gen1,
+ },
+ {
+ .cap_id = MIN_FRAME_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MIN_QP_8BIT_AR50LT,
+ .hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2,
+ .flags = CAP_FLAG_OUTPUT_PORT,
+ .set = iris_set_qp_range,
+ },
+ {
+ .cap_id = MIN_FRAME_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP_HEVC,
+ .step_or_mask = 1,
+ .value = MIN_QP_8BIT_AR50LT,
+ .hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2,
+ .flags = CAP_FLAG_OUTPUT_PORT,
+ .set = iris_set_qp_range,
+ },
+ {
+ .cap_id = MAX_FRAME_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MAX_QP,
+ .hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2,
+ .flags = CAP_FLAG_OUTPUT_PORT,
+ .set = iris_set_qp_range,
+ },
+ {
+ .cap_id = MAX_FRAME_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP_HEVC,
+ .step_or_mask = 1,
+ .value = MAX_QP_HEVC,
+ .hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2,
+ .flags = CAP_FLAG_OUTPUT_PORT,
+ .set = iris_set_qp_range,
+ },
+};
+
+static const u32 iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl[] = {
+ BUF_BIN,
+ BUF_SCRATCH_1,
+};
+
+const struct iris_firmware_data iris_hfi_gen1_ar50lt_data = {
+ .init_hfi_ops = &iris_hfi_gen1_sys_ops_init,
+
+ .inst_fw_caps_dec = iris_inst_fw_cap_gen1_ar50lt_dec,
+ .inst_fw_caps_dec_size = ARRAY_SIZE(iris_inst_fw_cap_gen1_ar50lt_dec),
+ .inst_fw_caps_enc = inst_fw_cap_gen1_ar50lt_enc,
+ .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_gen1_ar50lt_enc),
+
+ .dec_input_config_params_default =
+ sm8250_vdec_input_config_param_default,
+ .dec_input_config_params_default_size =
+ ARRAY_SIZE(sm8250_vdec_input_config_param_default),
+ .enc_input_config_params = sm8250_venc_input_config_param,
+ .enc_input_config_params_size =
+ ARRAY_SIZE(sm8250_venc_input_config_param),
+
+ .dec_ip_int_buf_tbl = iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl,
+ .dec_ip_int_buf_tbl_size = ARRAY_SIZE(iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl),
+ .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl,
+ .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl),
+
+ .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
+ .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
+};
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 4a0895bf5720..f9763ea51c53 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -29,6 +29,10 @@ struct iris_inst;
#define DEFAULT_QP 20
#define BITRATE_DEFAULT 20000000
+#define BITRATE_MAX_AR50LT 100000000
+#define BITRATE_DEFAULT_AR50LT 20000000
+#define MIN_QP_8BIT_AR50LT 0
+
enum stage_type {
STAGE_1 = 1,
STAGE_2 = 2,
@@ -41,8 +45,10 @@ enum pipe_type {
};
extern const struct iris_firmware_data iris_hfi_gen1_data;
+extern const struct iris_firmware_data iris_hfi_gen1_ar50lt_data;
extern const struct iris_firmware_data iris_hfi_gen2_data;
+extern const struct iris_platform_data qcm2290_data;
extern const struct iris_platform_data qcs8300_data;
extern const struct iris_platform_data sc7280_data;
extern const struct iris_platform_data sm8250_data;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c
new file mode 100644
index 000000000000..76bebe012bd8
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "iris_core.h"
+#include "iris_ctrls.h"
+#include "iris_hfi_gen2.h"
+#include "iris_hfi_gen2_defines.h"
+#include "iris_platform_common.h"
+#include "iris_vpu_buffer.h"
+#include "iris_vpu_common.h"
+
+#define WRAPPER_INTR_STATUS_A2HWD_BMSK 0x10
+
+const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen1_s6_desc = {
+ .firmware_data = &iris_hfi_gen1_ar50lt_data,
+ .get_vpu_buffer_size = iris_vpu_ar50lt_gen1_buf_size,
+ .fwname = "qcom/venus-6.0/venus.mbn",
+};
+
+static const u32 iris_fmts_ar50lt_dec[] = {
+ [IRIS_FMT_H264] = V4L2_PIX_FMT_H264,
+ [IRIS_FMT_HEVC] = V4L2_PIX_FMT_HEVC,
+ [IRIS_FMT_VP9] = V4L2_PIX_FMT_VP9,
+};
+
+static const struct bw_info iris_bw_table_dec_ar50lt[] = {
+ { ((1920 * 1080) / 256) * 60, 1564000, },
+ { ((1920 * 1080) / 256) * 30, 791000, },
+ { ((1280 * 720) / 256) * 60, 688000, },
+ { ((1280 * 720) / 256) * 30, 347000, },
+};
+
+static const struct icc_info iris_icc_info_ar50lt[] = {
+ { "cpu-cfg", 1000, 1000 },
+ { "video-mem", 1000, 6500000 },
+};
+
+static const char * const iris_pmdomain_table_ar50lt[] = { "venus", "vcodec0" };
+
+static const char * const iris_opp_pd_table_ar50lt[] = { "cx" };
+
+static const struct platform_clk_data iris_clk_table_ar50lt[] = {
+ {IRIS_CTRL_CLK, "core" },
+ {IRIS_AXI_CLK, "iface" },
+ {IRIS_AHB_CLK, "bus" },
+ {IRIS_HW_CLK, "vcodec0_core" },
+ {IRIS_HW_AHB_CLK, "vcodec0_bus" },
+ {IRIS_THROTTLE_CLK, "throttle" },
+};
+
+static const char * const iris_opp_clk_table_ar50lt[] = {
+ "vcodec0_core",
+ NULL,
+};
+
+static const struct tz_cp_config tz_cp_config_ar50lt[] = {
+ {
+ .cp_start = 0,
+ .cp_size = 0x25800000,
+ .cp_nonpixel_start = 0x01000000,
+ .cp_nonpixel_size = 0x24800000,
+ },
+};
+
+static struct platform_inst_caps platform_inst_cap_ar50lt = {
+ .min_frame_width = 128,
+ .max_frame_width = 1920,
+ .min_frame_height = 128,
+ .max_frame_height = 1920,
+ .max_mbpf = (1920 * 1088) / 256,
+ .mb_cycles_vpp = 440,
+ .mb_cycles_fw = 733003,
+ .mb_cycles_fw_vpp = 225975,
+ .num_comv = 0,
+ .max_frame_rate = 120,
+ .max_operating_rate = 120,
+};
+
+const struct iris_platform_data qcm2290_data = {
+ .firmware_desc_gen1 = &iris_vpu_ar50lt_p1_gen1_s6_desc,
+ .vpu_ops = &iris_vpu_ar50lt_ops,
+ .icc_tbl = iris_icc_info_ar50lt,
+ .icc_tbl_size = ARRAY_SIZE(iris_icc_info_ar50lt),
+ .bw_tbl_dec = iris_bw_table_dec_ar50lt,
+ .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_ar50lt),
+ .pmdomain_tbl = iris_pmdomain_table_ar50lt,
+ .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_ar50lt),
+ .opp_pd_tbl = iris_opp_pd_table_ar50lt,
+ .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_ar50lt),
+ .clk_tbl = iris_clk_table_ar50lt,
+ .clk_tbl_size = ARRAY_SIZE(iris_clk_table_ar50lt),
+ .opp_clk_tbl = iris_opp_clk_table_ar50lt,
+ /* Upper bound of DMA address range */
+ .dma_mask = 0xe0000000 - 1,
+ .inst_iris_fmts = iris_fmts_ar50lt_dec,
+ .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_ar50lt_dec),
+ .inst_caps = &platform_inst_cap_ar50lt,
+ .tz_cp_config_data = tz_cp_config_ar50lt,
+ .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_ar50lt),
+ .num_vpp_pipe = 1,
+ .no_rpmh = true,
+ .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
+ .icc_ib_multiplier = 2,
+ .max_session_count = 8,
+ .max_core_mbpf = ((1920 * 1088) / 256) * 4,
+ /* Concurrency: 1080p@30 decode + 1080p@30 encode */
+ /* Concurrency: 3 * 1080p@30 decode */
+ .max_core_mbps = (((1920 * 1088) / 256) * 90),
+};
diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index 7211d520eda3..070e09406d89 100644
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -356,6 +356,10 @@ static const struct dev_pm_ops iris_pm_ops = {
};
static const struct of_device_id iris_dt_match[] = {
+ {
+ .compatible = "qcom,qcm2290-venus",
+ .data = &qcm2290_data,
+ },
{
.compatible = "qcom,qcs8300-iris",
.data = &qcs8300_data,
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
index 9270422c1601..125fb2d6960d 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
@@ -2135,6 +2135,19 @@ u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_typ
return size;
}
+u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
+{
+ const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
+ int ret;
+
+ /* return 0 on error to let the driver cope */
+ ret = hfi_ops->session_get_property(inst, HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS);
+ if (ret)
+ return 0;
+
+ return inst->buffers[buffer_type].size;
+}
+
static u32 internal_buffer_count(struct iris_inst *inst,
enum iris_buffer_type buffer_type)
{
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
index 8c0d6b7b5de8..1d07137c70cd 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
@@ -288,6 +288,7 @@ static inline u32 size_av1d_qp(u32 frame_width, u32 frame_height)
u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
+u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type);
#endif
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 12/16] media: iris: implement support for the Agatti platform
2026-05-07 6:42 ` [PATCH 12/16] media: iris: implement support for the Agatti platform Dmitry Baryshkov
@ 2026-05-08 7:27 ` Vishnu Reddy
0 siblings, 0 replies; 36+ messages in thread
From: Vishnu Reddy @ 2026-05-08 7:27 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> Port support for the AR50Lt video codec core (present for example on the
> Agatti platform) to the Iris driver. Unlike more recent cores this
> generation doesn't have the PIPE property (as it always has only one
> pipe). Also, unlike newer platforms, buffer sizes are requested from the
> firmware instead of being calculated by the driver.
>
> Co-developed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/Makefile | 1 +
> drivers/media/platform/qcom/iris/iris_hfi_gen1.c | 227 +++++++++++++++++++++
> .../platform/qcom/iris/iris_platform_common.h | 6 +
> .../platform/qcom/iris/iris_platform_vpu_ar50lt.c | 111 ++++++++++
> drivers/media/platform/qcom/iris/iris_probe.c | 4 +
> drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 13 ++
> drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 1 +
> 7 files changed, 363 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
> index f1b204b95694..bbd1f724963e 100644
> --- a/drivers/media/platform/qcom/iris/Makefile
> +++ b/drivers/media/platform/qcom/iris/Makefile
> @@ -14,6 +14,7 @@ qcom-iris-objs += iris_buffer.o \
> iris_hfi_queue.o \
> iris_platform_vpu2.o \
> iris_platform_vpu3x.o \
> + iris_platform_vpu_ar50lt.o \
> iris_power.o \
> iris_probe.o \
> iris_resources.o \
> diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c
> index 60f51a1ba941..39f757b6e0a3 100644
> --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1.c
> +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1.c
> @@ -284,3 +284,230 @@ const struct iris_firmware_data iris_hfi_gen1_data = {
> .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
> .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
> };
> +
> +static struct platform_inst_fw_cap iris_inst_fw_cap_gen1_ar50lt_dec[] = {
const?
> + {
> + .cap_id = STAGE,
> + .min = STAGE_1,
> + .max = STAGE_2,
> + .step_or_mask = 1,
> + .value = STAGE_2,
> + .hfi_id = HFI_PROPERTY_PARAM_WORK_MODE,
> + .set = iris_set_stage,
> + },
> +};
> +
> +static const struct platform_inst_fw_cap inst_fw_cap_gen1_ar50lt_enc[] = {
> + {
> + .cap_id = STAGE,
> + .min = STAGE_1,
> + .max = STAGE_2,
> + .step_or_mask = 1,
> + .value = STAGE_2,
> + .hfi_id = HFI_PROPERTY_PARAM_WORK_MODE,
> + .set = iris_set_stage,
> + },
> + {
> + .cap_id = PROFILE_H264,
> + .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
> + .max = V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH) |
> + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH),
> + .value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
> + .hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_profile_level_gen1,
> + },
> + {
> + .cap_id = PROFILE_HEVC,
> + .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> + .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
> + .value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> + .hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_profile_level_gen1,
> + },
> + {
> + .cap_id = LEVEL_H264,
> + .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
> + .max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
> + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2),
> + .value = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
> + .hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_profile_level_gen1,
> + },
> + {
> + .cap_id = LEVEL_HEVC,
> + .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> + .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
> + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1),
> + .value = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> + .hfi_id = HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_profile_level_gen1,
> + },
> + {
> + .cap_id = HEADER_MODE,
> + .min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
> + .max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) |
> + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
> + .value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
> + .hfi_id = HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_header_mode_gen1,
> + },
> + {
> + .cap_id = BITRATE,
> + .min = BITRATE_MIN,
> + .max = BITRATE_MAX_AR50LT,
> + .step_or_mask = BITRATE_STEP,
> + .value = BITRATE_DEFAULT_AR50LT,
> + .hfi_id = HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
> + CAP_FLAG_DYNAMIC_ALLOWED,
> + .set = iris_set_bitrate,
> + },
> + {
> + .cap_id = BITRATE_MODE,
> + .min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
> + .max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
> + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR),
> + .value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
> + .hfi_id = HFI_PROPERTY_PARAM_VENC_RATE_CONTROL,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_bitrate_mode_gen1,
> + },
> + {
> + .cap_id = FRAME_SKIP_MODE,
> + .min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
> + .max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) |
> + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT),
> + .value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + },
> + {
> + .cap_id = FRAME_RC_ENABLE,
> + .min = 0,
> + .max = 1,
> + .step_or_mask = 1,
> + .value = 1,
> + },
> + {
> + .cap_id = GOP_SIZE,
> + .min = 0,
> + .max = (1 << 16) - 1,
> + .step_or_mask = 1,
> + .value = 30,
> + .set = iris_set_u32
> + },
> + {
> + .cap_id = ENTROPY_MODE,
> + .min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
> + .max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
> + .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
> + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC),
> + .value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
> + .hfi_id = HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL,
> + .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
> + .set = iris_set_entropy_mode_gen1,
> + },
> + {
> + .cap_id = MIN_FRAME_QP_H264,
> + .min = MIN_QP_8BIT_AR50LT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MIN_QP_8BIT_AR50LT,
> + .hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2,
> + .flags = CAP_FLAG_OUTPUT_PORT,
> + .set = iris_set_qp_range,
> + },
> + {
> + .cap_id = MIN_FRAME_QP_HEVC,
> + .min = MIN_QP_8BIT_AR50LT,
> + .max = MAX_QP_HEVC,
> + .step_or_mask = 1,
> + .value = MIN_QP_8BIT_AR50LT,
> + .hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2,
> + .flags = CAP_FLAG_OUTPUT_PORT,
> + .set = iris_set_qp_range,
> + },
> + {
> + .cap_id = MAX_FRAME_QP_H264,
> + .min = MIN_QP_8BIT_AR50LT,
> + .max = MAX_QP,
> + .step_or_mask = 1,
> + .value = MAX_QP,
> + .hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2,
> + .flags = CAP_FLAG_OUTPUT_PORT,
> + .set = iris_set_qp_range,
> + },
> + {
> + .cap_id = MAX_FRAME_QP_HEVC,
> + .min = MIN_QP_8BIT_AR50LT,
> + .max = MAX_QP_HEVC,
> + .step_or_mask = 1,
> + .value = MAX_QP_HEVC,
> + .hfi_id = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2,
> + .flags = CAP_FLAG_OUTPUT_PORT,
> + .set = iris_set_qp_range,
> + },
> +};
> +
> +static const u32 iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl[] = {
> + BUF_BIN,
> + BUF_SCRATCH_1,
> +};
> +
> +const struct iris_firmware_data iris_hfi_gen1_ar50lt_data = {
> + .init_hfi_ops = &iris_hfi_gen1_sys_ops_init,
> +
> + .inst_fw_caps_dec = iris_inst_fw_cap_gen1_ar50lt_dec,
> + .inst_fw_caps_dec_size = ARRAY_SIZE(iris_inst_fw_cap_gen1_ar50lt_dec),
> + .inst_fw_caps_enc = inst_fw_cap_gen1_ar50lt_enc,
> + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_gen1_ar50lt_enc),
> +
> + .dec_input_config_params_default =
> + sm8250_vdec_input_config_param_default,
> + .dec_input_config_params_default_size =
> + ARRAY_SIZE(sm8250_vdec_input_config_param_default),
> + .enc_input_config_params = sm8250_venc_input_config_param,
> + .enc_input_config_params_size =
> + ARRAY_SIZE(sm8250_venc_input_config_param),
> +
> + .dec_ip_int_buf_tbl = iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl,
> + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl),
> + .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl,
> + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl),
> +
> + .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
> + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
> +};
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index 4a0895bf5720..f9763ea51c53 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -29,6 +29,10 @@ struct iris_inst;
> #define DEFAULT_QP 20
> #define BITRATE_DEFAULT 20000000
>
> +#define BITRATE_MAX_AR50LT 100000000
> +#define BITRATE_DEFAULT_AR50LT 20000000
> +#define MIN_QP_8BIT_AR50LT 0
> +
> enum stage_type {
> STAGE_1 = 1,
> STAGE_2 = 2,
> @@ -41,8 +45,10 @@ enum pipe_type {
> };
>
> extern const struct iris_firmware_data iris_hfi_gen1_data;
> +extern const struct iris_firmware_data iris_hfi_gen1_ar50lt_data;
> extern const struct iris_firmware_data iris_hfi_gen2_data;
>
> +extern const struct iris_platform_data qcm2290_data;
> extern const struct iris_platform_data qcs8300_data;
> extern const struct iris_platform_data sc7280_data;
> extern const struct iris_platform_data sm8250_data;
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c
> new file mode 100644
> index 000000000000..76bebe012bd8
> --- /dev/null
> +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include "iris_core.h"
> +#include "iris_ctrls.h"
> +#include "iris_hfi_gen2.h"
> +#include "iris_hfi_gen2_defines.h"
> +#include "iris_platform_common.h"
> +#include "iris_vpu_buffer.h"
> +#include "iris_vpu_common.h"
> +
> +#define WRAPPER_INTR_STATUS_A2HWD_BMSK 0x10
> +
> +const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen1_s6_desc = {
> + .firmware_data = &iris_hfi_gen1_ar50lt_data,
> + .get_vpu_buffer_size = iris_vpu_ar50lt_gen1_buf_size,
> + .fwname = "qcom/venus-6.0/venus.mbn",
> +};
> +
> +static const u32 iris_fmts_ar50lt_dec[] = {
> + [IRIS_FMT_H264] = V4L2_PIX_FMT_H264,
> + [IRIS_FMT_HEVC] = V4L2_PIX_FMT_HEVC,
> + [IRIS_FMT_VP9] = V4L2_PIX_FMT_VP9,
> +};
> +
> +static const struct bw_info iris_bw_table_dec_ar50lt[] = {
> + { ((1920 * 1080) / 256) * 60, 1564000, },
> + { ((1920 * 1080) / 256) * 30, 791000, },
> + { ((1280 * 720) / 256) * 60, 688000, },
> + { ((1280 * 720) / 256) * 30, 347000, },
> +};
> +
> +static const struct icc_info iris_icc_info_ar50lt[] = {
> + { "cpu-cfg", 1000, 1000 },
> + { "video-mem", 1000, 6500000 },
> +};
> +
> +static const char * const iris_pmdomain_table_ar50lt[] = { "venus", "vcodec0" };
> +
> +static const char * const iris_opp_pd_table_ar50lt[] = { "cx" };
> +
> +static const struct platform_clk_data iris_clk_table_ar50lt[] = {
> + {IRIS_CTRL_CLK, "core" },
> + {IRIS_AXI_CLK, "iface" },
> + {IRIS_AHB_CLK, "bus" },
> + {IRIS_HW_CLK, "vcodec0_core" },
> + {IRIS_HW_AHB_CLK, "vcodec0_bus" },
> + {IRIS_THROTTLE_CLK, "throttle" },
> +};
> +
> +static const char * const iris_opp_clk_table_ar50lt[] = {
> + "vcodec0_core",
> + NULL,
> +};
> +
> +static const struct tz_cp_config tz_cp_config_ar50lt[] = {
> + {
> + .cp_start = 0,
> + .cp_size = 0x25800000,
> + .cp_nonpixel_start = 0x01000000,
> + .cp_nonpixel_size = 0x24800000,
> + },
> +};
> +
> +static struct platform_inst_caps platform_inst_cap_ar50lt = {
> + .min_frame_width = 128,
> + .max_frame_width = 1920,
> + .min_frame_height = 128,
> + .max_frame_height = 1920,
> + .max_mbpf = (1920 * 1088) / 256,
> + .mb_cycles_vpp = 440,
> + .mb_cycles_fw = 733003,
> + .mb_cycles_fw_vpp = 225975,
> + .num_comv = 0,
> + .max_frame_rate = 120,
> + .max_operating_rate = 120,
> +};
> +
> +const struct iris_platform_data qcm2290_data = {
> + .firmware_desc_gen1 = &iris_vpu_ar50lt_p1_gen1_s6_desc,
> + .vpu_ops = &iris_vpu_ar50lt_ops,
> + .icc_tbl = iris_icc_info_ar50lt,
> + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_ar50lt),
> + .bw_tbl_dec = iris_bw_table_dec_ar50lt,
> + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_ar50lt),
> + .pmdomain_tbl = iris_pmdomain_table_ar50lt,
> + .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_ar50lt),
> + .opp_pd_tbl = iris_opp_pd_table_ar50lt,
> + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_ar50lt),
> + .clk_tbl = iris_clk_table_ar50lt,
> + .clk_tbl_size = ARRAY_SIZE(iris_clk_table_ar50lt),
> + .opp_clk_tbl = iris_opp_clk_table_ar50lt,
> + /* Upper bound of DMA address range */
> + .dma_mask = 0xe0000000 - 1,
> + .inst_iris_fmts = iris_fmts_ar50lt_dec,
> + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_ar50lt_dec),
> + .inst_caps = &platform_inst_cap_ar50lt,
> + .tz_cp_config_data = tz_cp_config_ar50lt,
> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_ar50lt),
> + .num_vpp_pipe = 1,
> + .no_rpmh = true,
> + .wd_intr_mask = WRAPPER_INTR_STATUS_A2HWD_BMSK,
> + .icc_ib_multiplier = 2,
> + .max_session_count = 8,
> + .max_core_mbpf = ((1920 * 1088) / 256) * 4,
> + /* Concurrency: 1080p@30 decode + 1080p@30 encode */
> + /* Concurrency: 3 * 1080p@30 decode */
> + .max_core_mbps = (((1920 * 1088) / 256) * 90),
> +};
> diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
> index 7211d520eda3..070e09406d89 100644
> --- a/drivers/media/platform/qcom/iris/iris_probe.c
> +++ b/drivers/media/platform/qcom/iris/iris_probe.c
> @@ -356,6 +356,10 @@ static const struct dev_pm_ops iris_pm_ops = {
> };
>
> static const struct of_device_id iris_dt_match[] = {
> + {
> + .compatible = "qcom,qcm2290-venus",
> + .data = &qcm2290_data,
> + },
> {
> .compatible = "qcom,qcs8300-iris",
> .data = &qcs8300_data,
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
> index 9270422c1601..125fb2d6960d 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
> @@ -2135,6 +2135,19 @@ u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_typ
> return size;
> }
>
> +u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
> +{
> + const struct iris_hfi_session_ops *hfi_ops = inst->hfi_session_ops;
> + int ret;
> +
> + /* return 0 on error to let the driver cope */
> + ret = hfi_ops->session_get_property(inst, HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS);
> + if (ret)
> + return 0;
> +
> + return inst->buffers[buffer_type].size;
> +}
> +
> static u32 internal_buffer_count(struct iris_inst *inst,
> enum iris_buffer_type buffer_type)
> {
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
> index 8c0d6b7b5de8..1d07137c70cd 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
> @@ -288,6 +288,7 @@ static inline u32 size_av1d_qp(u32 frame_width, u32 frame_height)
> u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
> u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
> u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
> +u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
> int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type);
>
> #endif
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 13/16] media: iris: Introduce buffer size calculations for AR50LT
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (11 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 12/16] media: iris: implement support for the Agatti platform Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-08 7:26 ` Vishnu Reddy
2026-05-07 6:42 ` [PATCH 14/16] media: iris: add Gen2 firmware support on the Agatti platform Dmitry Baryshkov
` (3 subsequent siblings)
16 siblings, 1 reply; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Introduces AR50LT buffer size calculation for both encoder and
decoder. Reuse the buffer size calculation which are common, while
adding the AR50LT specific ones separately.
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 401 +++++++++++++++++++++
drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 37 ++
2 files changed, 438 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
index 125fb2d6960d..a1af3bca5dc9 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
@@ -50,6 +50,32 @@ static u32 hfi_buffer_bin_h264d(u32 frame_width, u32 frame_height, u32 num_vpp_p
return size_h264d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes);
}
+static u32 size_h264d_hw_bin_buffer_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
+{
+ u32 size_yuv, size_bin_hdr, size_bin_res;
+
+ size_yuv = ((frame_width * frame_height * 3) >> 1);
+ if (size_yuv <= 1920 * 1088 * 3 / 2) {
+ size_bin_hdr = size_yuv * H264_CABAC_HDR_RATIO_SM_TOT;
+ size_bin_res = size_yuv * H264_CABAC_RES_RATIO_SM_TOT;
+ } else {
+ size_bin_hdr = (size_yuv * 3) / 5;
+ size_bin_res = (size_yuv * 3) / 2;
+ }
+ size_bin_hdr = ALIGN(size_bin_hdr, DMA_ALIGNMENT);
+ size_bin_res = ALIGN(size_bin_res, DMA_ALIGNMENT);
+
+ return size_bin_hdr + size_bin_res;
+}
+
+static u32 hfi_buffer_bin_h264d_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
+{
+ u32 n_aligned_h = ALIGN(frame_height, 16);
+ u32 n_aligned_w = ALIGN(frame_width, 16);
+
+ return size_h264d_hw_bin_buffer_ar50lt(n_aligned_w, n_aligned_h, num_vpp_pipes);
+}
+
static u32 size_av1d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
{
u32 size_yuv, size_bin_hdr, size_bin_res;
@@ -103,6 +129,21 @@ static u32 hfi_buffer_bin_vp9d(u32 frame_width, u32 frame_height, u32 num_vpp_pi
return _size * num_vpp_pipes;
}
+static u32 hfi_buffer_bin_vp9d_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
+{
+ u32 size_yuv, size;
+
+ size_yuv = ALIGN(frame_width, 16) * ALIGN(frame_height, 16) * 3 / 2;
+ size_yuv = ALIGN(size_yuv, DMA_ALIGNMENT);
+
+ size = ALIGN(((((MAX(size_yuv, VPX_DECODER_FRAME_BIN_BUFFER_SIZE)) * 6) / 5) /
+ num_vpp_pipes), DMA_ALIGNMENT) +
+ ALIGN((((MAX(size_yuv, VPX_DECODER_FRAME_BIN_BUFFER_SIZE)) * 4) / num_vpp_pipes),
+ DMA_ALIGNMENT);
+
+ return size * num_vpp_pipes;
+}
+
static u32 hfi_buffer_bin_h265d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
{
u32 n_aligned_w = ALIGN(frame_width, 16);
@@ -111,6 +152,32 @@ static u32 hfi_buffer_bin_h265d(u32 frame_width, u32 frame_height, u32 num_vpp_p
return size_h265d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes);
}
+static u32 size_h265d_hw_bin_buffer_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
+{
+ u32 size_yuv, size_bin_hdr, size_bin_res;
+
+ size_yuv = ((frame_width * frame_height * 3) >> 1);
+ if (size_yuv <= ((BIN_BUFFER_THRESHOLD * 3) >> 1)) {
+ size_bin_hdr = size_yuv * H265_CABAC_HDR_RATIO_SM_TOT;
+ size_bin_res = size_yuv * H265_CABAC_RES_RATIO_SM_TOT;
+ } else {
+ size_bin_hdr = (size_yuv * 41) / 50;
+ size_bin_res = (size_yuv * 59) / 50;
+ }
+ size_bin_hdr = ALIGN(size_bin_hdr, DMA_ALIGNMENT);
+ size_bin_res = ALIGN(size_bin_res, DMA_ALIGNMENT);
+
+ return size_bin_hdr + size_bin_res;
+}
+
+static u32 hfi_buffer_bin_h265d_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
+{
+ u32 n_aligned_w = ALIGN(frame_width, 16);
+ u32 n_aligned_h = ALIGN(frame_height, 16);
+
+ return size_h265d_hw_bin_buffer_ar50lt(n_aligned_w, n_aligned_h, num_vpp_pipes);
+}
+
static u32 hfi_buffer_comv_h264d(u32 frame_width, u32 frame_height, u32 _comv_bufcount)
{
u32 frame_height_in_mbs = DIV_ROUND_UP(frame_height, 16);
@@ -174,6 +241,14 @@ static u32 size_h264d_bse_cmd_buf(u32 frame_height)
SIZE_H264D_BSE_CMD_PER_BUF;
}
+static u32 size_h264d_bse_cmd_buf_ar50lt(u32 frame_height)
+{
+ u32 height = ALIGN(frame_height, 32);
+
+ return min_t(u32, (DIV_ROUND_UP(height, 16) * 12), H264D_MAX_SLICE) *
+ SIZE_H264D_BSE_CMD_PER_BUF;
+}
+
static u32 size_h265d_bse_cmd_buf(u32 frame_width, u32 frame_height)
{
u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
@@ -185,6 +260,18 @@ static u32 size_h265d_bse_cmd_buf(u32 frame_width, u32 frame_height)
return _size;
}
+static u32 size_h265d_bse_cmd_buf_ar50lt(u32 frame_width, u32 frame_height)
+{
+ u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
+ (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) *
+ NUM_HW_PIC_BUF, DMA_ALIGNMENT);
+
+ _size = min_t(u32, _size, H265D_MAX_SLICE_AR50LT + 1);
+ _size = 2 * _size * SIZE_H265D_BSE_CMD_PER_BUF;
+
+ return _size;
+}
+
static u32 hfi_buffer_persist_h265d(u32 rpu_enabled)
{
return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 +
@@ -195,6 +282,13 @@ static u32 hfi_buffer_persist_h265d(u32 rpu_enabled)
DMA_ALIGNMENT);
}
+static u32 hfi_buffer_persist_h265d_ar50lt(void)
+{
+ return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 +
+ H265_NUM_TILE * sizeof(u32) + NUM_HW_PIC_BUF * SIZE_SEI_USERDATA),
+ DMA_ALIGNMENT);
+}
+
static inline
u32 hfi_iris3_vp9d_comv_size(void)
{
@@ -212,6 +306,13 @@ static u32 hfi_buffer_persist_vp9d(void)
HDR10_HIST_EXTRADATA_SIZE;
}
+static u32 hfi_buffer_persist_vp9d_ar50lt(void)
+{
+ return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALIGNMENT) +
+ ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) +
+ ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT);
+}
+
static u32 size_h264d_vpp_cmd_buf(u32 frame_height)
{
u32 size, height = ALIGN(frame_height, 32);
@@ -222,6 +323,16 @@ static u32 size_h264d_vpp_cmd_buf(u32 frame_height)
return size > VPP_CMD_MAX_SIZE ? VPP_CMD_MAX_SIZE : size;
}
+static u32 size_h264d_vpp_cmd_buf_ar50lt(u32 frame_height)
+{
+ u32 size, height = ALIGN(frame_height, 32);
+
+ size = min_t(u32, (DIV_ROUND_UP(height, 16) * 12), H264D_MAX_SLICE) *
+ SIZE_H264D_VPP_CMD_PER_BUF;
+
+ return size > VPP_CMD_MAX_SIZE ? VPP_CMD_MAX_SIZE : size;
+}
+
static u32 hfi_buffer_persist_h264d(void)
{
return ALIGN(SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264 +
@@ -230,6 +341,11 @@ static u32 hfi_buffer_persist_h264d(void)
DMA_ALIGNMENT);
}
+static u32 hfi_buffer_persist_h264d_ar50lt(void)
+{
+ return ALIGN((SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264), DMA_ALIGNMENT);
+}
+
static u32 hfi_buffer_persist_av1d(u32 max_width, u32 max_height, u32 total_ref_count)
{
u32 comv_size, size;
@@ -255,6 +371,17 @@ static u32 hfi_buffer_non_comv_h264d(u32 frame_width, u32 frame_height, u32 num_
return ALIGN(size, DMA_ALIGNMENT);
}
+static u32 hfi_buffer_non_comv_h264d_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
+{
+ u32 size_bse = size_h264d_bse_cmd_buf_ar50lt(frame_height);
+ u32 size_vpp = size_h264d_vpp_cmd_buf_ar50lt(frame_height);
+ u32 size = ALIGN(size_bse, DMA_ALIGNMENT) +
+ ALIGN(size_vpp, DMA_ALIGNMENT) +
+ ALIGN(SIZE_HW_PIC(SIZE_H264D_HW_PIC_T), DMA_ALIGNMENT);
+
+ return ALIGN(size, DMA_ALIGNMENT);
+}
+
static u32 size_h265d_vpp_cmd_buf(u32 frame_width, u32 frame_height)
{
u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
@@ -269,6 +396,20 @@ static u32 size_h265d_vpp_cmd_buf(u32 frame_width, u32 frame_height)
return _size;
}
+static u32 size_h265d_vpp_cmd_buf_ar50lt(u32 frame_width, u32 frame_height)
+{
+ u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
+ (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) *
+ NUM_HW_PIC_BUF, DMA_ALIGNMENT);
+ _size = min_t(u32, _size, H265D_MAX_SLICE_AR50LT + 1);
+ _size = ALIGN(_size, 4);
+ _size = 2 * _size * SIZE_H265D_VPP_CMD_PER_BUF_AR50LT;
+ if (_size > VPP_CMD_MAX_SIZE)
+ _size = VPP_CMD_MAX_SIZE;
+
+ return _size;
+}
+
static u32 hfi_buffer_non_comv_h265d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
{
u32 _size_bse = size_h265d_bse_cmd_buf(frame_width, frame_height);
@@ -285,6 +426,20 @@ static u32 hfi_buffer_non_comv_h265d(u32 frame_width, u32 frame_height, u32 num_
return ALIGN(_size, DMA_ALIGNMENT);
}
+static u32 hfi_buffer_non_comv_h265d_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
+{
+ u32 _size_bse = size_h265d_bse_cmd_buf_ar50lt(frame_width, frame_height);
+ u32 _size_vpp = size_h265d_vpp_cmd_buf_ar50lt(frame_width, frame_height);
+ u32 _size = ALIGN(_size_bse, DMA_ALIGNMENT) +
+ ALIGN(_size_vpp, DMA_ALIGNMENT) +
+ ALIGN(2 * sizeof(u16) *
+ (ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
+ (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS), DMA_ALIGNMENT) +
+ ALIGN(SIZE_HW_PIC(SIZE_H265D_HW_PIC_T), DMA_ALIGNMENT);
+
+ return ALIGN(_size, DMA_ALIGNMENT);
+}
+
static u32 size_vpss_lb(u32 frame_width, u32 frame_height)
{
u32 opb_lb_wr_llb_y_buffer_size, opb_lb_wr_llb_uv_buffer_size;
@@ -317,6 +472,13 @@ u32 size_h265d_lb_fe_top_data(u32 frame_width, u32 frame_height)
(ALIGN(frame_width, 64) + 8) * 2;
}
+static inline
+u32 size_h265d_lb_fe_top_data_ar50lt(u32 frame_width, u32 frame_height)
+{
+ return ALIGN(MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE *
+ (ALIGN(frame_width, 64) + 8), DMA_ALIGNMENT) * 2;
+}
+
static inline
u32 size_h265d_lb_fe_top_ctrl(u32 frame_width, u32 frame_height)
{
@@ -348,6 +510,17 @@ u32 size_h265d_lb_se_left_ctrl(u32 frame_width, u32 frame_height)
MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE));
}
+static inline
+u32 size_h265d_lb_se_left_ctrl_ar50lt(u32 frame_width, u32 frame_height)
+{
+ return max_t(u32, ((frame_height + 16 - 1) / 8) *
+ MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE_AR50LT,
+ max_t(u32, ((frame_height + 32 - 1) / 8) *
+ MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE_AR50LT,
+ ((frame_height + 64 - 1) / 8) *
+ MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT));
+}
+
static inline
u32 size_h265d_lb_pe_top_data(u32 frame_width, u32 frame_height)
{
@@ -355,6 +528,13 @@ u32 size_h265d_lb_pe_top_data(u32 frame_width, u32 frame_height)
(ALIGN(frame_width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS);
}
+static inline
+u32 size_h265d_lb_pe_top_data_ar50lt(u32 frame_width, u32 frame_height)
+{
+ return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE_AR50LT *
+ (ALIGN(frame_width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS);
+}
+
static inline
u32 size_h265d_lb_vsp_top(u32 frame_width, u32 frame_height)
{
@@ -404,6 +584,29 @@ u32 hfi_buffer_line_h265d(u32 frame_width, u32 frame_height, bool is_opb, u32 nu
return ALIGN((_size + vpss_lb_size), DMA_ALIGNMENT);
}
+static inline
+u32 hfi_buffer_line_h265d_ar50lt(u32 frame_width, u32 frame_height, bool is_opb, u32 num_vpp_pipes)
+{
+ u32 size;
+
+ size = ALIGN(size_h265d_lb_fe_top_data_ar50lt(frame_width, frame_height), DMA_ALIGNMENT) +
+ ALIGN(size_h265d_lb_fe_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) +
+ ALIGN(size_h265d_lb_fe_left_ctrl(frame_width, frame_height),
+ DMA_ALIGNMENT) * num_vpp_pipes +
+ ALIGN(size_h265d_lb_se_left_ctrl_ar50lt(frame_width, frame_height),
+ DMA_ALIGNMENT) * num_vpp_pipes +
+ ALIGN(size_h265d_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) +
+ ALIGN(size_h265d_lb_pe_top_data_ar50lt(frame_width, frame_height), DMA_ALIGNMENT) +
+ ALIGN(size_h265d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) +
+ ALIGN(size_h265d_lb_vsp_left(frame_width, frame_height),
+ DMA_ALIGNMENT) * num_vpp_pipes +
+ ALIGN(size_h265d_lb_recon_dma_metadata_wr(frame_width, frame_height),
+ DMA_ALIGNMENT) * 4 +
+ ALIGN(size_h265d_qp(frame_width, frame_height), DMA_ALIGNMENT);
+
+ return ALIGN(size, DMA_ALIGNMENT);
+}
+
static inline
u32 size_vpxd_lb_fe_left_ctrl(u32 frame_width, u32 frame_height)
{
@@ -438,6 +641,17 @@ u32 size_vpxd_lb_se_left_ctrl(u32 frame_width, u32 frame_height)
MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE));
}
+static inline
+u32 size_vpxd_lb_se_left_ctrl_ar50lt(u32 frame_width, u32 frame_height)
+{
+ return max_t(u32, ((frame_height + 15) >> 4) *
+ MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE_AR50LT,
+ max_t(u32, ((frame_height + 31) >> 5) *
+ MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE_AR50LT,
+ ((frame_height + 63) >> 6) *
+ MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT));
+}
+
static inline
u32 size_vpxd_lb_recon_dma_metadata_wr(u32 frame_width, u32 frame_height)
{
@@ -492,6 +706,19 @@ u32 hfi_iris3_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT);
}
+static inline
+u32 hfi_ar50lt_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
+{
+ return ALIGN(size_vpxd_lb_fe_left_ctrl(frame_width, frame_height), DMA_ALIGNMENT) *
+ num_vpp_pipes +
+ ALIGN(size_vpxd_lb_se_left_ctrl_ar50lt(frame_width, frame_height), DMA_ALIGNMENT) *
+ num_vpp_pipes +
+ ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) +
+ ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) +
+ ALIGN(size_vp9d_lb_pe_top_data(frame_width, frame_height), DMA_ALIGNMENT) +
+ ALIGN(size_vp9d_lb_fe_top_data(frame_width, frame_height), DMA_ALIGNMENT);
+}
+
static inline
u32 hfi_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_min, bool is_opb,
u32 num_vpp_pipes)
@@ -507,6 +734,13 @@ u32 hfi_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_mi
return _lb_size + vpss_lb_size + 4096;
}
+static inline
+u32 hfi_buffer_line_vp9d_ar50lt(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_min,
+ bool is_opb, u32 num_vpp_pipes)
+{
+ return hfi_ar50lt_vp9d_lb_size(frame_width, frame_height, num_vpp_pipes);
+}
+
static u32 hfi_buffer_line_h264d(u32 frame_width, u32 frame_height,
bool is_opb, u32 num_vpp_pipes)
{
@@ -529,6 +763,25 @@ static u32 hfi_buffer_line_h264d(u32 frame_width, u32 frame_height,
return ALIGN((size + vpss_lb_size), DMA_ALIGNMENT);
}
+static u32 hfi_buffer_line_h264d_ar50lt(u32 frame_width, u32 frame_height,
+ bool is_opb, u32 num_vpp_pipes)
+{
+ u32 size;
+
+ size = ALIGN(size_h264d_lb_fe_top_data_ar50lt(frame_width), DMA_ALIGNMENT) +
+ ALIGN(size_h264d_lb_fe_top_ctrl_ar50lt(frame_width), DMA_ALIGNMENT) +
+ ALIGN(size_h264d_lb_fe_left_ctrl(frame_height), DMA_ALIGNMENT) * num_vpp_pipes +
+ ALIGN(size_h264d_lb_se_top_ctrl_ar50lt(frame_width), DMA_ALIGNMENT) +
+ ALIGN(size_h264d_lb_se_left_ctrl_ar50lt(frame_height), DMA_ALIGNMENT) *
+ num_vpp_pipes +
+ ALIGN(size_h264d_lb_pe_top_data_ar50lt(frame_width), DMA_ALIGNMENT) +
+ ALIGN(size_h264d_lb_vsp_top(frame_width), DMA_ALIGNMENT) +
+ ALIGN(size_h264d_lb_recon_dma_metadata_wr(frame_height), DMA_ALIGNMENT) * 2 +
+ ALIGN(size_h264d_qp(frame_width, frame_height), DMA_ALIGNMENT);
+
+ return ALIGN(size, DMA_ALIGNMENT);
+}
+
static u32 size_av1d_lb_opb_wr1_nv12_ubwc(u32 frame_width, u32 frame_height)
{
u32 size, y_width, y_width_a = 128;
@@ -724,6 +977,23 @@ static u32 iris_vpu_dec_bin_size(struct iris_inst *inst)
return 0;
}
+static u32 iris_vpu_ar50lt_dec_bin_size(struct iris_inst *inst)
+{
+ u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
+ struct v4l2_format *f = inst->fmt_src;
+ u32 height = f->fmt.pix_mp.height;
+ u32 width = f->fmt.pix_mp.width;
+
+ if (inst->codec == V4L2_PIX_FMT_H264)
+ return hfi_buffer_bin_h264d_ar50lt(width, height, num_vpp_pipes);
+ else if (inst->codec == V4L2_PIX_FMT_HEVC)
+ return hfi_buffer_bin_h265d_ar50lt(width, height, num_vpp_pipes);
+ else if (inst->codec == V4L2_PIX_FMT_VP9)
+ return hfi_buffer_bin_vp9d_ar50lt(width, height, num_vpp_pipes);
+
+ return 0;
+}
+
static u32 iris_vpu_dec_comv_size(struct iris_inst *inst)
{
u32 num_comv = VIDEO_MAX_FRAME;
@@ -767,6 +1037,18 @@ static u32 iris_vpu_dec_persist_size(struct iris_inst *inst)
return 0;
}
+static u32 iris_vpu_ar50lt_dec_persist_size(struct iris_inst *inst)
+{
+ if (inst->codec == V4L2_PIX_FMT_H264)
+ return hfi_buffer_persist_h264d_ar50lt();
+ else if (inst->codec == V4L2_PIX_FMT_HEVC)
+ return hfi_buffer_persist_h265d_ar50lt();
+ else if (inst->codec == V4L2_PIX_FMT_VP9)
+ return hfi_buffer_persist_vp9d_ar50lt();
+
+ return 0;
+}
+
static u32 iris_vpu_dec_dpb_size(struct iris_inst *inst)
{
if (iris_split_mode_enabled(inst))
@@ -790,6 +1072,21 @@ static u32 iris_vpu_dec_non_comv_size(struct iris_inst *inst)
return 0;
}
+static u32 iris_vpu_ar50lt_dec_non_comv_size(struct iris_inst *inst)
+{
+ u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
+ struct v4l2_format *f = inst->fmt_src;
+ u32 height = f->fmt.pix_mp.height;
+ u32 width = f->fmt.pix_mp.width;
+
+ if (inst->codec == V4L2_PIX_FMT_H264)
+ return hfi_buffer_non_comv_h264d_ar50lt(width, height, num_vpp_pipes);
+ else if (inst->codec == V4L2_PIX_FMT_HEVC)
+ return hfi_buffer_non_comv_h265d_ar50lt(width, height, num_vpp_pipes);
+
+ return 0;
+}
+
static u32 iris_vpu_dec_line_size(struct iris_inst *inst)
{
u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
@@ -815,6 +1112,29 @@ static u32 iris_vpu_dec_line_size(struct iris_inst *inst)
return 0;
}
+static u32 iris_vpu_ar50lt_dec_line_size(struct iris_inst *inst)
+{
+ u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
+ struct v4l2_format *f = inst->fmt_src;
+ u32 height = f->fmt.pix_mp.height;
+ u32 width = f->fmt.pix_mp.width;
+ bool is_opb = false;
+ u32 out_min_count = inst->buffers[BUF_OUTPUT].min_count;
+
+ if (iris_split_mode_enabled(inst))
+ is_opb = true;
+
+ if (inst->codec == V4L2_PIX_FMT_H264)
+ return hfi_buffer_line_h264d_ar50lt(width, height, is_opb, num_vpp_pipes);
+ else if (inst->codec == V4L2_PIX_FMT_HEVC)
+ return hfi_buffer_line_h265d_ar50lt(width, height, is_opb, num_vpp_pipes);
+ else if (inst->codec == V4L2_PIX_FMT_VP9)
+ return hfi_buffer_line_vp9d_ar50lt(width, height, out_min_count, is_opb,
+ num_vpp_pipes);
+
+ return 0;
+}
+
static u32 iris_vpu_dec_scratch1_size(struct iris_inst *inst)
{
return iris_vpu_dec_comv_size(inst) +
@@ -822,6 +1142,13 @@ static u32 iris_vpu_dec_scratch1_size(struct iris_inst *inst)
iris_vpu_dec_line_size(inst);
}
+static u32 iris_vpu_ar50lt_dec_scratch1_size(struct iris_inst *inst)
+{
+ return iris_vpu_dec_comv_size(inst) +
+ iris_vpu_ar50lt_dec_non_comv_size(inst) +
+ iris_vpu_ar50lt_dec_line_size(inst);
+}
+
static inline u32 iris_vpu_enc_get_bitstream_width(struct iris_inst *inst)
{
if (is_rotation_90_or_270(inst))
@@ -1410,6 +1737,15 @@ u32 hfi_buffer_dpb_enc(u32 frame_width, u32 frame_height, bool is_ten_bit)
return size;
}
+static inline
+u32 hfi_buffer_dpb_enc_ar50lt(u32 frame_width, u32 frame_height, bool is_ten_bit)
+{
+ if (!is_ten_bit)
+ return size_enc_ref_buffer(frame_width, frame_height);
+ else
+ return size_enc_ten_bit_ref_buffer(frame_width, frame_height);
+}
+
static u32 iris_vpu_enc_arp_size(struct iris_inst *inst)
{
return HFI_BUFFER_ARP_ENC;
@@ -1434,6 +1770,16 @@ u32 hfi_buffer_vpss_enc(u32 dswidth, u32 dsheight, bool ds_enable,
return 0;
}
+static inline
+u32 hfi_buffer_vpss_enc_ar50lt(u32 dswidth, u32 dsheight, bool ds_enable,
+ u32 blur, bool is_ten_bit)
+{
+ if (ds_enable || blur)
+ return hfi_buffer_dpb_enc_ar50lt(dswidth, dsheight, is_ten_bit);
+
+ return 0;
+}
+
static inline u32 hfi_buffer_scratch1_enc(u32 frame_width, u32 frame_height,
u32 lcu_size, u32 num_ref,
bool ten_bit, u32 num_vpp_pipes,
@@ -1693,6 +2039,16 @@ static u32 iris_vpu_enc_vpss_size(struct iris_inst *inst)
return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0);
}
+static u32 iris_vpu_ar50lt_enc_vpss_size(struct iris_inst *inst)
+{
+ u32 ds_enable = is_scaling_enabled(inst);
+ struct v4l2_format *f = inst->fmt_dst;
+ u32 height = f->fmt.pix_mp.height;
+ u32 width = f->fmt.pix_mp.width;
+
+ return hfi_buffer_vpss_enc_ar50lt(width, height, ds_enable, 0, 0);
+}
+
static inline u32 size_dpb_opb(u32 height, u32 lcu_size)
{
u32 max_tile_height = ((height + lcu_size - 1) / lcu_size) * lcu_size + 8;
@@ -2148,6 +2504,51 @@ u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer_type
return inst->buffers[buffer_type].size;
}
+u32 iris_vpu_ar50lt_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
+{
+ const struct iris_vpu_buf_type_handle *buf_type_handle_arr = NULL;
+ u32 size = 0, buf_type_handle_size = 0, i;
+
+ static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle[] = {
+ {BUF_BIN, iris_vpu_ar50lt_dec_bin_size },
+ {BUF_COMV, iris_vpu_dec_comv_size },
+ {BUF_NON_COMV, iris_vpu_ar50lt_dec_non_comv_size },
+ {BUF_LINE, iris_vpu_ar50lt_dec_line_size },
+ {BUF_PERSIST, iris_vpu_ar50lt_dec_persist_size },
+ {BUF_DPB, iris_vpu_dec_dpb_size },
+ {BUF_SCRATCH_1, iris_vpu_ar50lt_dec_scratch1_size },
+ {BUF_PARTIAL, iris_vpu_dec_partial_size },
+ };
+
+ static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = {
+ {BUF_BIN, iris_vpu_enc_bin_size },
+ {BUF_COMV, iris_vpu_enc_comv_size },
+ {BUF_NON_COMV, iris_vpu_enc_non_comv_size },
+ {BUF_LINE, iris_vpu_enc_line_size },
+ {BUF_ARP, iris_vpu_enc_arp_size },
+ {BUF_VPSS, iris_vpu_ar50lt_enc_vpss_size },
+ {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size },
+ {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size },
+ };
+
+ if (inst->domain == DECODER) {
+ buf_type_handle_size = ARRAY_SIZE(dec_internal_buf_type_handle);
+ buf_type_handle_arr = dec_internal_buf_type_handle;
+ } else if (inst->domain == ENCODER) {
+ buf_type_handle_size = ARRAY_SIZE(enc_internal_buf_type_handle);
+ buf_type_handle_arr = enc_internal_buf_type_handle;
+ }
+
+ for (i = 0; i < buf_type_handle_size; i++) {
+ if (buf_type_handle_arr[i].type == buffer_type) {
+ size = buf_type_handle_arr[i].handle(inst);
+ break;
+ }
+ }
+
+ return size;
+}
+
static u32 internal_buffer_count(struct iris_inst *inst,
enum iris_buffer_type buffer_type)
{
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
index 1d07137c70cd..2085e316a6bd 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
+++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
@@ -61,17 +61,26 @@ struct iris_inst;
#define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64
#define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE (128 / 8)
#define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE (128 / 8)
+#define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE_AR50LT (8 / 8)
+#define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE_AR50LT (16 / 8)
+#define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT (32 / 8)
#define VP9_UDC_HEADER_BUF_SIZE (3 * 128)
#define SIZE_SEI_USERDATA 4096
#define SIZE_DOLBY_RPU_METADATA (41 * 1024)
#define H264_CABAC_HDR_RATIO_HD_TOT 1
#define H264_CABAC_RES_RATIO_HD_TOT 3
+#define H264_CABAC_HDR_RATIO_SM_TOT 1
+#define H264_CABAC_RES_RATIO_SM_TOT 2
#define H265D_MAX_SLICE 3600
+#define H265D_MAX_SLICE_AR50LT 600
#define SIZE_H265D_HW_PIC_T SIZE_H264D_HW_PIC_T
#define H265_CABAC_HDR_RATIO_HD_TOT 2
#define H265_CABAC_RES_RATIO_HD_TOT 2
+#define H265_CABAC_HDR_RATIO_SM_TOT 1
+#define H265_CABAC_RES_RATIO_SM_TOT 6
#define SIZE_H265D_VPP_CMD_PER_BUF (256)
+#define SIZE_H265D_VPP_CMD_PER_BUF_AR50LT (192)
#define SIZE_THREE_DIMENSION_USERDATA 768
#define SIZE_H265D_ARP 9728
@@ -81,6 +90,7 @@ struct iris_inst;
#define VPX_DECODER_FRAME_BIN_DENOMINATOR 2
#define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2)
+#define VPX_DECODER_FRAME_BIN_BUFFER_SIZE (1024 * 1024)
#define SIZE_H264D_HW_PIC_T (BIT(11))
@@ -99,6 +109,7 @@ struct iris_inst;
#define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64
#define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16
#define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384
+#define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE_AR50LT 176
#define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640
#define AV1_CABAC_HDR_RATIO_HD_TOT 2
@@ -155,11 +166,21 @@ static inline u32 size_h264d_lb_fe_top_data(u32 frame_width)
return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN(frame_width, 16) * 3;
}
+static inline u32 size_h264d_lb_fe_top_data_ar50lt(u32 frame_width)
+{
+ return 16 * ALIGN(frame_width, 16) * 2;
+}
+
static inline u32 size_h264d_lb_fe_top_ctrl(u32 frame_width)
{
return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
}
+static inline u32 size_h264d_lb_fe_top_ctrl_ar50lt(u32 frame_width)
+{
+ return 16 * DIV_ROUND_UP(frame_width, 16);
+}
+
static inline u32 size_h264d_lb_fe_left_ctrl(u32 frame_height)
{
return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16);
@@ -170,16 +191,31 @@ static inline u32 size_h264d_lb_se_top_ctrl(u32 frame_width)
return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
}
+static inline u32 size_h264d_lb_se_top_ctrl_ar50lt(u32 frame_width)
+{
+ return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT * DIV_ROUND_UP(frame_width, 16);
+}
+
static inline u32 size_h264d_lb_se_left_ctrl(u32 frame_height)
{
return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16);
}
+static inline u32 size_h264d_lb_se_left_ctrl_ar50lt(u32 frame_height)
+{
+ return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT * DIV_ROUND_UP(frame_height, 16);
+}
+
static inline u32 size_h264d_lb_pe_top_data(u32 frame_width)
{
return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
}
+static inline u32 size_h264d_lb_pe_top_data_ar50lt(u32 frame_width)
+{
+ return 64 * DIV_ROUND_UP(frame_width, 16);
+}
+
static inline u32 size_h264d_lb_vsp_top(u32 frame_width)
{
return (DIV_ROUND_UP(frame_width, 16) << 7);
@@ -289,6 +325,7 @@ u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
+u32 iris_vpu_ar50lt_gen2_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type);
#endif
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 13/16] media: iris: Introduce buffer size calculations for AR50LT
2026-05-07 6:42 ` [PATCH 13/16] media: iris: Introduce buffer size calculations for AR50LT Dmitry Baryshkov
@ 2026-05-08 7:26 ` Vishnu Reddy
0 siblings, 0 replies; 36+ messages in thread
From: Vishnu Reddy @ 2026-05-08 7:26 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
>
> Introduces AR50LT buffer size calculation for both encoder and
> decoder. Reuse the buffer size calculation which are common, while
> adding the AR50LT specific ones separately.
>
> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 401 +++++++++++++++++++++
> drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 37 ++
> 2 files changed, 438 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
> index 125fb2d6960d..a1af3bca5dc9 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
> @@ -50,6 +50,32 @@ static u32 hfi_buffer_bin_h264d(u32 frame_width, u32 frame_height, u32 num_vpp_p
> return size_h264d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes);
> }
>
> +static u32 size_h264d_hw_bin_buffer_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> +{
> + u32 size_yuv, size_bin_hdr, size_bin_res;
> +
> + size_yuv = ((frame_width * frame_height * 3) >> 1);
> + if (size_yuv <= 1920 * 1088 * 3 / 2) {
> + size_bin_hdr = size_yuv * H264_CABAC_HDR_RATIO_SM_TOT;
> + size_bin_res = size_yuv * H264_CABAC_RES_RATIO_SM_TOT;
> + } else {
> + size_bin_hdr = (size_yuv * 3) / 5;
> + size_bin_res = (size_yuv * 3) / 2;
> + }
> + size_bin_hdr = ALIGN(size_bin_hdr, DMA_ALIGNMENT);
> + size_bin_res = ALIGN(size_bin_res, DMA_ALIGNMENT);
> +
> + return size_bin_hdr + size_bin_res;
> +}
> +
> +static u32 hfi_buffer_bin_h264d_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> +{
> + u32 n_aligned_h = ALIGN(frame_height, 16);
> + u32 n_aligned_w = ALIGN(frame_width, 16);
> +
> + return size_h264d_hw_bin_buffer_ar50lt(n_aligned_w, n_aligned_h, num_vpp_pipes);
> +}
> +
> static u32 size_av1d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> {
> u32 size_yuv, size_bin_hdr, size_bin_res;
> @@ -103,6 +129,21 @@ static u32 hfi_buffer_bin_vp9d(u32 frame_width, u32 frame_height, u32 num_vpp_pi
> return _size * num_vpp_pipes;
> }
>
> +static u32 hfi_buffer_bin_vp9d_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> +{
> + u32 size_yuv, size;
> +
> + size_yuv = ALIGN(frame_width, 16) * ALIGN(frame_height, 16) * 3 / 2;
> + size_yuv = ALIGN(size_yuv, DMA_ALIGNMENT);
> +
> + size = ALIGN(((((MAX(size_yuv, VPX_DECODER_FRAME_BIN_BUFFER_SIZE)) * 6) / 5) /
> + num_vpp_pipes), DMA_ALIGNMENT) +
> + ALIGN((((MAX(size_yuv, VPX_DECODER_FRAME_BIN_BUFFER_SIZE)) * 4) / num_vpp_pipes),
> + DMA_ALIGNMENT);
> +
> + return size * num_vpp_pipes;
> +}
> +
> static u32 hfi_buffer_bin_h265d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> {
> u32 n_aligned_w = ALIGN(frame_width, 16);
> @@ -111,6 +152,32 @@ static u32 hfi_buffer_bin_h265d(u32 frame_width, u32 frame_height, u32 num_vpp_p
> return size_h265d_hw_bin_buffer(n_aligned_w, n_aligned_h, num_vpp_pipes);
> }
>
> +static u32 size_h265d_hw_bin_buffer_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> +{
> + u32 size_yuv, size_bin_hdr, size_bin_res;
> +
> + size_yuv = ((frame_width * frame_height * 3) >> 1);
> + if (size_yuv <= ((BIN_BUFFER_THRESHOLD * 3) >> 1)) {
> + size_bin_hdr = size_yuv * H265_CABAC_HDR_RATIO_SM_TOT;
> + size_bin_res = size_yuv * H265_CABAC_RES_RATIO_SM_TOT;
> + } else {
> + size_bin_hdr = (size_yuv * 41) / 50;
> + size_bin_res = (size_yuv * 59) / 50;
> + }
> + size_bin_hdr = ALIGN(size_bin_hdr, DMA_ALIGNMENT);
> + size_bin_res = ALIGN(size_bin_res, DMA_ALIGNMENT);
> +
> + return size_bin_hdr + size_bin_res;
> +}
> +
> +static u32 hfi_buffer_bin_h265d_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> +{
> + u32 n_aligned_w = ALIGN(frame_width, 16);
> + u32 n_aligned_h = ALIGN(frame_height, 16);
> +
> + return size_h265d_hw_bin_buffer_ar50lt(n_aligned_w, n_aligned_h, num_vpp_pipes);
> +}
> +
> static u32 hfi_buffer_comv_h264d(u32 frame_width, u32 frame_height, u32 _comv_bufcount)
> {
> u32 frame_height_in_mbs = DIV_ROUND_UP(frame_height, 16);
> @@ -174,6 +241,14 @@ static u32 size_h264d_bse_cmd_buf(u32 frame_height)
> SIZE_H264D_BSE_CMD_PER_BUF;
> }
>
> +static u32 size_h264d_bse_cmd_buf_ar50lt(u32 frame_height)
> +{
> + u32 height = ALIGN(frame_height, 32);
> +
> + return min_t(u32, (DIV_ROUND_UP(height, 16) * 12), H264D_MAX_SLICE) *
> + SIZE_H264D_BSE_CMD_PER_BUF;
> +}
> +
> static u32 size_h265d_bse_cmd_buf(u32 frame_width, u32 frame_height)
> {
> u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
> @@ -185,6 +260,18 @@ static u32 size_h265d_bse_cmd_buf(u32 frame_width, u32 frame_height)
> return _size;
> }
>
> +static u32 size_h265d_bse_cmd_buf_ar50lt(u32 frame_width, u32 frame_height)
> +{
> + u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
> + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) *
> + NUM_HW_PIC_BUF, DMA_ALIGNMENT);
> +
> + _size = min_t(u32, _size, H265D_MAX_SLICE_AR50LT + 1);
> + _size = 2 * _size * SIZE_H265D_BSE_CMD_PER_BUF;
> +
> + return _size;
> +}
> +
> static u32 hfi_buffer_persist_h265d(u32 rpu_enabled)
> {
> return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 +
> @@ -195,6 +282,13 @@ static u32 hfi_buffer_persist_h265d(u32 rpu_enabled)
> DMA_ALIGNMENT);
> }
>
> +static u32 hfi_buffer_persist_h265d_ar50lt(void)
> +{
> + return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 +
> + H265_NUM_TILE * sizeof(u32) + NUM_HW_PIC_BUF * SIZE_SEI_USERDATA),
> + DMA_ALIGNMENT);
> +}
> +
> static inline
> u32 hfi_iris3_vp9d_comv_size(void)
> {
> @@ -212,6 +306,13 @@ static u32 hfi_buffer_persist_vp9d(void)
> HDR10_HIST_EXTRADATA_SIZE;
> }
>
> +static u32 hfi_buffer_persist_vp9d_ar50lt(void)
> +{
> + return ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, DMA_ALIGNMENT) +
> + ALIGN(hfi_iris3_vp9d_comv_size(), DMA_ALIGNMENT) +
> + ALIGN(MAX_SUPERFRAME_HEADER_LEN, DMA_ALIGNMENT);
> +}
> +
> static u32 size_h264d_vpp_cmd_buf(u32 frame_height)
> {
> u32 size, height = ALIGN(frame_height, 32);
> @@ -222,6 +323,16 @@ static u32 size_h264d_vpp_cmd_buf(u32 frame_height)
> return size > VPP_CMD_MAX_SIZE ? VPP_CMD_MAX_SIZE : size;
> }
>
> +static u32 size_h264d_vpp_cmd_buf_ar50lt(u32 frame_height)
> +{
> + u32 size, height = ALIGN(frame_height, 32);
> +
> + size = min_t(u32, (DIV_ROUND_UP(height, 16) * 12), H264D_MAX_SLICE) *
> + SIZE_H264D_VPP_CMD_PER_BUF;
> +
> + return size > VPP_CMD_MAX_SIZE ? VPP_CMD_MAX_SIZE : size;
> +}
> +
> static u32 hfi_buffer_persist_h264d(void)
> {
> return ALIGN(SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264 +
> @@ -230,6 +341,11 @@ static u32 hfi_buffer_persist_h264d(void)
> DMA_ALIGNMENT);
> }
>
> +static u32 hfi_buffer_persist_h264d_ar50lt(void)
> +{
> + return ALIGN((SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264), DMA_ALIGNMENT);
> +}
> +
> static u32 hfi_buffer_persist_av1d(u32 max_width, u32 max_height, u32 total_ref_count)
> {
> u32 comv_size, size;
> @@ -255,6 +371,17 @@ static u32 hfi_buffer_non_comv_h264d(u32 frame_width, u32 frame_height, u32 num_
> return ALIGN(size, DMA_ALIGNMENT);
> }
>
> +static u32 hfi_buffer_non_comv_h264d_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> +{
> + u32 size_bse = size_h264d_bse_cmd_buf_ar50lt(frame_height);
> + u32 size_vpp = size_h264d_vpp_cmd_buf_ar50lt(frame_height);
> + u32 size = ALIGN(size_bse, DMA_ALIGNMENT) +
> + ALIGN(size_vpp, DMA_ALIGNMENT) +
> + ALIGN(SIZE_HW_PIC(SIZE_H264D_HW_PIC_T), DMA_ALIGNMENT);
> +
> + return ALIGN(size, DMA_ALIGNMENT);
> +}
> +
> static u32 size_h265d_vpp_cmd_buf(u32 frame_width, u32 frame_height)
> {
> u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
> @@ -269,6 +396,20 @@ static u32 size_h265d_vpp_cmd_buf(u32 frame_width, u32 frame_height)
> return _size;
> }
>
> +static u32 size_h265d_vpp_cmd_buf_ar50lt(u32 frame_width, u32 frame_height)
> +{
> + u32 _size = ALIGN(((ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
> + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) *
> + NUM_HW_PIC_BUF, DMA_ALIGNMENT);
> + _size = min_t(u32, _size, H265D_MAX_SLICE_AR50LT + 1);
> + _size = ALIGN(_size, 4);
> + _size = 2 * _size * SIZE_H265D_VPP_CMD_PER_BUF_AR50LT;
> + if (_size > VPP_CMD_MAX_SIZE)
> + _size = VPP_CMD_MAX_SIZE;
> +
> + return _size;
> +}
> +
> static u32 hfi_buffer_non_comv_h265d(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> {
> u32 _size_bse = size_h265d_bse_cmd_buf(frame_width, frame_height);
> @@ -285,6 +426,20 @@ static u32 hfi_buffer_non_comv_h265d(u32 frame_width, u32 frame_height, u32 num_
> return ALIGN(_size, DMA_ALIGNMENT);
> }
>
> +static u32 hfi_buffer_non_comv_h265d_ar50lt(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> +{
> + u32 _size_bse = size_h265d_bse_cmd_buf_ar50lt(frame_width, frame_height);
> + u32 _size_vpp = size_h265d_vpp_cmd_buf_ar50lt(frame_width, frame_height);
> + u32 _size = ALIGN(_size_bse, DMA_ALIGNMENT) +
> + ALIGN(_size_vpp, DMA_ALIGNMENT) +
> + ALIGN(2 * sizeof(u16) *
> + (ALIGN(frame_width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
> + (ALIGN(frame_height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS), DMA_ALIGNMENT) +
> + ALIGN(SIZE_HW_PIC(SIZE_H265D_HW_PIC_T), DMA_ALIGNMENT);
> +
> + return ALIGN(_size, DMA_ALIGNMENT);
> +}
> +
> static u32 size_vpss_lb(u32 frame_width, u32 frame_height)
> {
> u32 opb_lb_wr_llb_y_buffer_size, opb_lb_wr_llb_uv_buffer_size;
> @@ -317,6 +472,13 @@ u32 size_h265d_lb_fe_top_data(u32 frame_width, u32 frame_height)
> (ALIGN(frame_width, 64) + 8) * 2;
> }
>
> +static inline
> +u32 size_h265d_lb_fe_top_data_ar50lt(u32 frame_width, u32 frame_height)
> +{
> + return ALIGN(MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE *
> + (ALIGN(frame_width, 64) + 8), DMA_ALIGNMENT) * 2;
> +}
> +
> static inline
> u32 size_h265d_lb_fe_top_ctrl(u32 frame_width, u32 frame_height)
> {
> @@ -348,6 +510,17 @@ u32 size_h265d_lb_se_left_ctrl(u32 frame_width, u32 frame_height)
> MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE));
> }
>
> +static inline
> +u32 size_h265d_lb_se_left_ctrl_ar50lt(u32 frame_width, u32 frame_height)
> +{
> + return max_t(u32, ((frame_height + 16 - 1) / 8) *
> + MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE_AR50LT,
> + max_t(u32, ((frame_height + 32 - 1) / 8) *
> + MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE_AR50LT,
> + ((frame_height + 64 - 1) / 8) *
> + MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT));
> +}
> +
> static inline
> u32 size_h265d_lb_pe_top_data(u32 frame_width, u32 frame_height)
> {
> @@ -355,6 +528,13 @@ u32 size_h265d_lb_pe_top_data(u32 frame_width, u32 frame_height)
> (ALIGN(frame_width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS);
> }
>
> +static inline
> +u32 size_h265d_lb_pe_top_data_ar50lt(u32 frame_width, u32 frame_height)
> +{
> + return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE_AR50LT *
> + (ALIGN(frame_width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS);
> +}
> +
> static inline
> u32 size_h265d_lb_vsp_top(u32 frame_width, u32 frame_height)
> {
> @@ -404,6 +584,29 @@ u32 hfi_buffer_line_h265d(u32 frame_width, u32 frame_height, bool is_opb, u32 nu
> return ALIGN((_size + vpss_lb_size), DMA_ALIGNMENT);
> }
>
> +static inline
> +u32 hfi_buffer_line_h265d_ar50lt(u32 frame_width, u32 frame_height, bool is_opb, u32 num_vpp_pipes)
> +{
> + u32 size;
> +
> + size = ALIGN(size_h265d_lb_fe_top_data_ar50lt(frame_width, frame_height), DMA_ALIGNMENT) +
> + ALIGN(size_h265d_lb_fe_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) +
> + ALIGN(size_h265d_lb_fe_left_ctrl(frame_width, frame_height),
> + DMA_ALIGNMENT) * num_vpp_pipes +
> + ALIGN(size_h265d_lb_se_left_ctrl_ar50lt(frame_width, frame_height),
> + DMA_ALIGNMENT) * num_vpp_pipes +
> + ALIGN(size_h265d_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) +
> + ALIGN(size_h265d_lb_pe_top_data_ar50lt(frame_width, frame_height), DMA_ALIGNMENT) +
> + ALIGN(size_h265d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) +
> + ALIGN(size_h265d_lb_vsp_left(frame_width, frame_height),
> + DMA_ALIGNMENT) * num_vpp_pipes +
> + ALIGN(size_h265d_lb_recon_dma_metadata_wr(frame_width, frame_height),
> + DMA_ALIGNMENT) * 4 +
> + ALIGN(size_h265d_qp(frame_width, frame_height), DMA_ALIGNMENT);
> +
> + return ALIGN(size, DMA_ALIGNMENT);
> +}
> +
> static inline
> u32 size_vpxd_lb_fe_left_ctrl(u32 frame_width, u32 frame_height)
> {
> @@ -438,6 +641,17 @@ u32 size_vpxd_lb_se_left_ctrl(u32 frame_width, u32 frame_height)
> MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE));
> }
>
> +static inline
> +u32 size_vpxd_lb_se_left_ctrl_ar50lt(u32 frame_width, u32 frame_height)
> +{
> + return max_t(u32, ((frame_height + 15) >> 4) *
> + MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE_AR50LT,
> + max_t(u32, ((frame_height + 31) >> 5) *
> + MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE_AR50LT,
> + ((frame_height + 63) >> 6) *
> + MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT));
> +}
> +
> static inline
> u32 size_vpxd_lb_recon_dma_metadata_wr(u32 frame_width, u32 frame_height)
> {
> @@ -492,6 +706,19 @@ u32 hfi_iris3_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> ALIGN(size_vp9d_qp(frame_width, frame_height), DMA_ALIGNMENT);
> }
>
> +static inline
> +u32 hfi_ar50lt_vp9d_lb_size(u32 frame_width, u32 frame_height, u32 num_vpp_pipes)
> +{
> + return ALIGN(size_vpxd_lb_fe_left_ctrl(frame_width, frame_height), DMA_ALIGNMENT) *
> + num_vpp_pipes +
> + ALIGN(size_vpxd_lb_se_left_ctrl_ar50lt(frame_width, frame_height), DMA_ALIGNMENT) *
> + num_vpp_pipes +
> + ALIGN(size_vp9d_lb_vsp_top(frame_width, frame_height), DMA_ALIGNMENT) +
> + ALIGN(size_vpxd_lb_se_top_ctrl(frame_width, frame_height), DMA_ALIGNMENT) +
> + ALIGN(size_vp9d_lb_pe_top_data(frame_width, frame_height), DMA_ALIGNMENT) +
> + ALIGN(size_vp9d_lb_fe_top_data(frame_width, frame_height), DMA_ALIGNMENT);
> +}
> +
> static inline
> u32 hfi_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_min, bool is_opb,
> u32 num_vpp_pipes)
> @@ -507,6 +734,13 @@ u32 hfi_buffer_line_vp9d(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_mi
> return _lb_size + vpss_lb_size + 4096;
> }
>
> +static inline
> +u32 hfi_buffer_line_vp9d_ar50lt(u32 frame_width, u32 frame_height, u32 _yuv_bufcount_min,
> + bool is_opb, u32 num_vpp_pipes)
> +{
> + return hfi_ar50lt_vp9d_lb_size(frame_width, frame_height, num_vpp_pipes);
> +}
> +
> static u32 hfi_buffer_line_h264d(u32 frame_width, u32 frame_height,
> bool is_opb, u32 num_vpp_pipes)
> {
> @@ -529,6 +763,25 @@ static u32 hfi_buffer_line_h264d(u32 frame_width, u32 frame_height,
> return ALIGN((size + vpss_lb_size), DMA_ALIGNMENT);
> }
>
> +static u32 hfi_buffer_line_h264d_ar50lt(u32 frame_width, u32 frame_height,
> + bool is_opb, u32 num_vpp_pipes)
> +{
> + u32 size;
> +
> + size = ALIGN(size_h264d_lb_fe_top_data_ar50lt(frame_width), DMA_ALIGNMENT) +
> + ALIGN(size_h264d_lb_fe_top_ctrl_ar50lt(frame_width), DMA_ALIGNMENT) +
> + ALIGN(size_h264d_lb_fe_left_ctrl(frame_height), DMA_ALIGNMENT) * num_vpp_pipes +
> + ALIGN(size_h264d_lb_se_top_ctrl_ar50lt(frame_width), DMA_ALIGNMENT) +
> + ALIGN(size_h264d_lb_se_left_ctrl_ar50lt(frame_height), DMA_ALIGNMENT) *
> + num_vpp_pipes +
> + ALIGN(size_h264d_lb_pe_top_data_ar50lt(frame_width), DMA_ALIGNMENT) +
> + ALIGN(size_h264d_lb_vsp_top(frame_width), DMA_ALIGNMENT) +
> + ALIGN(size_h264d_lb_recon_dma_metadata_wr(frame_height), DMA_ALIGNMENT) * 2 +
> + ALIGN(size_h264d_qp(frame_width, frame_height), DMA_ALIGNMENT);
> +
> + return ALIGN(size, DMA_ALIGNMENT);
> +}
> +
> static u32 size_av1d_lb_opb_wr1_nv12_ubwc(u32 frame_width, u32 frame_height)
> {
> u32 size, y_width, y_width_a = 128;
> @@ -724,6 +977,23 @@ static u32 iris_vpu_dec_bin_size(struct iris_inst *inst)
> return 0;
> }
>
> +static u32 iris_vpu_ar50lt_dec_bin_size(struct iris_inst *inst)
> +{
> + u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
> + struct v4l2_format *f = inst->fmt_src;
> + u32 height = f->fmt.pix_mp.height;
> + u32 width = f->fmt.pix_mp.width;
> +
> + if (inst->codec == V4L2_PIX_FMT_H264)
> + return hfi_buffer_bin_h264d_ar50lt(width, height, num_vpp_pipes);
> + else if (inst->codec == V4L2_PIX_FMT_HEVC)
> + return hfi_buffer_bin_h265d_ar50lt(width, height, num_vpp_pipes);
> + else if (inst->codec == V4L2_PIX_FMT_VP9)
> + return hfi_buffer_bin_vp9d_ar50lt(width, height, num_vpp_pipes);
> +
> + return 0;
> +}
> +
> static u32 iris_vpu_dec_comv_size(struct iris_inst *inst)
> {
> u32 num_comv = VIDEO_MAX_FRAME;
> @@ -767,6 +1037,18 @@ static u32 iris_vpu_dec_persist_size(struct iris_inst *inst)
> return 0;
> }
>
> +static u32 iris_vpu_ar50lt_dec_persist_size(struct iris_inst *inst)
> +{
> + if (inst->codec == V4L2_PIX_FMT_H264)
> + return hfi_buffer_persist_h264d_ar50lt();
> + else if (inst->codec == V4L2_PIX_FMT_HEVC)
> + return hfi_buffer_persist_h265d_ar50lt();
> + else if (inst->codec == V4L2_PIX_FMT_VP9)
> + return hfi_buffer_persist_vp9d_ar50lt();
> +
> + return 0;
> +}
> +
> static u32 iris_vpu_dec_dpb_size(struct iris_inst *inst)
> {
> if (iris_split_mode_enabled(inst))
> @@ -790,6 +1072,21 @@ static u32 iris_vpu_dec_non_comv_size(struct iris_inst *inst)
> return 0;
> }
>
> +static u32 iris_vpu_ar50lt_dec_non_comv_size(struct iris_inst *inst)
> +{
> + u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
> + struct v4l2_format *f = inst->fmt_src;
> + u32 height = f->fmt.pix_mp.height;
> + u32 width = f->fmt.pix_mp.width;
> +
> + if (inst->codec == V4L2_PIX_FMT_H264)
> + return hfi_buffer_non_comv_h264d_ar50lt(width, height, num_vpp_pipes);
> + else if (inst->codec == V4L2_PIX_FMT_HEVC)
> + return hfi_buffer_non_comv_h265d_ar50lt(width, height, num_vpp_pipes);
> +
> + return 0;
> +}
> +
> static u32 iris_vpu_dec_line_size(struct iris_inst *inst)
> {
> u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
> @@ -815,6 +1112,29 @@ static u32 iris_vpu_dec_line_size(struct iris_inst *inst)
> return 0;
> }
>
> +static u32 iris_vpu_ar50lt_dec_line_size(struct iris_inst *inst)
> +{
> + u32 num_vpp_pipes = inst->core->iris_platform_data->num_vpp_pipe;
> + struct v4l2_format *f = inst->fmt_src;
> + u32 height = f->fmt.pix_mp.height;
> + u32 width = f->fmt.pix_mp.width;
> + bool is_opb = false;
> + u32 out_min_count = inst->buffers[BUF_OUTPUT].min_count;
> +
> + if (iris_split_mode_enabled(inst))
> + is_opb = true;
> +
> + if (inst->codec == V4L2_PIX_FMT_H264)
> + return hfi_buffer_line_h264d_ar50lt(width, height, is_opb, num_vpp_pipes);
> + else if (inst->codec == V4L2_PIX_FMT_HEVC)
> + return hfi_buffer_line_h265d_ar50lt(width, height, is_opb, num_vpp_pipes);
> + else if (inst->codec == V4L2_PIX_FMT_VP9)
> + return hfi_buffer_line_vp9d_ar50lt(width, height, out_min_count, is_opb,
> + num_vpp_pipes);
> +
> + return 0;
> +}
> +
> static u32 iris_vpu_dec_scratch1_size(struct iris_inst *inst)
> {
> return iris_vpu_dec_comv_size(inst) +
> @@ -822,6 +1142,13 @@ static u32 iris_vpu_dec_scratch1_size(struct iris_inst *inst)
> iris_vpu_dec_line_size(inst);
> }
>
> +static u32 iris_vpu_ar50lt_dec_scratch1_size(struct iris_inst *inst)
> +{
> + return iris_vpu_dec_comv_size(inst) +
> + iris_vpu_ar50lt_dec_non_comv_size(inst) +
> + iris_vpu_ar50lt_dec_line_size(inst);
> +}
> +
> static inline u32 iris_vpu_enc_get_bitstream_width(struct iris_inst *inst)
> {
> if (is_rotation_90_or_270(inst))
> @@ -1410,6 +1737,15 @@ u32 hfi_buffer_dpb_enc(u32 frame_width, u32 frame_height, bool is_ten_bit)
> return size;
> }
>
> +static inline
> +u32 hfi_buffer_dpb_enc_ar50lt(u32 frame_width, u32 frame_height, bool is_ten_bit)
> +{
> + if (!is_ten_bit)
> + return size_enc_ref_buffer(frame_width, frame_height);
> + else
> + return size_enc_ten_bit_ref_buffer(frame_width, frame_height);
> +}
> +
> static u32 iris_vpu_enc_arp_size(struct iris_inst *inst)
> {
> return HFI_BUFFER_ARP_ENC;
> @@ -1434,6 +1770,16 @@ u32 hfi_buffer_vpss_enc(u32 dswidth, u32 dsheight, bool ds_enable,
> return 0;
> }
>
> +static inline
> +u32 hfi_buffer_vpss_enc_ar50lt(u32 dswidth, u32 dsheight, bool ds_enable,
> + u32 blur, bool is_ten_bit)
> +{
> + if (ds_enable || blur)
> + return hfi_buffer_dpb_enc_ar50lt(dswidth, dsheight, is_ten_bit);
> +
> + return 0;
> +}
> +
> static inline u32 hfi_buffer_scratch1_enc(u32 frame_width, u32 frame_height,
> u32 lcu_size, u32 num_ref,
> bool ten_bit, u32 num_vpp_pipes,
> @@ -1693,6 +2039,16 @@ static u32 iris_vpu_enc_vpss_size(struct iris_inst *inst)
> return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0);
> }
>
> +static u32 iris_vpu_ar50lt_enc_vpss_size(struct iris_inst *inst)
> +{
> + u32 ds_enable = is_scaling_enabled(inst);
> + struct v4l2_format *f = inst->fmt_dst;
> + u32 height = f->fmt.pix_mp.height;
> + u32 width = f->fmt.pix_mp.width;
> +
> + return hfi_buffer_vpss_enc_ar50lt(width, height, ds_enable, 0, 0);
> +}
> +
> static inline u32 size_dpb_opb(u32 height, u32 lcu_size)
> {
> u32 max_tile_height = ((height + lcu_size - 1) / lcu_size) * lcu_size + 8;
> @@ -2148,6 +2504,51 @@ u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer_type
> return inst->buffers[buffer_type].size;
> }
>
> +u32 iris_vpu_ar50lt_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
> +{
> + const struct iris_vpu_buf_type_handle *buf_type_handle_arr = NULL;
> + u32 size = 0, buf_type_handle_size = 0, i;
> +
> + static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle[] = {
> + {BUF_BIN, iris_vpu_ar50lt_dec_bin_size },
> + {BUF_COMV, iris_vpu_dec_comv_size },
> + {BUF_NON_COMV, iris_vpu_ar50lt_dec_non_comv_size },
> + {BUF_LINE, iris_vpu_ar50lt_dec_line_size },
> + {BUF_PERSIST, iris_vpu_ar50lt_dec_persist_size },
> + {BUF_DPB, iris_vpu_dec_dpb_size },
> + {BUF_SCRATCH_1, iris_vpu_ar50lt_dec_scratch1_size },
> + {BUF_PARTIAL, iris_vpu_dec_partial_size },
> + };
> +
> + static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle[] = {
> + {BUF_BIN, iris_vpu_enc_bin_size },
> + {BUF_COMV, iris_vpu_enc_comv_size },
> + {BUF_NON_COMV, iris_vpu_enc_non_comv_size },
> + {BUF_LINE, iris_vpu_enc_line_size },
> + {BUF_ARP, iris_vpu_enc_arp_size },
> + {BUF_VPSS, iris_vpu_ar50lt_enc_vpss_size },
> + {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size },
> + {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size },
> + };
> +
> + if (inst->domain == DECODER) {
> + buf_type_handle_size = ARRAY_SIZE(dec_internal_buf_type_handle);
> + buf_type_handle_arr = dec_internal_buf_type_handle;
> + } else if (inst->domain == ENCODER) {
> + buf_type_handle_size = ARRAY_SIZE(enc_internal_buf_type_handle);
> + buf_type_handle_arr = enc_internal_buf_type_handle;
> + }
> +
> + for (i = 0; i < buf_type_handle_size; i++) {
> + if (buf_type_handle_arr[i].type == buffer_type) {
> + size = buf_type_handle_arr[i].handle(inst);
> + break;
> + }
> + }
> +
> + return size;
> +}
> +
> static u32 internal_buffer_count(struct iris_inst *inst,
> enum iris_buffer_type buffer_type)
> {
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
> index 1d07137c70cd..2085e316a6bd 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h
> @@ -61,17 +61,26 @@ struct iris_inst;
> #define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64
> #define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE (128 / 8)
> #define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE (128 / 8)
> +#define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE_AR50LT (8 / 8)
> +#define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE_AR50LT (16 / 8)
> +#define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT (32 / 8)
> #define VP9_UDC_HEADER_BUF_SIZE (3 * 128)
>
> #define SIZE_SEI_USERDATA 4096
> #define SIZE_DOLBY_RPU_METADATA (41 * 1024)
> #define H264_CABAC_HDR_RATIO_HD_TOT 1
> #define H264_CABAC_RES_RATIO_HD_TOT 3
> +#define H264_CABAC_HDR_RATIO_SM_TOT 1
> +#define H264_CABAC_RES_RATIO_SM_TOT 2
> #define H265D_MAX_SLICE 3600
> +#define H265D_MAX_SLICE_AR50LT 600
> #define SIZE_H265D_HW_PIC_T SIZE_H264D_HW_PIC_T
> #define H265_CABAC_HDR_RATIO_HD_TOT 2
> #define H265_CABAC_RES_RATIO_HD_TOT 2
> +#define H265_CABAC_HDR_RATIO_SM_TOT 1
> +#define H265_CABAC_RES_RATIO_SM_TOT 6
> #define SIZE_H265D_VPP_CMD_PER_BUF (256)
> +#define SIZE_H265D_VPP_CMD_PER_BUF_AR50LT (192)
> #define SIZE_THREE_DIMENSION_USERDATA 768
> #define SIZE_H265D_ARP 9728
>
> @@ -81,6 +90,7 @@ struct iris_inst;
> #define VPX_DECODER_FRAME_BIN_DENOMINATOR 2
>
> #define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2)
> +#define VPX_DECODER_FRAME_BIN_BUFFER_SIZE (1024 * 1024)
>
> #define SIZE_H264D_HW_PIC_T (BIT(11))
>
> @@ -99,6 +109,7 @@ struct iris_inst;
> #define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64
> #define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16
> #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384
> +#define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE_AR50LT 176
> #define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640
>
> #define AV1_CABAC_HDR_RATIO_HD_TOT 2
> @@ -155,11 +166,21 @@ static inline u32 size_h264d_lb_fe_top_data(u32 frame_width)
> return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN(frame_width, 16) * 3;
> }
>
> +static inline u32 size_h264d_lb_fe_top_data_ar50lt(u32 frame_width)
> +{
> + return 16 * ALIGN(frame_width, 16) * 2;
> +}
> +
> static inline u32 size_h264d_lb_fe_top_ctrl(u32 frame_width)
> {
> return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
> }
>
> +static inline u32 size_h264d_lb_fe_top_ctrl_ar50lt(u32 frame_width)
> +{
> + return 16 * DIV_ROUND_UP(frame_width, 16);
> +}
> +
> static inline u32 size_h264d_lb_fe_left_ctrl(u32 frame_height)
> {
> return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16);
> @@ -170,16 +191,31 @@ static inline u32 size_h264d_lb_se_top_ctrl(u32 frame_width)
> return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
> }
>
> +static inline u32 size_h264d_lb_se_top_ctrl_ar50lt(u32 frame_width)
> +{
> + return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT * DIV_ROUND_UP(frame_width, 16);
> +}
> +
> static inline u32 size_h264d_lb_se_left_ctrl(u32 frame_height)
> {
> return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16);
> }
>
> +static inline u32 size_h264d_lb_se_left_ctrl_ar50lt(u32 frame_height)
> +{
> + return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE_AR50LT * DIV_ROUND_UP(frame_height, 16);
> +}
> +
> static inline u32 size_h264d_lb_pe_top_data(u32 frame_width)
> {
> return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
> }
>
> +static inline u32 size_h264d_lb_pe_top_data_ar50lt(u32 frame_width)
> +{
> + return 64 * DIV_ROUND_UP(frame_width, 16);
> +}
> +
> static inline u32 size_h264d_lb_vsp_top(u32 frame_width)
> {
> return (DIV_ROUND_UP(frame_width, 16) << 7);
> @@ -289,6 +325,7 @@ u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
> u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
> u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
> u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
> +u32 iris_vpu_ar50lt_gen2_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
The function is defined as iris_vpu_ar50lt_buf_size in this patch, but
declared as iris_vpu_ar50lt_gen2_buf_size, these names don't match. The
rename happens in the next patch.
Rename the function definition to iris_vpu_ar50lt_gen2_buf_size here itself,
so both the definition and declaration are aligned in this patch.
Or, keep the declaration as iris_vpu_ar50lt_buf_size here, and rename both
the definition and declaration together in the next patch.
> int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type);
>
> #endif
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 14/16] media: iris: add Gen2 firmware support on the Agatti platform
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (12 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 13/16] media: iris: Introduce buffer size calculations for AR50LT Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 6:42 ` [PATCH 15/16] media: venus: skip QCM2290 if Iris driver is enabled Dmitry Baryshkov
` (2 subsequent siblings)
16 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Agatti platform is using HFI Gen1 firmware, which is considered to be
legacy firmware branch. Follow the example of the SC7280 platform and
extend the driver with supporting both HFI Gen1 and Gen2 firmwares for
this platform. Like HFI Gen1 this firmware doesn't have PIPE property
(but unlike Gen1 buffer sizes are calculated on the driver side).
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/media/platform/qcom/iris/iris_hfi_gen2.c | 613 +++++++++++++++++++++
.../platform/qcom/iris/iris_platform_common.h | 1 +
.../platform/qcom/iris/iris_platform_vpu_ar50lt.c | 11 +-
drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 2 +-
4 files changed, 624 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2.c b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c
index ce8490d64854..61061d17afe5 100644
--- a/drivers/media/platform/qcom/iris/iris_hfi_gen2.c
+++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2.c
@@ -894,3 +894,616 @@ const struct iris_firmware_data iris_hfi_gen2_data = {
.enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
.enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
};
+
+static const struct platform_inst_fw_cap inst_fw_cap_gen2_ar50lt_dec[] = {
+ {
+ .cap_id = PROFILE_H264,
+ .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
+ .max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH),
+ .value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
+ .hfi_id = HFI_PROP_PROFILE,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_u32_enum,
+ },
+ {
+ .cap_id = PROFILE_HEVC,
+ .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
+ .value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ .hfi_id = HFI_PROP_PROFILE,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_u32_enum,
+ },
+ {
+ .cap_id = PROFILE_VP9,
+ .min = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
+ .max = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_PROFILE_0),
+ .value = V4L2_MPEG_VIDEO_VP9_PROFILE_0,
+ .hfi_id = HFI_PROP_PROFILE,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_u32_enum,
+ },
+ {
+ .cap_id = LEVEL_H264,
+ .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
+ .max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2),
+ .value = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
+ .hfi_id = HFI_PROP_LEVEL,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_u32_enum,
+ },
+ {
+ .cap_id = LEVEL_HEVC,
+ .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
+ .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1),
+ .value = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1,
+ .hfi_id = HFI_PROP_LEVEL,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_u32_enum,
+ },
+ {
+ .cap_id = LEVEL_VP9,
+ .min = V4L2_MPEG_VIDEO_VP9_LEVEL_1_0,
+ .max = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_0) |
+ BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_1_1) |
+ BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_0) |
+ BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_2_1) |
+ BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_0) |
+ BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_3_1) |
+ BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_0) |
+ BIT(V4L2_MPEG_VIDEO_VP9_LEVEL_4_1),
+ .value = V4L2_MPEG_VIDEO_VP9_LEVEL_4_1,
+ .hfi_id = HFI_PROP_LEVEL,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_u32_enum,
+ },
+ {
+ .cap_id = TIER,
+ .min = V4L2_MPEG_VIDEO_HEVC_TIER_MAIN,
+ .max = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_TIER_MAIN) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_TIER_HIGH),
+ .value = V4L2_MPEG_VIDEO_HEVC_TIER_HIGH,
+ .hfi_id = HFI_PROP_TIER,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_u32_enum,
+ },
+ {
+ .cap_id = INPUT_BUF_HOST_MAX_COUNT,
+ .min = DEFAULT_MAX_HOST_BUF_COUNT,
+ .max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
+ .step_or_mask = 1,
+ .value = DEFAULT_MAX_HOST_BUF_COUNT,
+ .hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
+ .flags = CAP_FLAG_INPUT_PORT,
+ .set = iris_set_u32,
+ },
+ {
+ .cap_id = STAGE,
+ .min = STAGE_1,
+ .max = STAGE_2,
+ .step_or_mask = 1,
+ .value = STAGE_2,
+ .hfi_id = HFI_PROP_STAGE,
+ .set = iris_set_stage,
+ },
+ {
+ .cap_id = POC,
+ .min = 0,
+ .max = 2,
+ .step_or_mask = 1,
+ .value = 1,
+ .hfi_id = HFI_PROP_PIC_ORDER_CNT_TYPE,
+ },
+ {
+ .cap_id = CODED_FRAMES,
+ .min = CODED_FRAMES_PROGRESSIVE,
+ .max = CODED_FRAMES_PROGRESSIVE,
+ .step_or_mask = 0,
+ .value = CODED_FRAMES_PROGRESSIVE,
+ .hfi_id = HFI_PROP_CODED_FRAMES,
+ },
+ {
+ .cap_id = BIT_DEPTH,
+ .min = BIT_DEPTH_8,
+ .max = BIT_DEPTH_8,
+ .step_or_mask = 1,
+ .value = BIT_DEPTH_8,
+ .hfi_id = HFI_PROP_LUMA_CHROMA_BIT_DEPTH,
+ },
+ {
+ .cap_id = RAP_FRAME,
+ .min = 0,
+ .max = 1,
+ .step_or_mask = 1,
+ .value = 1,
+ .hfi_id = HFI_PROP_DEC_START_FROM_RAP_FRAME,
+ .flags = CAP_FLAG_INPUT_PORT,
+ .set = iris_set_u32,
+ },
+};
+
+static const struct platform_inst_fw_cap inst_fw_cap_gen2_ar50lt_enc[] = {
+ {
+ .cap_id = PROFILE_H264,
+ .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
+ .max = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |
+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH),
+ .value = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
+ .hfi_id = HFI_PROP_PROFILE,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_profile,
+ },
+ {
+ .cap_id = PROFILE_HEVC,
+ .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE),
+ .value = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ .hfi_id = HFI_PROP_PROFILE,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_profile,
+ },
+ {
+ .cap_id = LEVEL_H264,
+ .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
+ .max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |
+ BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2),
+ .value = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,
+ .hfi_id = HFI_PROP_LEVEL,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_level,
+ },
+ {
+ .cap_id = LEVEL_HEVC,
+ .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
+ .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) |
+ BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1),
+ .value = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1,
+ .hfi_id = HFI_PROP_LEVEL,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_level,
+ },
+ {
+ .cap_id = STAGE,
+ .min = STAGE_1,
+ .max = STAGE_2,
+ .step_or_mask = 1,
+ .value = STAGE_2,
+ .hfi_id = HFI_PROP_STAGE,
+ .set = iris_set_stage,
+ },
+ {
+ .cap_id = HEADER_MODE,
+ .min = V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE,
+ .max = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) |
+ BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME),
+ .value = V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
+ .hfi_id = HFI_PROP_SEQ_HEADER_MODE,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_header_mode_gen2,
+ },
+ {
+ .cap_id = PREPEND_SPSPPS_TO_IDR,
+ .min = 0,
+ .max = 1,
+ .step_or_mask = 1,
+ .value = 0,
+ },
+ {
+ .cap_id = BITRATE,
+ .min = 1,
+ .max = BITRATE_MAX_AR50LT,
+ .step_or_mask = 1,
+ .value = BITRATE_DEFAULT_AR50LT,
+ .hfi_id = HFI_PROP_TOTAL_BITRATE,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+ CAP_FLAG_DYNAMIC_ALLOWED,
+ .set = iris_set_bitrate,
+ },
+ {
+ .cap_id = BITRATE_PEAK,
+ .min = 1,
+ .max = BITRATE_MAX_AR50LT,
+ .step_or_mask = 1,
+ .value = BITRATE_DEFAULT_AR50LT,
+ .hfi_id = HFI_PROP_TOTAL_PEAK_BITRATE,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+ CAP_FLAG_DYNAMIC_ALLOWED,
+ .set = iris_set_peak_bitrate,
+ },
+ {
+ .cap_id = BITRATE_MODE,
+ .min = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
+ .max = V4L2_MPEG_VIDEO_BITRATE_MODE_CBR,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) |
+ BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR),
+ .value = V4L2_MPEG_VIDEO_BITRATE_MODE_VBR,
+ .hfi_id = HFI_PROP_RATE_CONTROL,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_bitrate_mode_gen2,
+ },
+ {
+ .cap_id = FRAME_SKIP_MODE,
+ .min = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
+ .max = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) |
+ BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) |
+ BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT),
+ .value = V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ },
+ {
+ .cap_id = FRAME_RC_ENABLE,
+ .min = 0,
+ .max = 1,
+ .step_or_mask = 1,
+ .value = 1,
+ },
+ {
+ .cap_id = GOP_SIZE,
+ .min = 0,
+ .max = INT_MAX,
+ .step_or_mask = 1,
+ .value = 2 * DEFAULT_FPS - 1,
+ .hfi_id = HFI_PROP_MAX_GOP_FRAMES,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+ CAP_FLAG_DYNAMIC_ALLOWED,
+ .set = iris_set_u32,
+ },
+ {
+ .cap_id = ENTROPY_MODE,
+ .min = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
+ .max = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
+ .step_or_mask = BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
+ BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC),
+ .value = V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
+ .hfi_id = HFI_PROP_CABAC_SESSION,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ .set = iris_set_entropy_mode_gen2,
+ },
+ {
+ .cap_id = MIN_FRAME_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MIN_QP_8BIT_AR50LT,
+ .hfi_id = HFI_PROP_MIN_QP_PACKED,
+ .flags = CAP_FLAG_OUTPUT_PORT,
+ .set = iris_set_min_qp,
+ },
+ {
+ .cap_id = MIN_FRAME_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MIN_QP_8BIT_AR50LT,
+ .hfi_id = HFI_PROP_MIN_QP_PACKED,
+ .flags = CAP_FLAG_OUTPUT_PORT,
+ .set = iris_set_min_qp,
+ },
+ {
+ .cap_id = MAX_FRAME_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MAX_QP,
+ .hfi_id = HFI_PROP_MAX_QP_PACKED,
+ .flags = CAP_FLAG_OUTPUT_PORT,
+ .set = iris_set_max_qp,
+ },
+ {
+ .cap_id = MAX_FRAME_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MAX_QP,
+ .hfi_id = HFI_PROP_MAX_QP_PACKED,
+ .flags = CAP_FLAG_OUTPUT_PORT,
+ .set = iris_set_max_qp,
+ },
+ {
+ .cap_id = I_FRAME_MIN_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MIN_QP_8BIT_AR50LT,
+ },
+ {
+ .cap_id = I_FRAME_MIN_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MIN_QP_8BIT_AR50LT,
+ },
+ {
+ .cap_id = P_FRAME_MIN_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MIN_QP_8BIT_AR50LT,
+ },
+ {
+ .cap_id = P_FRAME_MIN_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MIN_QP_8BIT_AR50LT,
+ },
+ {
+ .cap_id = B_FRAME_MIN_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MIN_QP_8BIT_AR50LT,
+ },
+ {
+ .cap_id = B_FRAME_MIN_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MIN_QP_8BIT_AR50LT,
+ },
+ {
+ .cap_id = I_FRAME_MAX_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MAX_QP,
+ },
+ {
+ .cap_id = I_FRAME_MAX_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MAX_QP,
+ },
+ {
+ .cap_id = P_FRAME_MAX_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MAX_QP,
+ },
+ {
+ .cap_id = P_FRAME_MAX_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MAX_QP,
+ },
+ {
+ .cap_id = B_FRAME_MAX_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MAX_QP,
+ },
+ {
+ .cap_id = B_FRAME_MAX_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = MAX_QP,
+ },
+ {
+ .cap_id = I_FRAME_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = DEFAULT_QP,
+ .hfi_id = HFI_PROP_QP_PACKED,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+ CAP_FLAG_DYNAMIC_ALLOWED,
+ .set = iris_set_frame_qp,
+ },
+ {
+ .cap_id = I_FRAME_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = DEFAULT_QP,
+ .hfi_id = HFI_PROP_QP_PACKED,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+ CAP_FLAG_DYNAMIC_ALLOWED,
+ .set = iris_set_frame_qp,
+ },
+ {
+ .cap_id = P_FRAME_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = DEFAULT_QP,
+ .hfi_id = HFI_PROP_QP_PACKED,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+ CAP_FLAG_DYNAMIC_ALLOWED,
+ .set = iris_set_frame_qp,
+ },
+ {
+ .cap_id = P_FRAME_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = DEFAULT_QP,
+ .hfi_id = HFI_PROP_QP_PACKED,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+ CAP_FLAG_DYNAMIC_ALLOWED,
+ .set = iris_set_frame_qp,
+ },
+ {
+ .cap_id = B_FRAME_QP_H264,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = DEFAULT_QP,
+ .hfi_id = HFI_PROP_QP_PACKED,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+ CAP_FLAG_DYNAMIC_ALLOWED,
+ .set = iris_set_frame_qp,
+ },
+ {
+ .cap_id = B_FRAME_QP_HEVC,
+ .min = MIN_QP_8BIT_AR50LT,
+ .max = MAX_QP,
+ .step_or_mask = 1,
+ .value = DEFAULT_QP,
+ .hfi_id = HFI_PROP_QP_PACKED,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT |
+ CAP_FLAG_DYNAMIC_ALLOWED,
+ .set = iris_set_frame_qp,
+ },
+ {
+ .cap_id = INPUT_BUF_HOST_MAX_COUNT,
+ .min = DEFAULT_MAX_HOST_BUF_COUNT,
+ .max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
+ .step_or_mask = 1,
+ .value = DEFAULT_MAX_HOST_BUF_COUNT,
+ .hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
+ .flags = CAP_FLAG_INPUT_PORT,
+ .set = iris_set_u32,
+ },
+ {
+ .cap_id = OUTPUT_BUF_HOST_MAX_COUNT,
+ .min = DEFAULT_MAX_HOST_BUF_COUNT,
+ .max = DEFAULT_MAX_HOST_BURST_BUF_COUNT,
+ .step_or_mask = 1,
+ .value = DEFAULT_MAX_HOST_BUF_COUNT,
+ .hfi_id = HFI_PROP_BUFFER_HOST_MAX_COUNT,
+ .flags = CAP_FLAG_OUTPUT_PORT,
+ .set = iris_set_u32,
+ },
+ {
+ .cap_id = IR_TYPE,
+ .min = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
+ .max = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
+ .step_or_mask = BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM),
+ .value = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ },
+ {
+ .cap_id = IR_PERIOD,
+ .min = 0,
+ .max = INT_MAX,
+ .step_or_mask = 1,
+ .value = 0,
+ .flags = CAP_FLAG_OUTPUT_PORT |
+ CAP_FLAG_DYNAMIC_ALLOWED,
+ .set = iris_set_ir_period,
+ },
+};
+
+static const u32 iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl[] = {
+ BUF_BIN,
+ BUF_COMV,
+ BUF_NON_COMV,
+ BUF_LINE,
+};
+
+const struct iris_firmware_data iris_hfi_gen2_ar50lt_data = {
+ .init_hfi_ops = iris_hfi_gen2_sys_ops_init,
+
+ .core_arch = VIDEO_ARCH_LX,
+
+ .inst_fw_caps_dec = inst_fw_cap_gen2_ar50lt_dec,
+ .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_gen2_ar50lt_dec),
+ .inst_fw_caps_enc = inst_fw_cap_gen2_ar50lt_enc,
+ .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_gen2_ar50lt_enc),
+ .dec_input_config_params_default =
+ sm8550_vdec_input_config_params_default,
+ .dec_input_config_params_default_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_params_default),
+ .dec_input_config_params_hevc =
+ sm8550_vdec_input_config_param_hevc,
+ .dec_input_config_params_hevc_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
+ .dec_input_config_params_vp9 =
+ sm8550_vdec_input_config_param_vp9,
+ .dec_input_config_params_vp9_size =
+ ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
+ .dec_output_config_params =
+ sm8550_vdec_output_config_params,
+ .dec_output_config_params_size =
+ ARRAY_SIZE(sm8550_vdec_output_config_params),
+ .enc_input_config_params =
+ sm8550_venc_input_config_params,
+ .enc_input_config_params_size =
+ ARRAY_SIZE(sm8550_venc_input_config_params),
+ .enc_output_config_params =
+ sm8550_venc_output_config_params,
+ .enc_output_config_params_size =
+ ARRAY_SIZE(sm8550_venc_output_config_params),
+ .dec_input_prop = sm8550_vdec_subscribe_input_properties,
+ .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
+ .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
+ .dec_output_prop_avc_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
+ .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
+ .dec_output_prop_hevc_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
+ .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
+ .dec_output_prop_vp9_size =
+ ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
+ .dec_ip_int_buf_tbl = iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl,
+ .dec_ip_int_buf_tbl_size = ARRAY_SIZE(iris_hfi_gen2_ar50lt_dec_ip_int_buf_tbl),
+ .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
+ .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
+ .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl,
+ .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl),
+ .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
+ .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
+};
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index f9763ea51c53..e0c18780c045 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -47,6 +47,7 @@ enum pipe_type {
extern const struct iris_firmware_data iris_hfi_gen1_data;
extern const struct iris_firmware_data iris_hfi_gen1_ar50lt_data;
extern const struct iris_firmware_data iris_hfi_gen2_data;
+extern const struct iris_firmware_data iris_hfi_gen2_ar50lt_data;
extern const struct iris_platform_data qcm2290_data;
extern const struct iris_platform_data qcs8300_data;
diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c
index 76bebe012bd8..d2ee3039e35a 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_vpu_ar50lt.c
@@ -13,12 +13,18 @@
#define WRAPPER_INTR_STATUS_A2HWD_BMSK 0x10
-const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen1_s6_desc = {
+const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen1_desc = {
.firmware_data = &iris_hfi_gen1_ar50lt_data,
.get_vpu_buffer_size = iris_vpu_ar50lt_gen1_buf_size,
.fwname = "qcom/venus-6.0/venus.mbn",
};
+const struct iris_firmware_desc iris_vpu_ar50lt_p1_gen2_s6_desc = {
+ .firmware_data = &iris_hfi_gen2_ar50lt_data,
+ .get_vpu_buffer_size = iris_vpu_ar50lt_gen2_buf_size,
+ .fwname = "qcom/vpu/ar50lt_p1_gen2_s6.mbn",
+};
+
static const u32 iris_fmts_ar50lt_dec[] = {
[IRIS_FMT_H264] = V4L2_PIX_FMT_H264,
[IRIS_FMT_HEVC] = V4L2_PIX_FMT_HEVC,
@@ -79,7 +85,8 @@ static struct platform_inst_caps platform_inst_cap_ar50lt = {
};
const struct iris_platform_data qcm2290_data = {
- .firmware_desc_gen1 = &iris_vpu_ar50lt_p1_gen1_s6_desc,
+ .firmware_desc_gen1 = &iris_vpu_ar50lt_p1_gen1_desc,
+ .firmware_desc_gen2 = &iris_vpu_ar50lt_p1_gen2_s6_desc,
.vpu_ops = &iris_vpu_ar50lt_ops,
.icc_tbl = iris_icc_info_ar50lt,
.icc_tbl_size = ARRAY_SIZE(iris_icc_info_ar50lt),
diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
index a1af3bca5dc9..e75684d6d97d 100644
--- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c
@@ -2504,7 +2504,7 @@ u32 iris_vpu_ar50lt_gen1_buf_size(struct iris_inst *inst, enum iris_buffer_type
return inst->buffers[buffer_type].size;
}
-u32 iris_vpu_ar50lt_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
+u32 iris_vpu_ar50lt_gen2_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type)
{
const struct iris_vpu_buf_type_handle *buf_type_handle_arr = NULL;
u32 size = 0, buf_type_handle_size = 0, i;
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 15/16] media: venus: skip QCM2290 if Iris driver is enabled
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (13 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 14/16] media: iris: add Gen2 firmware support on the Agatti platform Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 6:42 ` [PATCH 16/16] arm64: dts: qcom: agatti: add higher OPP levels Dmitry Baryshkov
2026-05-07 13:02 ` [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Vikash Garodia
16 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
As the Iris driver now supports the QCM2290 hardware too, there is a
race between Venus and Iris drivers on binding to the corresponding
device. Follow the approach used by other platforms and skip QCM2290 in
the Venus driver if Iris is enabled.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
---
drivers/media/platform/qcom/venus/core.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c
index 247fb54bc00e..ea67e713a810 100644
--- a/drivers/media/platform/qcom/venus/core.c
+++ b/drivers/media/platform/qcom/venus/core.c
@@ -1074,7 +1074,6 @@ static const struct venus_resources sc7280_res = {
.dec_nodename = "video-decoder",
.enc_nodename = "video-encoder",
};
-#endif
static const struct bw_tbl qcm2290_bw_table_dec[] = {
{ 352800, 597000, 0, 746000, 0 }, /* 1080p@30 + 720p@30 */
@@ -1125,12 +1124,15 @@ static const struct venus_resources qcm2290_res = {
.enc_nodename = "video-encoder",
.min_fw = &min_fw,
};
+#endif
static const struct of_device_id venus_dt_match[] = {
{ .compatible = "qcom,msm8916-venus", .data = &msm8916_res, },
{ .compatible = "qcom,msm8996-venus", .data = &msm8996_res, },
{ .compatible = "qcom,msm8998-venus", .data = &msm8998_res, },
+#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS))
{ .compatible = "qcom,qcm2290-venus", .data = &qcm2290_res, },
+#endif
{ .compatible = "qcom,sc7180-venus", .data = &sc7180_res, },
#if (!IS_ENABLED(CONFIG_VIDEO_QCOM_IRIS))
{ .compatible = "qcom,sc7280-venus", .data = &sc7280_res, },
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH 16/16] arm64: dts: qcom: agatti: add higher OPP levels
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (14 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 15/16] media: venus: skip QCM2290 if Iris driver is enabled Dmitry Baryshkov
@ 2026-05-07 6:42 ` Dmitry Baryshkov
2026-05-07 13:02 ` [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Vikash Garodia
16 siblings, 0 replies; 36+ messages in thread
From: Dmitry Baryshkov @ 2026-05-07 6:42 UTC (permalink / raw)
To: Vikash Garodia, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Add additional OPP entries for the Agatti platform to support higher
operating frequencies as specified in the hardware documentation.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/agatti.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi
index 8a7337239b1e..fd40aa59878a 100644
--- a/arch/arm64/boot/dts/qcom/agatti.dtsi
+++ b/arch/arm64/boot/dts/qcom/agatti.dtsi
@@ -2455,6 +2455,16 @@ opp-240000000 {
opp-hz = /bits/ 64 <240000000>;
required-opps = <&rpmpd_opp_svs>;
};
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
};
};
--
2.47.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform
2026-05-07 6:42 [PATCH 00/16] media: iris: Add AR50LT core support and enable Agatti platform Dmitry Baryshkov
` (15 preceding siblings ...)
2026-05-07 6:42 ` [PATCH 16/16] arm64: dts: qcom: agatti: add higher OPP levels Dmitry Baryshkov
@ 2026-05-07 13:02 ` Vikash Garodia
16 siblings, 0 replies; 36+ messages in thread
From: Vikash Garodia @ 2026-05-07 13:02 UTC (permalink / raw)
To: Dmitry Baryshkov, Abhinav Kumar, Bryan O'Donoghue,
Mauro Carvalho Chehab, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote:
> This series adds support for the AR50Lt VPU core to the iris driver and
> enables the Agatti SoC to use Gen2 firmware and HFI.
>
> AR50Lt introduces a few platform-specific requirements that need to be
> handled in the iris core and VPU abstraction layer. To accommodate
> this, the series adds minimal hooks and updates needed to allow the
> firmware to operate correctly on AR50Lt without impacting existing
> supported platforms.
>
> Additionally, the series wires up Agatti to use the Gen2 firmware and
> HFI path, aligning it with newer generations of supported Qualcomm
> video hardware.
>
> v4l2-compliance results:
>
> v4l2-compliance -d /dev/video1 -s
> v4l2-compliance 1.33.0-5421, 64 bits, 64-bit time_t
> v4l2-compliance SHA: af4a91dea9a2 2025-10-29 10:33:25
>
> Compliance test for iris_driver device /dev/video1:
>
> Driver Info:
> Driver name : iris_driver
> Card type : Iris Encoder
> Bus info : platform:5a00000.video-codec
> Driver version : 6.19.0
> Capabilities : 0x84204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Device Capabilities
> Device Caps : 0x04204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Detected Stateful Encoder
>
> Required ioctls:
> test VIDIOC_QUERYCAP: OK
> test invalid ioctls: OK
>
> Allow for multiple opens:
> test second /dev/video1 open: OK
> test VIDIOC_QUERYCAP: OK
> test VIDIOC_G/S_PRIORITY: OK
> test for unlimited opens: OK
>
> Debug ioctls:
> test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> test VIDIOC_ENUMAUDIO: OK (Not Supported)
> test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDIO: OK (Not Supported)
> Inputs: 0 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls:
> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> test VIDIOC_QUERYCTRL: OK
> test VIDIOC_G/S_CTRL: OK
> test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> Standard Controls: 43 Private Controls: 0
>
> Format ioctls:
> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> test VIDIOC_G/S_PARM: OK
> test VIDIOC_G_FBUF: OK (Not Supported)
> test VIDIOC_G_FMT: OK
> test VIDIOC_TRY_FMT: OK
> test VIDIOC_S_FMT: OK
> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> test Cropping: OK
> test Composing: OK (Not Supported)
> test Scaling: OK (Not Supported)
>
> Codec ioctls:
> test VIDIOC_(TRY_)ENCODER_CMD: OK
> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
>
> Buffer ioctls:
> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> test CREATE_BUFS maximum buffers: OK
> test VIDIOC_REMOVE_BUFS: OK
> test VIDIOC_EXPBUF: OK
> test Requests: OK (Not Supported)
> test blocking wait: OK
>
> Test input 0:
>
> Streaming ioctls:
> test read/write: OK67609.731994] use of bytesused == 0 is deprecated and will be removed in the future,
> [67609.741833] use the actual size instead.
> m (Not Supported)
> Video Capture Multiplanar: Captured 61 buffers
> test MMAP (select, REQBUFS): OK
> Video Capture Multiplanar: Captured 61 buffers
> test MMAP (epoll, REQBUFS): OK
> Video Capture Multiplanar: Captured 61 buffers
> test MMAP (select, CREATE_BUFS): OK
> Video Capture Multiplanar: Captured 61 buffers
> test MMAP (epoll, CREATE_BUFS): OK
> test USERPTR (select): OK (Not Supported)
> test DMABUF: Cannot test, specify --expbuf-device
>
> Total for iris_driver device /dev/video1: 54, Succeeded: 54, Failed: 0, Warnings: 0
>
> v4l2-compliance -d /dev/video0 -s5 --stream-from=/media/FVDO_Freeway_720p.264
> v4l2-compliance 1.33.0-5421, 64 bits, 64-bit time_t
> v4l2-compliance SHA: af4a91dea9a2 2025-10-29 10:33:25
>
> Compliance test for iris_driver device /dev/video0:
>
> Driver Info:
> Driver name : iris_driver
> Card type : Iris Decoder
> Bus info : platform:5a00000.video-codec
> Driver version : 6.19.0
> Capabilities : 0x84204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Device Capabilities
> Device Caps : 0x04204000
> Video Memory-to-Memory Multiplanar
> Streaming
> Extended Pix Format
> Detected Stateful Decoder
>
> Required ioctls:
> test VIDIOC_QUERYCAP: OK
> test invalid ioctls: OK
>
> Allow for multiple opens:
> test second /dev/video0 open: OK
> test VIDIOC_QUERYCAP: OK
> test VIDIOC_G/S_PRIORITY: OK
> test for unlimited opens: OK
>
> Debug ioctls:
> test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> test VIDIOC_ENUMAUDIO: OK (Not Supported)
> test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDIO: OK (Not Supported)
> Inputs: 0 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls:
> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
> test VIDIOC_QUERYCTRL: OK
> test VIDIOC_G/S_CTRL: OK
> test VIDIOC_G/S/TRY_EXT_CTRLS: OK
> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> Standard Controls: 12 Private Controls: 0
>
> Format ioctls:
> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> test VIDIOC_G/S_PARM: OK (Not Supported)
> test VIDIOC_G_FBUF: OK (Not Supported)
> test VIDIOC_G_FMT: OK
> test VIDIOC_TRY_FMT: OK
> test VIDIOC_S_FMT: OK
> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> test Cropping: OK
> test Composing: OK
> test Scaling: OK (Not Supported)
>
> Codec ioctls:
> test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> test VIDIOC_(TRY_)DECODER_CMD: OK
>
> Buffer ioctls:
> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> test CREATE_BUFS maximum buffers: OK
> test VIDIOC_REMOVE_BUFS: OK
> test VIDIOC_EXPBUF: OK
> test Requests: OK (Not Supported)
> test blocking wait: OK
>
> Test input 0:
>
> Streaming ioctls:
> test read/write: OK (Not Supported)
> the input file is smaller than 7077888 bytes
> Video Capture Multiplanar: Captured 465 buffers
> test MMAP (select, REQBUFS): OK
> the input file is smaller than 7077888 bytes
> Video Capture Multiplanar: Captured 465 buffers
> test MMAP (epoll, REQBUFS): OK
> the input file is smaller than 7077888 bytes
> Video Capture Multiplanar: Captured 465 buffers
> test MMAP (select, CREATE_BUFS): OK
> the input file is smaller than 7077888 bytes
> Video Capture Multiplanar: Captured 465 buffers
> test MMAP (epoll, CREATE_BUFS): OK
> test USERPTR (select): OK (Not Supported)
> test DMABUF: Cannot test, specify --expbuf-device
>
> Total for iris_driver device /dev/video0: 54, Succeeded: 54, Failed: 0, Warnings: 0
>
> Fluster results for HFI Gen2 firmware:
>
> ./fluster.py run -ts JVT-AVC_V1 -d GStreamer-H.264-V4L2-Gst1.0 - 77/135
Thank you for listing out the failure ones, it makes it easier to review
the failing ones.
> The failing test case:
> - Unsupported profile: H.264 Extended profile is deprecated.
> - BA3_SVA_C
> - Interlaced content is not supported yet.
> - CABREF3_Sand_D
> - CAFI1_SVA_C
> - CAMA1_Sony_C
> - CAMA1_TOSHIBA_B
> - CAMA3_Sand_E
> - CAMACI3_Sony_C
> - CAMANL1_TOSHIBA_B
> - CAMANL2_TOSHIBA_B
> - CAMANL3_Sand_E
> - CAMASL3_Sony_B
> - CAMP_MOT_MBAFF_L30
> - CAMP_MOT_MBAFF_L31
> - CANLMA2_Sony_C
> - CANLMA3_Sony_C
> - CAPA1_TOSHIBA_B
> - CAPAMA3_Sand_F
> - CVCANLMA2_Sony_C
> - CVFI1_SVA_C
> - CVFI1_Sony_D
> - CVFI2_SVA_C
> - CVFI2_Sony_H
> - CVMA1_Sony_D
> - CVMA1_TOSHIBA_B
> - CVMANL1_TOSHIBA_B
> - CVMANL2_TOSHIBA_B
> - CVMAPAQP3_Sony_E
> - CVMAQP2_Sony_G
> - CVMAQP3_Sony_D
> - CVMP_MOT_FLD_L30_B
> - CVMP_MOT_FRM_L31
> - CVNLFI1_Sony_C
> - CVNLFI2_Sony_H
> - CVPA1_TOSHIBA_B
> - FI1_Sony_E
> - MR6_BT_B
> - MR7_BT_B
> - MR8_BT_B
> - MR9_BT_B
> - Sharp_MP_Field_1_B
> - Sharp_MP_Field_2_B
> - Sharp_MP_Field_3_B
> - Sharp_MP_PAFF_1r2
> - Sharp_MP_PAFF_2r
> - cabac_mot_fld0_full
> - cabac_mot_mbaff0_full
> - cabac_mot_picaff0_full
> - cama1_vtc_c
> - cama2_vtc_b
> - cama3_vtc_b
> - cavlc_mot_fld0_full_B
> - cavlc_mot_mbaff0_full_B
> - cavlc_mot_picaff0_full_B
> - Unsupported bitstream: num_slice_group_minus1 > 0 (slice groups not supported by hardware).
> - FM1_BT_B
> - FM1_FT_E
> - FM2_SVA_C
> - Unsupported bitstream: SP slice type is not supported by hardware.
> - SP1_BT_A
> - sp2_bt_b
>
> ./fluster.py run -ts JCT-VC-HEVC_V1 -d GStreamer-H.265-V4L2-Gst1.0 - 113/147
> The failing test case:
> - Unsupported level
> - AMP_D_Hisilicon_3
> - AMP_E_Hisilicon_3
> - AMP_F_Hisilicon_3
> - DELTAQP_A_BRCM_4
> - IPRED_A_docomo_2
> - IPRED_C_Mitsubishi_3
> - LS_A_Orange_2
> - LS_B_Orange_4
> - PPS_A_qualcomm_7
> - RAP_B_Bossen_2
> - RPS_F_docomo_2
> - SAO_G_Canon_3
> - SDH_A_Orange_4
> - 10bit content not supported yet
> - DBLK_A_MAIN10_VIXS_4
> - INITQP_B_Main10_Sony_1
> - TSUNEQBD_A_MAIN10_Technicolor_2
> - WPP_A_ericsson_MAIN10_2
> - WPP_B_ericsson_MAIN10_2
> - WPP_C_ericsson_MAIN10_2
> - WPP_D_ericsson_MAIN10_2
> - WPP_E_ericsson_MAIN10_2
> - WPP_F_ericsson_MAIN10_2
> - WP_A_MAIN10_Toshiba_3
> - WP_MAIN10_B_Toshiba_3
> - Unsupported resolution
> - AMP_A_Samsung_7 - resolution is higher than max supported
> - AMP_B_Samsung_7 - resolution is higher than max supported
> - PICSIZE_A_Bossen_1 - resolution is higher than max supported
> - PICSIZE_B_Bossen_1 - resolution is higher than max supported
> - PICSIZE_C_Bossen_1 - resolution is higher than max supported
> - PICSIZE_D_Bossen_1 - resolution is higher than max supported
> - TUSIZE_A_Samsung_1 - resolution is higher than max supported
> - WPP_D_ericsson_MAIN_2 - resolution is lower than min supported
> - CRC mismatch
> - RAP_A_docomo_6
> - CRC mismatch - bitstream issue - fails with ffmpeg sw decoder as well
> - VPSSPSPPS_A_MainConcept_1
>
> ./fluster.py run -ts VP9-TEST-VECTORS -d GStreamer-VP9-V4L2-Gst1.0 -j1 - 206/305
> The failing test case:
> - Unsupported resolution
> - vp90-2-02-size-08x08.webm
> - vp90-2-02-size-08x10.webm
> - vp90-2-02-size-08x16.webm
> - vp90-2-02-size-08x18.webm
> - vp90-2-02-size-08x32.webm
> - vp90-2-02-size-08x34.webm
> - vp90-2-02-size-08x64.webm
> - vp90-2-02-size-08x66.webm
> - vp90-2-02-size-10x08.webm
> - vp90-2-02-size-10x10.webm
> - vp90-2-02-size-10x16.webm
> - vp90-2-02-size-10x18.webm
> - vp90-2-02-size-10x32.webm
> - vp90-2-02-size-10x34.webm
> - vp90-2-02-size-10x64.webm
> - vp90-2-02-size-10x66.webm
> - vp90-2-02-size-16x08.webm
> - vp90-2-02-size-16x10.webm
> - vp90-2-02-size-16x16.webm
> - vp90-2-02-size-16x18.webm
> - vp90-2-02-size-16x32.webm
> - vp90-2-02-size-16x34.webm
> - vp90-2-02-size-16x64.webm
> - vp90-2-02-size-16x66.webm
> - vp90-2-02-size-18x08.webm
> - vp90-2-02-size-18x10.webm
> - vp90-2-02-size-18x16.webm
> - vp90-2-02-size-18x18.webm
> - vp90-2-02-size-18x32.webm
> - vp90-2-02-size-18x34.webm
> - vp90-2-02-size-18x64.webm
> - vp90-2-02-size-18x66.webm
> - vp90-2-02-size-32x08.webm
> - vp90-2-02-size-32x10.webm
> - vp90-2-02-size-32x16.webm
> - vp90-2-02-size-32x18.webm
> - vp90-2-02-size-32x32.webm
> - vp90-2-02-size-32x34.webm
> - vp90-2-02-size-32x64.webm
> - vp90-2-02-size-32x66.webm
> - vp90-2-02-size-34x08.webm
> - vp90-2-02-size-34x10.webm
> - vp90-2-02-size-34x16.webm
> - vp90-2-02-size-34x18.webm
> - vp90-2-02-size-34x32.webm
> - vp90-2-02-size-34x34.webm
> - vp90-2-02-size-34x64.webm
> - vp90-2-02-size-34x66.webm
> - vp90-2-02-size-64x08.webm
> - vp90-2-02-size-64x10.webm
> - vp90-2-02-size-64x16.webm
> - vp90-2-02-size-64x18.webm
> - vp90-2-02-size-64x32.webm
> - vp90-2-02-size-64x34.webm
> - vp90-2-02-size-64x64.webm
> - vp90-2-02-size-64x66.webm
> - vp90-2-02-size-66x08.webm
> - vp90-2-02-size-66x10.webm
> - vp90-2-02-size-66x16.webm
> - vp90-2-02-size-66x18.webm
> - vp90-2-02-size-66x32.webm
> - vp90-2-02-size-66x34.webm
> - vp90-2-02-size-66x64.webm
> - vp90-2-02-size-66x66.webm
> - vp90-2-08-tile_1x8.webm - resolution is higher than max supported
> - vp90-2-08-tile_1x8_frame_parallel.webm - resolution is higher than max supported
> - vp90-2-14-resize-10frames-fp-tiles-1-2-4-8.webm - resolution is higher than max supported
> - vp90-2-14-resize-10frames-fp-tiles-1-8.webm - resolution is higher than max supported
> - vp90-2-14-resize-10frames-fp-tiles-2-8.webm - resolution is higher than max supported
> - vp90-2-14-resize-10frames-fp-tiles-4-8.webm - resolution is higher than max supported
> - vp90-2-14-resize-10frames-fp-tiles-8-1.webm - resolution is higher than max supported
> - vp90-2-14-resize-10frames-fp-tiles-8-2.webm - resolution is higher than max supported
> - vp90-2-14-resize-10frames-fp-tiles-8-4-2-1.webm - resolution is higher than max supported
> - vp90-2-14-resize-10frames-fp-tiles-8-4.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-1-16.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-1-2-4-8-16.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-1-8.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-16-1.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-16-2.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-16-4.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-16-8-4-2-1.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-16-8.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-2-16.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-2-8.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-4-16.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-4-8.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-8-1.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-8-16.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-8-2.webm - resolution is higher than max supported
> - vp90-2-14-resize-fp-tiles-8-4.webm - resolution is higher than max supported
> - Unsupported format
> - vp91-2-04-yuv422.webm
> - vp91-2-04-yuv444.webm
> - CRC mismatch
> - vp90-2-22-svc_1280x720_3.ivf
> - Unsupported resolution after sequence change
> - vp90-2-18-resize.ivf
> - vp90-2-21-resize_inter_320x180_5_1-2.webm
> - vp90-2-21-resize_inter_320x180_7_1-2.webm
> - vp90-2-21-resize_inter_320x240_5_1-2.webm
> - p90-2-21-resize_inter_320x240_7_1-2.webm
> - Unsupported stream
> - vp90-2-16-intra-only.webm
>
> Fluster results for HFI Gen1 firmware:
>
> Tests failing with the Venus driver, but passing with the Iris:
> - H.264: BA3_SVA_C
>
> - H.265: ipcm_A_NEC_3, ipcm_B_NEC_3, ipcm_C_NEC_3, ipcm_D_NEC_3,
> ipcm_E_NEC_2, IPRED_B_Nokia_3, VPSSPSPPS_A_MainConcept_1
>
> - VP9: vp90-2-14-resize-10frames-fp-tiles-1-2.webm,
> vp90-2-14-resize-10frames-fp-tiles-2-1.webm,
> vp90-2-14-resize-fp-tiles-1-2.webm,
> vp90-2-14-resize-fp-tiles-2-1.webm,
> vp90-2-14-resize-fp-tiles-4-1.webm,
> vp90-2-14-resize-fp-tiles-4-2.webm,
> vp90-2-15-segkey.webm
>
Looks promising
> Tests failing with the Iris driver, but passing with the Venus (due to
> interlaced H.264 being not supported yet):
>
> - H.264: cabac_mot_fld0_full, cabac_mot_mbaff0_full,
> cabac_mot_picaff0_full, CABREF3_Sand_D, CAFI1_SVA_C, CAMA1_Sony_C,
> CAMA1_TOSHIBA_B, cama1_vtc_c, cama2_vtc_b, CAMA3_Sand_E, cama3_vtc_b,
> CAMACI3_Sony_C, CAMANL1_TOSHIBA_B, CAMANL2_TOSHIBA_B, CAMANL3_Sand_E,
> CAMASL3_Sony_B, CAMP_MOT_MBAFF_L30, CAMP_MOT_MBAFF_L31,
> CANLMA2_Sony_C, CANLMA3_Sony_C, CAPA1_TOSHIBA_B, CAPAMA3_Sand_F,
> cavlc_mot_fld0_full_B, cavlc_mot_mbaff0_full_B,
> cavlc_mot_picaff0_full_B, CVCANLMA2_Sony_C, CVFI1_Sony_D, CVFI1_SVA_C,
> CVFI2_Sony_H, CVFI2_SVA_C, CVMA1_Sony_D, CVMA1_TOSHIBA_B,
> CVMANL1_TOSHIBA_B, CVMANL2_TOSHIBA_B, CVMAPAQP3_Sony_E,
> CVMAQP2_Sony_G, CVMAQP3_Sony_D, CVMP_MOT_FLD_L30_B,
> CVMP_MOT_FRM_L31_B, CVNLFI1_Sony_C, CVNLFI2_Sony_H, CVPA1_TOSHIBA_B,
> FI1_Sony_E, MR9_BT_B, Sharp_MP_Field_1_B, Sharp_MP_Field_2_B,
> Sharp_MP_Field_3_B, Sharp_MP_PAFF_1r2, Sharp_MP_PAFF_2r
>
> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> Dikshita Agarwal (11):
> media: iris: Skip UBWC configuration when not supported
> media: iris: Filter UBWC raw formats based on hardware capabilities
> media: iris: Introduce set_preset_register as a vpu_op
> media: iris: Introduce interrupt_init as a vpu_op
> media: iris: add vpu op hook to disable ARP buffer
> media: iris: Add platform data field for watchdog interrupt mask
> media: iris: Add platform flag for instantaneous bandwidth voting
> media: iris: Add framework support for AR50_LITE video core
> media: iris: Introduce buffer size calculations for AR50LT
> media: iris: add Gen2 firmware support on the Agatti platform
> arm64: dts: qcom: agatti: add higher OPP levels
>
> Dmitry Baryshkov (5):
> media: iris: skip PIPE if it is not supported by the platform
> media: iris: add minimal GET_PROPERTY implementation
> media: iris: update buffer requirements based on received info
> media: iris: implement support for the Agatti platform
> media: venus: skip QCM2290 if Iris driver is enabled
>
> arch/arm64/boot/dts/qcom/agatti.dtsi | 10 +
> drivers/media/platform/qcom/iris/Makefile | 2 +
> drivers/media/platform/qcom/iris/iris_core.c | 4 +
> drivers/media/platform/qcom/iris/iris_ctrls.c | 3 +
> drivers/media/platform/qcom/iris/iris_hfi_common.c | 4 +
> drivers/media/platform/qcom/iris/iris_hfi_common.h | 1 +
> drivers/media/platform/qcom/iris/iris_hfi_gen1.c | 227 ++++++++
> .../platform/qcom/iris/iris_hfi_gen1_command.c | 21 +
> .../platform/qcom/iris/iris_hfi_gen1_defines.h | 15 +
> .../platform/qcom/iris/iris_hfi_gen1_response.c | 78 +++
> drivers/media/platform/qcom/iris/iris_hfi_gen2.c | 613 +++++++++++++++++++++
> .../platform/qcom/iris/iris_hfi_gen2_packet.c | 3 +
> .../platform/qcom/iris/iris_platform_common.h | 11 +
> .../media/platform/qcom/iris/iris_platform_vpu2.c | 6 +
> .../media/platform/qcom/iris/iris_platform_vpu3x.c | 10 +
> .../platform/qcom/iris/iris_platform_vpu_ar50lt.c | 118 ++++
> drivers/media/platform/qcom/iris/iris_probe.c | 4 +
> drivers/media/platform/qcom/iris/iris_resources.c | 2 +
> drivers/media/platform/qcom/iris/iris_vdec.c | 9 +
> drivers/media/platform/qcom/iris/iris_venc.c | 9 +
> drivers/media/platform/qcom/iris/iris_vpu2.c | 2 +
> drivers/media/platform/qcom/iris/iris_vpu3x.c | 6 +
> drivers/media/platform/qcom/iris/iris_vpu4x.c | 2 +
> drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c | 156 ++++++
> drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 414 ++++++++++++++
> drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 38 ++
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 17 +-
> drivers/media/platform/qcom/iris/iris_vpu_common.h | 5 +
> .../platform/qcom/iris/iris_vpu_register_defines.h | 1 -
> drivers/media/platform/qcom/venus/core.c | 4 +-
> 30 files changed, 1786 insertions(+), 9 deletions(-)
> ---
> base-commit: bee6ea30c48788e18348309f891ed8afbf7702ac
> change-id: 20260507-iris-ar50lt-06228469aa5b
> prerequisite-message-id: 20260209-iris-venus-fix-sm8250-v5-0-0a22365d3585@oss.qualcomm.com
> prerequisite-patch-id: 8948139735836adb9fbc51d93b969911dc5b38e8
> prerequisite-patch-id: 7ec91bd0149f347c479c906e73cabaa28601ab3d
> prerequisite-patch-id: c711522b63f640b7504767b3af7adc05a0b36cac
> prerequisite-patch-id: 42b9cd5e0fd6fd99eae267c78b239333adff7637
> prerequisite-patch-id: 11c487545e2462ff0a515d689863c3f7f25f9449
> prerequisite-message-id: 20260327-venus-iris-flip-switch-v5-0-2f4b6c636927@oss.qualcomm.com
> prerequisite-patch-id: 579d712ec3f942ba0c362e242c71361c151092b5
> prerequisite-patch-id: fa4629a3909fbae3917d8c067cce4f673ee857c0
> prerequisite-patch-id: cbbd40736f7a797ff76b0fe2b1ddfb559e14e666
> prerequisite-patch-id: 5b50917dcfef01db13af320cbd1cba15fd5fa16f
> prerequisite-message-id: 20260507-iris-ubwc-v5-0-e9a3aee53c49@oss.qualcomm.com
> prerequisite-patch-id: af2ff44a7b919da2ee06cc40893fbcd3f65d32f7
> prerequisite-patch-id: f3a2b9ef97be3fa250ea0a6467b2d5a782315aa5
> prerequisite-patch-id: 6bdd2119448e84aacbdc6a54d999d47fc69dac81
> prerequisite-patch-id: 38cc9502c93c71324f1a11a1fd438374fc41ca84
> prerequisite-patch-id: 059d1f35274246575ca4fa9b4ee33cd4801479d1
> prerequisite-patch-id: 1cf4ea774a145cdba617eb8be5c1f7afe5817772
> prerequisite-patch-id: 46375dcd0da4629e6031336351b9cf688691d7c5
> prerequisite-message-id: 20260329-iris-platform-data-v11-0-eea672b03a95@oss.qualcomm.com
> prerequisite-patch-id: 34d473ba50399f8cfaf583f4def12de776aad65d
> prerequisite-patch-id: 5a6a2b41c9312687512db5d12bac95114b8d8719
> prerequisite-patch-id: e6ec4cd9eb5e93f3443f5f496a1b990a95b5d96d
> prerequisite-patch-id: 4be4bbb454444d6f314c2b6ad6a73290184e6d57
> prerequisite-patch-id: fd9cd7882f2a8f1b6141f48ff5c3da708839d03f
> prerequisite-patch-id: 952471fa5477280d399978c05fbc9bfe6d2d33b0
> prerequisite-patch-id: 01c5b37358de833f85de1954f770fe0489818a16
> prerequisite-patch-id: dd14b47d6cd8ff14d1bc78c187c061f6fe262fda
> prerequisite-patch-id: f4eba0865e7f91bce3fb4b2c627ee123980e0ff9
> prerequisite-patch-id: 72984784b916e2d94ede8ab7d52cc0dedfa37c41
> prerequisite-patch-id: 2fabf4e36b4e4f74b27fe75133ab8ba0ec9b6e3d
> prerequisite-message-id: 20260330-iris-remote-fmts-v3-1-a26ab9e90101@oss.qualcomm.com
> prerequisite-patch-id: aab511a6975936fb0198697fca7b61cc2277e1b4
> prerequisite-change-id: 20260429-kodiak-gen2-support-v4-a7f055f15afb:v4
> prerequisite-patch-id: d4f40aee0948578a4195456554ba88c228d5bf7f
> prerequisite-patch-id: 38d706b45998b7b5fbf90e27ecf9c856354f5a23
> prerequisite-patch-id: 16ea0271e2c2c708c1ad1ba3490f4b05fc04173d
>
> Best regards,
> --
> With best wishes
> Dmitry
>
^ permalink raw reply [flat|nested] 36+ messages in thread