From: "Xuyang Dong" <dongxuyang@eswincomputing.com>
To: "Stephen Boyd" <sboyd@kernel.org>, "Brian Masney" <bmasney@redhat.com>
Cc: mturquette@baylibre.com, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
p.zabel@pengutronix.de, huangyifeng@eswincomputing.com,
benoit.monin@bootlin.com, ningyu@eswincomputing.com,
linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com
Subject: Re: Re: Re: Re: [PATCH v3 2/3] clk: eswin: Add eic7700 HSP clock driver
Date: Wed, 29 Apr 2026 17:38:51 +0800 (GMT+08:00) [thread overview]
Message-ID: <4257942f.5c6d.19dd89b06f8.Coremail.dongxuyang@eswincomputing.com> (raw)
In-Reply-To: <177742748214.5403.15526965667317467444@localhost.localdomain>
> >
> > The common gate API, the HSP private API, and the reset driver all access
> > the same register space.
> > Therefore, they need to be protected by the same data->lock.
> >
>
> If everything is accessing registers through regmap why aren't we using
> the builtin lock with struct regmap_config::use_raw_spinlock? I don't
> understand why we're rolling our own here.
Hi Stephen,
In the HSP clock driver and reset driver, there are three components that
access the HSP register space: a common gate clock, a custom gate clock
(i.e., 0x800), and a reset.
1. The common gate uses eswin_clk_register_gate() to register a gate clock
via devm_clk_hw_register_gate_parent_data(). It accesses the register
using clk_gate_endisable().
static void clk_gate_endisable(struct clk_hw *hw, int enable)
{
struct clk_gate *gate = to_clk_gate(hw);
unsigned long flags;
if (gate->lock)
spin_lock_irqsave(gate->lock, flags);
else
__acquire(gate->lock);
...
if (gate->lock)
spin_unlock_irqrestore(gate->lock, flags);
else
__release(gate->lock);
}
The gate->lock in use is the data->lock passed in from the clock driver.
2. The custom gate uses hsp_clk_register_gate() to register a gate clock.
It accesses the register using hsp_clk_gate_endisable().
static void hsp_clk_gate_endisable(struct clk_hw *hw, int enable)
{
struct eic7700_hsp_clk_gate *gate = to_gate_clk(hw);
guard(spinlock_irqsave)(gate->lock);
...
}
The gate->lock in use is the same data->lock passed in from the clock
driver.
3. The reset uses eic7700_hsp_reset_assert() and
eic7700_hsp_reset_deassert(), which call regmap_assign_bits() to access
the register.
All three methods access the same register space; therefore, they must be
protected by the same lock (data->lock).
That's why we introduced eic7700_hsp_regmap_lock/unlock for
eic7700_hsp_regmap_config.
eic7700_hsp_regmap_config = {
.lock = eic7700_hsp_regmap_lock,
.unlock = eic7700_hsp_regmap_unlock,
.lock_arg = lock_ctx,
};
The 'lock_ctx->lock' in eic7700_hsp_regmap_lock/unlock is the 'data->lock'.
static void eic7700_hsp_regmap_lock(void *arg)
__acquires(lock_ctx->lock)
{
struct eic7700_hsp_regmap_lock *const lock_ctx = arg;
unsigned long flags;
spin_lock_irqsave(lock_ctx->lock, flags);
lock_ctx->flags = flags;
}
The similar approach can be found in clk-imx8ulp-sim-lpav.c.
The annotations what we mentioned previously is the above
"__acquires(lock_ctx->lock)".
Best regards,
Xuyang Dong
next prev parent reply other threads:[~2026-04-29 9:39 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-23 9:09 [PATCH v3 0/3] Add driver support for ESWIN EIC7700 HSP clock and reset generator Xuyang Dong
2026-04-23 9:10 ` [PATCH v3 1/3] dt-bindings: clock: Add ESWIN eic7700 " dongxuyang
2026-04-23 9:11 ` [PATCH v3 2/3] clk: eswin: Add eic7700 HSP clock driver dongxuyang
2026-04-23 15:37 ` Brian Masney
2026-04-24 10:44 ` Xuyang Dong
2026-04-24 11:15 ` Brian Masney
2026-04-28 0:21 ` Stephen Boyd
2026-04-28 9:21 ` Xuyang Dong
2026-04-28 13:39 ` Brian Masney
2026-04-29 1:51 ` Stephen Boyd
2026-04-29 9:38 ` Xuyang Dong [this message]
2026-04-29 13:54 ` Brian Masney
2026-04-23 15:51 ` Benoît Monin
2026-04-23 9:12 ` [PATCH v3 3/3] reset: eswin: Add eic7700 HSP reset driver dongxuyang
2026-04-23 16:09 ` Philipp Zabel
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