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From: 李志 <lizhi2@eswincomputing.com>
To: "Conor Dooley" <conor@kernel.org>
Cc: sashiko-reviews@lists.linux.dev, robh@kernel.org,
	devicetree@vger.kernel.org, conor+dt@kernel.org
Subject: Re: Re: [PATCH net v2 1/5] dt-bindings: ethernet: eswin: add optional TXD and RXD delay register offsets
Date: Tue, 19 May 2026 17:51:05 +0800 (GMT+08:00)	[thread overview]
Message-ID: <44d1ad42.8505.19e3fa56a49.Coremail.lizhi2@eswincomputing.com> (raw)
In-Reply-To: <20260519-thinness-slashing-cc0310904419@spud>




> -----Original Messages-----
> From: "Conor Dooley" <conor@kernel.org>
> Send time:Tuesday, 19/05/2026 17:11:59
> To: sashiko-reviews@lists.linux.dev
> Cc: lizhi2@eswincomputing.com, robh@kernel.org, devicetree@vger.kernel.org, conor+dt@kernel.org
> Subject: Re: [PATCH net v2 1/5] dt-bindings: ethernet: eswin: add optional TXD and RXD delay register offsets
> 
> On Tue, May 19, 2026 at 02:23:33AM +0000, sashiko-bot@kernel.org wrote:
> > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> > - [Medium] Missing `minItems: 4` constraint makes the newly added optional cells mandatory, breaking schema backward compatibility.
> > --
> > 
> > commit 2992483df88af2823c275fc86187f7e38acbee5c
> > Author: Zhi Li <lizhi2@eswincomputing.com>
> > 
> > dt-bindings: ethernet: eswin: add optional TXD and RXD delay register offsets
> > 
> > This commit documents two optional cells in the eswin,hsp-sp-csr property
> > for the TXD and RXD delay control register offsets.
> > 
> > > diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> > > --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> > > +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml
> > 
> > [ ... ]
> > 
> > > @@ -82,6 +91,8 @@ properties:
> > >            - description: Offset of AXI clock controller Low-Power request
> > >                           register
> > >            - description: Offset of register controlling TX/RX clock delay
> > > +          - description: Optional offset of register controlling TXD delay
> > > +          - description: Optional offset of register controlling RXD delay
> > 
> > Will this make the two new offsets strictly required instead of optional?
> > 
> > In dt-schema, when an items list defines a tuple, minItems implicitly
> > defaults to the total number of items in that list. By increasing the list
> > from 4 to 6 items without adding a minItems: 4 constraint to the inner items
> > list, won't validation now strictly require exactly 6 items?
> > 
> > Could this cause dt_binding_check to fail for existing device trees that
> > correctly specify only the original 4 elements?
> 
> Looks like a valid complaint to me.
> pw-bot: changes-requested
> 
You're right, this is a valid issue.

I'll fix it in v3 by adding only minItems: 4 to preserve backward
compatibility with existing 4-cell device trees.

Should I drop your Acked-by in v3 due to the schema change, or should
it be retained?

Thanks.

  reply	other threads:[~2026-05-19  9:51 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-18  2:19 [PATCH net v2 0/5] net: stmmac: eic7700: fix delay calculation and initialization ordering lizhi2
2026-05-18  2:20 ` [PATCH net v2 1/5] dt-bindings: ethernet: eswin: add optional TXD and RXD delay register offsets lizhi2
2026-05-19  2:23   ` sashiko-bot
2026-05-19  9:11     ` Conor Dooley
2026-05-19  9:51       ` 李志 [this message]
2026-05-19  9:55         ` Conor Dooley
2026-05-18  2:20 ` [PATCH net v2 2/5] net: stmmac: eswin: fix HSP CSR init ordering after clock enable lizhi2
2026-05-19  2:23   ` sashiko-bot
2026-05-19  9:58     ` 李志
2026-05-18  2:21 ` [PATCH net v2 3/5] net: stmmac: eswin: clear TXD and RXD delay registers during initialization lizhi2
2026-05-18  2:21 ` [PATCH net v2 4/5] net: stmmac: eswin: correct RGMII delay granularity to 20 ps lizhi2
2026-05-18  2:22 ` [PATCH net v2 5/5] net: stmmac: eswin: validate RGMII delay values lizhi2

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