Re: [PATCH 1/6] drm/msm/a8xx: Add support for Adreno 830 GPU

[Akhil P Oommen <akhilpo@oss.qualcomm.com>]

On 8/11/2026 1:29 PM, Aaron Kling wrote:
>> From: Jie Zhang <jie.zhang@oss.qualcomm.com>
>> Add support for the Adreno 830 GPU present in SM8750 SoC. Adreno 830 GPU
>> belongs to the A8x Gen 1 family and it is architecturally close Adreno 840.
>> Add a new catalog entry along with the register list to enable support
>> for this GPU.
>> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
>>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 334 ++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/msm/adreno/a8xx_gpu.c     |   2 +-
>>  drivers/gpu/drm/msm/adreno/adreno_gpu.h   |   5 +
>>  3 files changed, 340 insertions(+), 1 deletion(-)
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index 90a0c7ffb3c8..418edde9104e 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1693,6 +1693,294 @@ static const struct adreno_info a7xx_gpus[] = {
>>  };
>>  DECLARE_ADRENO_GPULIST(a7xx);
>>
>> +static const struct adreno_reglist_pipe a830_nonctxt_regs[] = {
>> + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
>> + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00400000, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + /* Configure GBIF GX registers */
>> + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
>> + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
>> + /* Enable full concurrent resolve and unresolves */
>> + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
>> + /* Partially enable perf clear, Disable DINT to c/z be data forwarding */
>> + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) },
>> + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x0c000000, BIT(PIPE_BR) },
>> + /* Configure number of outstanding transactions to 32 */
>> + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
>> + /* Configure UCHE request time out to 16 cycles for CCU/UCHE arbitration */
>> + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
>> + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
>> + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
>> + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
>> + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
>> + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
>> + /* Enable contribution of all shader stages to SP perfcounters */
>> + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
>> + /*
>> + * BIT(26): Limit the number of wave-slots for Eviction buffer to 1 per ALU GRP
>> + * BIT(30): Disable LPAC auto-promotion
>> + */
>> + { REG_A7XX_SP_CHICKEN_BITS_1, BIT(26) | BIT(30), BIT(PIPE_NONE) },
>> + /*
>> + * BIT(22): Disable PS out of order retire
>> + * BIT(23): Enable half wave mode and MM instruction src&dst is half precision
>> + */
>> + { REG_A7XX_SP_CHICKEN_BITS_2, BIT(22) | BIT(23), BIT(PIPE_NONE) },
>> + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
>> + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080,  BIT(PIPE_NONE) },
>> + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
>> + /* Enable cubemap small miplevel optimization settings */
>> + /* BIT(26): Disable final clamp for bicubic filtering */
>> + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000724, BIT(PIPE_NONE) },
>> + /* Disable tag bank id hashing */
>> + { REG_A6XX_UCHE_MODE_CNTL, 0x00080000, BIT(PIPE_NONE) },
>> + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
>> + /* Limit gmem number of ways for GMEM requests in each set */
>> + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE)},
>> + /* Disable write slow pointer in data phase queue */
>> + { REG_A8XX_UCHE_HW_DBG_CNTL, BIT(8), BIT(PIPE_NONE) },
>> + /* Configure UCHE to CCU switchthreshold timeout cycles */
>> + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
>> + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BR) | BIT(PIPE_BV) },
>> + /* Disable redundant tile data optimization */
>> + { REG_A8XX_VSC_KMD_DBG_ECO_CNTL, BIT(11), BIT(PIPE_NONE)},
>> + { },
>> +};
>> +
>> +static const u32 a830_protect_regs[] = {
>> + A6XX_PROTECT_RDONLY(0x00000, 0x03a3),
>> + A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
>> + A6XX_PROTECT_NORDWR(0x00440, 0x001f),
>> + A6XX_PROTECT_RDONLY(0x00580, 0x005f),
>> + A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
>> + A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
>> + A6XX_PROTECT_RDONLY(0x00759, 0x0026),
>> + A6XX_PROTECT_RDONLY(0x00789, 0x0000),
>> + A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
>> + A6XX_PROTECT_NORDWR(0x00800, 0x0029),
>> + A6XX_PROTECT_NORDWR(0x00837, 0x00af),
>> + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
>> + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
>> + A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
>> + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
>> + A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
>> + A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
>> + A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
>> + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
>> + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
>> + A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff),
>> + A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
>> + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
>> + A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
>> + A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
>> + A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
>> + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
>> + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
>> + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
>> + A6XX_PROTECT_NORDWR(0x0ae00, 0x0000),
>> + A6XX_PROTECT_NORDWR(0x0ae02, 0x0004),
>> + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
>> + A6XX_PROTECT_NORDWR(0x0ae10, 0x036f),
>> + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
>> + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
>> + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
>> + A6XX_PROTECT_NORDWR(0x18400, 0x003f),
>> + A6XX_PROTECT_RDONLY(0x18440, 0x013f),
>> + A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
>> + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
>> + A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
>> + A6XX_PROTECT_RDONLY(0x1f878, 0x0787),
>> + A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
>> + A6XX_PROTECT_NORDWR(0x20000, 0x1fff),
>> + A6XX_PROTECT_NORDWR(0x27800, 0x007f),
>> + A6XX_PROTECT_RDONLY(0x27880, 0x0381),
>> + A6XX_PROTECT_NORDWR(0x27882, 0x0001),
>> + A6XX_PROTECT_NORDWR(0x27c02, 0x0000),
>> +};
>> +DECLARE_ADRENO_PROTECT(a830_protect, 64);
> 
> I have tested this on an AYN Odin 3, which has a CQ8725S SoC with
> A830. As-is, this change causes the device to fail to boot. Comparing
> to a different implementation of this support that I used previously,
> I found the operable difference is the count_max field here. Dropping
> that from 64 to 15 allows the device to boot and work as intended. I
> unfortunately don't have uart to see what the actual failure text is
> and provide any more information than this.

Maybe your stack is missing this patch:
https://lore.kernel.org/lkml/20260502-adreno-810-v5-5-bc9fd2bb788d@pm.me/

-Akhil

> 
> Aaron
>