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* Re: [PATCH 1/6] drm/msm/a8xx: Add support for Adreno 830 GPU
@ 2026-08-11  7:59 Aaron Kling
  2026-08-11 22:53 ` Akhil P Oommen
  0 siblings, 1 reply; 5+ messages in thread
From: Aaron Kling @ 2026-08-11  7:59 UTC (permalink / raw)
  To: Akhil P Oommen
  Cc: abhinav.kumar, David Airlie, Bjorn Andersson, Conor Dooley,
	devicetree, dri-devel, freedreno, Jessica Zhang, jie.zhang,
	Konrad Dybcio, Krzysztof Kozlowski, linux-arm-msm, linux-kernel,
	Dmitry Baryshkov, Maarten Lankhorst, marijn.suijten,
	Maxime Ripard, Rob Herring, robin.clark, sean, Simona Vetter,
	Thomas Zimmermann

> From: Jie Zhang <jie.zhang@oss.qualcomm.com>
> Add support for the Adreno 830 GPU present in SM8750 SoC. Adreno 830 GPU
> belongs to the A8x Gen 1 family and it is architecturally close Adreno 840.
> Add a new catalog entry along with the register list to enable support
> for this GPU.
> Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com>
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 334 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/msm/adreno/a8xx_gpu.c     |   2 +-
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h   |   5 +
>  3 files changed, 340 insertions(+), 1 deletion(-)
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 90a0c7ffb3c8..418edde9104e 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1693,6 +1693,294 @@ static const struct adreno_info a7xx_gpus[] = {
>  };
>  DECLARE_ADRENO_GPULIST(a7xx);
>
> +static const struct adreno_reglist_pipe a830_nonctxt_regs[] = {
> + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
> + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00400000, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + /* Configure GBIF GX registers */
> + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
> + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
> + /* Enable full concurrent resolve and unresolves */
> + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
> + /* Partially enable perf clear, Disable DINT to c/z be data forwarding */
> + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) },
> + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x0c000000, BIT(PIPE_BR) },
> + /* Configure number of outstanding transactions to 32 */
> + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
> + /* Configure UCHE request time out to 16 cycles for CCU/UCHE arbitration */
> + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
> + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
> + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
> + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
> + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
> + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
> + /* Enable contribution of all shader stages to SP perfcounters */
> + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
> + /*
> + * BIT(26): Limit the number of wave-slots for Eviction buffer to 1 per ALU GRP
> + * BIT(30): Disable LPAC auto-promotion
> + */
> + { REG_A7XX_SP_CHICKEN_BITS_1, BIT(26) | BIT(30), BIT(PIPE_NONE) },
> + /*
> + * BIT(22): Disable PS out of order retire
> + * BIT(23): Enable half wave mode and MM instruction src&dst is half precision
> + */
> + { REG_A7XX_SP_CHICKEN_BITS_2, BIT(22) | BIT(23), BIT(PIPE_NONE) },
> + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
> + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080,  BIT(PIPE_NONE) },
> + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
> + /* Enable cubemap small miplevel optimization settings */
> + /* BIT(26): Disable final clamp for bicubic filtering */
> + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000724, BIT(PIPE_NONE) },
> + /* Disable tag bank id hashing */
> + { REG_A6XX_UCHE_MODE_CNTL, 0x00080000, BIT(PIPE_NONE) },
> + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
> + /* Limit gmem number of ways for GMEM requests in each set */
> + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE)},
> + /* Disable write slow pointer in data phase queue */
> + { REG_A8XX_UCHE_HW_DBG_CNTL, BIT(8), BIT(PIPE_NONE) },
> + /* Configure UCHE to CCU switchthreshold timeout cycles */
> + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
> + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + /* Disable redundant tile data optimization */
> + { REG_A8XX_VSC_KMD_DBG_ECO_CNTL, BIT(11), BIT(PIPE_NONE)},
> + { },
> +};
> +
> +static const u32 a830_protect_regs[] = {
> + A6XX_PROTECT_RDONLY(0x00000, 0x03a3),
> + A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
> + A6XX_PROTECT_NORDWR(0x00440, 0x001f),
> + A6XX_PROTECT_RDONLY(0x00580, 0x005f),
> + A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
> + A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
> + A6XX_PROTECT_RDONLY(0x00759, 0x0026),
> + A6XX_PROTECT_RDONLY(0x00789, 0x0000),
> + A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
> + A6XX_PROTECT_NORDWR(0x00800, 0x0029),
> + A6XX_PROTECT_NORDWR(0x00837, 0x00af),
> + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
> + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
> + A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
> + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
> + A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
> + A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
> + A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
> + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
> + A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
> + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
> + A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
> + A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
> + A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
> + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
> + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
> + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
> + A6XX_PROTECT_NORDWR(0x0ae00, 0x0000),
> + A6XX_PROTECT_NORDWR(0x0ae02, 0x0004),
> + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
> + A6XX_PROTECT_NORDWR(0x0ae10, 0x036f),
> + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
> + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x18400, 0x003f),
> + A6XX_PROTECT_RDONLY(0x18440, 0x013f),
> + A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
> + A6XX_PROTECT_RDONLY(0x1f878, 0x0787),
> + A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
> + A6XX_PROTECT_NORDWR(0x20000, 0x1fff),
> + A6XX_PROTECT_NORDWR(0x27800, 0x007f),
> + A6XX_PROTECT_RDONLY(0x27880, 0x0381),
> + A6XX_PROTECT_NORDWR(0x27882, 0x0001),
> + A6XX_PROTECT_NORDWR(0x27c02, 0x0000),
> +};
> +DECLARE_ADRENO_PROTECT(a830_protect, 64);

I have tested this on an AYN Odin 3, which has a CQ8725S SoC with
A830. As-is, this change causes the device to fail to boot. Comparing
to a different implementation of this support that I used previously,
I found the operable difference is the count_max field here. Dropping
that from 64 to 15 allows the device to boot and work as intended. I
unfortunately don't have uart to see what the actual failure text is
and provide any more information than this.

Aaron

> +static const u32 a830_pwrup_reglist_regs[] = {
> + REG_A6XX_UCHE_MODE_CNTL,
> + REG_A8XX_UCHE_VARB_IDLE_TIMEOUT,
> + REG_A8XX_UCHE_GBIF_GX_CONFIG,
> + REG_A8XX_UCHE_CACHE_WAYS,
> + REG_A8XX_UCHE_CCHE_MODE_CNTL,
> + REG_A8XX_UCHE_CCHE_CACHE_WAYS,
> + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN,
> + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1,
> + REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN,
> + REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN + 1,
> + REG_A8XX_UCHE_CCHE_TRAP_BASE,
> + REG_A8XX_UCHE_CCHE_TRAP_BASE + 1,
> + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE,
> + REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1,
> + REG_A8XX_UCHE_HW_DBG_CNTL,
> + REG_A8XX_UCHE_WRITE_THRU_BASE,
> + REG_A8XX_UCHE_WRITE_THRU_BASE + 1,
> + REG_A8XX_UCHE_TRAP_BASE,
> + REG_A8XX_UCHE_TRAP_BASE + 1,
> + REG_A8XX_UCHE_CLIENT_PF,
> + REG_A8XX_VSC_KMD_DBG_ECO_CNTL,
> + REG_A8XX_RB_CMP_NC_MODE_CNTL,
> + REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP,
> + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN,
> + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1,
> + REG_A7XX_SP_READ_SEL,
> + REG_A6XX_TPL1_NC_MODE_CNTL,
> + REG_A6XX_TPL1_DBG_ECO_CNTL,
> + REG_A6XX_TPL1_DBG_ECO_CNTL1,
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18),
> + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19),
> +};
> +DECLARE_ADRENO_REGLIST_LIST(a830_pwrup_reglist);
> +
> +static const u32 a830_ifpc_reglist_regs[] = {
> + REG_A8XX_RBBM_NC_MODE_CNTL,
> + REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL,
> + REG_A8XX_RBBM_SLICE_NC_MODE_CNTL,
> + REG_A6XX_SP_NC_MODE_CNTL,
> + REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN,
> + REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN + 1,
> + REG_A7XX_SP_CHICKEN_BITS_1,
> + REG_A7XX_SP_CHICKEN_BITS_2,
> + REG_A7XX_SP_CHICKEN_BITS_3,
> + REG_A6XX_SP_PERFCTR_SHADER_MASK,
> + REG_A7XX_SP_HLSQ_DBG_ECO_CNTL,
> + REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL,
> + REG_A8XX_RBBM_PERFCTR_CNTL,
> + REG_A8XX_CP_PROTECT_GLOBAL(0),
> + REG_A8XX_CP_PROTECT_GLOBAL(1),
> + REG_A8XX_CP_PROTECT_GLOBAL(2),
> + REG_A8XX_CP_PROTECT_GLOBAL(3),
> + REG_A8XX_CP_PROTECT_GLOBAL(4),
> + REG_A8XX_CP_PROTECT_GLOBAL(5),
> + REG_A8XX_CP_PROTECT_GLOBAL(6),
> + REG_A8XX_CP_PROTECT_GLOBAL(7),
> + REG_A8XX_CP_PROTECT_GLOBAL(8),
> + REG_A8XX_CP_PROTECT_GLOBAL(9),
> + REG_A8XX_CP_PROTECT_GLOBAL(10),
> + REG_A8XX_CP_PROTECT_GLOBAL(11),
> + REG_A8XX_CP_PROTECT_GLOBAL(12),
> + REG_A8XX_CP_PROTECT_GLOBAL(13),
> + REG_A8XX_CP_PROTECT_GLOBAL(14),
> + REG_A8XX_CP_PROTECT_GLOBAL(15),
> + REG_A8XX_CP_PROTECT_GLOBAL(16),
> + REG_A8XX_CP_PROTECT_GLOBAL(17),
> + REG_A8XX_CP_PROTECT_GLOBAL(18),
> + REG_A8XX_CP_PROTECT_GLOBAL(19),
> + REG_A8XX_CP_PROTECT_GLOBAL(20),
> + REG_A8XX_CP_PROTECT_GLOBAL(21),
> + REG_A8XX_CP_PROTECT_GLOBAL(22),
> + REG_A8XX_CP_PROTECT_GLOBAL(23),
> + REG_A8XX_CP_PROTECT_GLOBAL(24),
> + REG_A8XX_CP_PROTECT_GLOBAL(25),
> + REG_A8XX_CP_PROTECT_GLOBAL(26),
> + REG_A8XX_CP_PROTECT_GLOBAL(27),
> + REG_A8XX_CP_PROTECT_GLOBAL(28),
> + REG_A8XX_CP_PROTECT_GLOBAL(29),
> + REG_A8XX_CP_PROTECT_GLOBAL(30),
> + REG_A8XX_CP_PROTECT_GLOBAL(31),
> + REG_A8XX_CP_PROTECT_GLOBAL(32),
> + REG_A8XX_CP_PROTECT_GLOBAL(33),
> + REG_A8XX_CP_PROTECT_GLOBAL(34),
> + REG_A8XX_CP_PROTECT_GLOBAL(35),
> + REG_A8XX_CP_PROTECT_GLOBAL(36),
> + REG_A8XX_CP_PROTECT_GLOBAL(37),
> + REG_A8XX_CP_PROTECT_GLOBAL(38),
> + REG_A8XX_CP_PROTECT_GLOBAL(39),
> + REG_A8XX_CP_PROTECT_GLOBAL(40),
> + REG_A8XX_CP_PROTECT_GLOBAL(41),
> + REG_A8XX_CP_PROTECT_GLOBAL(42),
> + REG_A8XX_CP_PROTECT_GLOBAL(43),
> + REG_A8XX_CP_PROTECT_GLOBAL(44),
> + REG_A8XX_CP_PROTECT_GLOBAL(45),
> + REG_A8XX_CP_PROTECT_GLOBAL(46),
> + REG_A8XX_CP_PROTECT_GLOBAL(47),
> + REG_A8XX_CP_PROTECT_GLOBAL(48),
> + REG_A8XX_CP_PROTECT_GLOBAL(49),
> + REG_A8XX_CP_PROTECT_GLOBAL(50),
> + REG_A8XX_CP_PROTECT_GLOBAL(51),
> + REG_A8XX_CP_PROTECT_GLOBAL(52),
> + REG_A8XX_CP_PROTECT_GLOBAL(53),
> + REG_A8XX_CP_PROTECT_GLOBAL(54),
> + REG_A8XX_CP_PROTECT_GLOBAL(55),
> + REG_A8XX_CP_PROTECT_GLOBAL(56),
> + REG_A8XX_CP_PROTECT_GLOBAL(57),
> + REG_A8XX_CP_PROTECT_GLOBAL(58),
> + REG_A8XX_CP_PROTECT_GLOBAL(59),
> + REG_A8XX_CP_PROTECT_GLOBAL(60),
> + REG_A8XX_CP_PROTECT_GLOBAL(61),
> + REG_A8XX_CP_PROTECT_GLOBAL(62),
> + REG_A8XX_CP_PROTECT_GLOBAL(63),
> +};
> +DECLARE_ADRENO_REGLIST_LIST(a830_ifpc_reglist);
> +
> +static const struct adreno_reglist_pipe a830_dyn_pwrup_reglist_regs[] = {
> + { REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) |
> + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) |
> + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) },
> + { REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) |
> + BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) |
> + BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) },
> + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) },
> + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) },
> + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) },
> + { REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR) },
> + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
> + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
> + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) },
> + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) },
> + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
> + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) },
> + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
> + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) },
> + { },
> +};
> +DECLARE_ADRENO_REGLIST_PIPE_LIST(a830_dyn_pwrup_reglist);
> +
>  static const struct adreno_reglist_pipe x285_nonctxt_regs[] = {
>   { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
>   { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
> @@ -2399,6 +2687,51 @@ DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist);
>
>  static const struct adreno_info a8xx_gpus[] = {
>   {
> + .chip_ids = ADRENO_CHIP_IDS(0x44050001),
> + .family = ADRENO_8XX_GEN1,
> + .fw = {
> + [ADRENO_FW_SQE] = "gen80000_sqe.fw",
> + [ADRENO_FW_GMU] = "gen80000_gmu.bin",
> + [ADRENO_FW_AQE] = "gen80000_aqe.fw",
> + },
> + .gmem = 12 * SZ_1M,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
> +  ADRENO_QUIRK_HAS_HW_APRIV |
> +  ADRENO_QUIRK_PREEMPTION |
> +  ADRENO_QUIRK_IFPC,
> + .funcs = &a8xx_gpu_funcs,
> + .a6xx = &(const struct a6xx_info) {
> + .protect = &a830_protect,
> + .nonctxt_reglist = a830_nonctxt_regs,
> + .pwrup_reglist = &a830_pwrup_reglist,
> + .dyn_pwrup_reglist = &a830_dyn_pwrup_reglist,
> + .ifpc_reglist = &a830_ifpc_reglist,
> + .gbif_cx = a840_gbif,
> + .max_slices = 3,
> + .gmu_chipid = 0x8000100,
> + .bcms = (const struct a6xx_bcm[]) {
> + { .name = "SH0", .buswidth = 16 },
> + { .name = "MC0", .buswidth = 4 },
> + {
> + .name = "ACV",
> + .fixed = true,
> + .perfmode = BIT(2),
> + .perfmode_bw = 10687500,
> + },
> + { /* sentinel */ },
> + },
> + },
> + .preempt_record_size = 13536 * SZ_1K,
> + .speedbins = ADRENO_SPEEDBINS(
> + { 0,   0 },
> + { 252, 0 },
> + { 242, 1 },
> + { 232, 2 },
> + { 221, 3 },
> + { 190, 4 },
> + ),
> + }, {
>   .chip_ids = ADRENO_CHIP_IDS(0x44070001),
>   .family = ADRENO_8XX_GEN2,
>   .fw = {
> @@ -2537,4 +2870,5 @@ static inline __always_unused void __build_asserts(void)
>   BUILD_BUG_ON(a690_protect.count > a690_protect.count_max);
>   BUILD_BUG_ON(a730_protect.count > a730_protect.count_max);
>   BUILD_BUG_ON(a810_protect.count > a810_protect.count_max);
> + BUILD_BUG_ON(a830_protect.count > a830_protect.count_max);
>  }
> diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> index add93c1fa039..62df0569c62b 100644
> --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
> @@ -200,7 +200,7 @@ static void a8xx_set_hwcg(struct msm_gpu *gpu, bool state)
>   struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
>   u32 val;
>
> - if (adreno_is_x285(adreno_gpu) && state)
> + if ((adreno_is_x285(adreno_gpu) || adreno_is_a830(adreno_gpu)) && state)
>   gpu_write(gpu, REG_A8XX_RBBM_CGC_0_PC, 0x00000702);
>
>   gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 114a40f79ef3..338e02271fcc 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -602,6 +602,11 @@ static inline int adreno_is_x285(struct adreno_gpu *gpu)
>   return gpu->info->chip_ids[0] == 0x44070001;
>  }
>
> +static inline int adreno_is_a830(struct adreno_gpu *gpu)
> +{
> + return gpu->info->chip_ids[0] == 0x44050001;
> +}
> +
>  static inline int adreno_is_a840(struct adreno_gpu *gpu)
>  {
>   return gpu->info->chip_ids[0] == 0x44050a01;
> --
> 2.54.0

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH 0/6] drm/msm: Support for Adreno 830 GPU
@ 2026-08-08 20:23 Akhil P Oommen
  2026-08-08 20:23 ` [PATCH 1/6] drm/msm/a8xx: Add support " Akhil P Oommen
  0 siblings, 1 reply; 5+ messages in thread
From: Akhil P Oommen @ 2026-08-08 20:23 UTC (permalink / raw)
  To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
	Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
	Simona Vetter, Maarten Lankhorst, Maxime Ripard,
	Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Bjorn Andersson
  Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, devicetree,
	Jie Zhang, Akhil P Oommen, Gaurav Kohli

This series add support for Adreno 830 GPU present in Snapdragon SM8750
chipset, which is almost 2 yr old now. Adreno 830 is the first GPU in
AdrenoeA8xx family [1]. So, architecturally A830 is very close to A840 GPU,
so we just need to add a catalog entry to describe the GPU along with the
necessary register lists. Both Mesa support and firmwares at
linux-firmware repo are already available. Mesa needs a correction to
the chipid value which will be fixed soon.

Patch [1] & [2] are for Rob Clark and the remaining devicetree patches
are for Bjorn to pick up.

[1] https://lore.kernel.org/lkml/20251118-kaana-gpu-support-v4-0-86eeb8e93fb6@oss.qualcomm.com/

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
Gaurav Kohli (1):
      arm64: dts: qcom: sm8750: Add GPU cooling

Jie Zhang (5):
      drm/msm/a8xx: Add support for Adreno 830 GPU
      dt-bindings: display/msm: Document Adreno 830 GPU/GMU
      arm64: dts: qcom: sm8750: Add GPU and GMU nodes
      arm64: dts: qcom: sm8750-mtp: Enable Adreno 830 GPU
      arm64: dts: qcom: sm8750-qrd: Enable Adreno 830 GPU

 .../devicetree/bindings/display/msm/gmu.yaml       |   4 +-
 .../devicetree/bindings/display/msm/gpu.yaml       |   2 +
 arch/arm64/boot/dts/qcom/sm8750-mtp.dts            |   8 +
 arch/arm64/boot/dts/qcom/sm8750-qrd.dts            |   8 +
 arch/arm64/boot/dts/qcom/sm8750.dtsi               | 335 +++++++++++++++++++--
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c          | 334 ++++++++++++++++++++
 drivers/gpu/drm/msm/adreno/a8xx_gpu.c              |   2 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h            |   5 +
 8 files changed, 672 insertions(+), 26 deletions(-)
---
base-commit: d56fa0b2bd2d9b2fddc10e8f5bdd42d56676935c
change-id: 20260428-pakala-gpu-1e99c9671687
prerequisite-message-id: <20260714-gpucc_dt_v6-v6-1-16bf5289572d@oss.qualcomm.com>
prerequisite-patch-id: c050130345665caf00f2390fb3da0adc62667eb4

Best regards,
-- 
Akhil P Oommen <akhilpo@oss.qualcomm.com>


^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-08-17 12:23 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-08-11  7:59 [PATCH 1/6] drm/msm/a8xx: Add support for Adreno 830 GPU Aaron Kling
2026-08-11 22:53 ` Akhil P Oommen
2026-08-11 23:48   ` Aaron Kling
  -- strict thread matches above, loose matches on Subject: below --
2026-08-08 20:23 [PATCH 0/6] drm/msm: Support " Akhil P Oommen
2026-08-08 20:23 ` [PATCH 1/6] drm/msm/a8xx: Add support " Akhil P Oommen
2026-08-17 12:23   ` Konrad Dybcio

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