From: "Jernej Škrabec" <jernej.skrabec@gmail.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Andre Przywara <andre.przywara@arm.com>,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
wens@csie.org, samuel@sholland.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: allwinner: h6: Add OrangePi 3 LTS DTS
Date: Tue, 29 Apr 2025 17:27:10 +0200 [thread overview]
Message-ID: <4975791.GXAFRqVoOG@jernej-laptop> (raw)
In-Reply-To: <4645060.LvFx2qVVIh@jernej-laptop>
Dne torek, 29. april 2025 ob 17:24:18 Srednjeevropski poletni čas je Jernej Škrabec napisal(a):
> Dne torek, 29. april 2025 ob 17:09:22 Srednjeevropski poletni čas je Andrew Lunn napisal(a):
> > On Tue, Apr 29, 2025 at 04:51:59PM +0200, Jernej Škrabec wrote:
> > > Dne ponedeljek, 28. april 2025 ob 14:37:48 Srednjeevropski poletni čas je Andrew Lunn napisal(a):
> > > > On Sat, Apr 26, 2025 at 08:00:49PM +0200, Jernej Škrabec wrote:
> > > > > Dne petek, 25. april 2025 ob 17:34:14 Srednjeevropski poletni čas je Andrew Lunn napisal(a):
> > > > > > > > +&emac {
> > > > > > > > + pinctrl-names = "default";
> > > > > > > > + pinctrl-0 = <&ext_rgmii_pins>;
> > > > > > > > + phy-mode = "rgmii-rxid";
> > > > > > >
> > > > > > > So relating to what Andrew said earlier today, should this read rgmii-id
> > > > > > > instead? Since the strap resistors just set some boot-up value, but we
> > > > > > > want the PHY driver to enable both RX and TX delay programmatically?
> > > > > >
> > > > > > Yes.
> > > > > >
> > > > > > There is a checkpatch.pl patch working its way through the system
> > > > > > which will add warning about any rgmii value other than rgmii-id. Such
> > > > > > values need a comment that the PCB has extra long clock
> > > > > > lines. Hopefully that will make people actually stop and think about
> > > > > > this, rather than just copy broken vendor code.
> > > > >
> > > > > I spent quite some time working on ethernet support for this board. Once
> > > > > I've found PHY datasheet, I confirmed that there is added delay. So this
> > > > > particular board needs "rgmii-rxid" mode.
> > > >
> > > > There have been numerous discussions about what these rgmii modes
> > > > mean, because DT developers frequently get them wrong.
> > > >
> > > > Does the PCB have an extra long clock line in the TX direction? That
> > > > is what rgmii-rxid means, the PCB is providing the TX delay, the
> > > > MAC/PHY pair needs to add the RX delay.
> > >
> > > While schematic is accessible, AFAIK PCB/gerbers are not, so I can't really
> > > tell how long it is. But without this extra delay, ethernet doesn't work.
> >
> > You are not adding an extra delay, you are subtracting a
> > delay. 'rgmii-rxid' says the TX delay is implemented by the PCB, hence
> > the PHY does not need to add the delay.
> >
> > What is normal is that the PCB adds no delays, and the PHY adds the
> > delay for both the RX and the TX. And you represent this with
> > 'rgmii-id'.
>
> ok, thanks for explanation.
>
> >
> > So what you need to find out is, where does the TX delay come from?
>
> How to do that? Strapping show me this way and testing confirmed it. Not
> sure what more I can do? As a hobbyist, I don't have access to anything more
> than schematic.
I just to be clear, I tested various combinations, including rgmii-id, and it
didn't work, except rgmii-rxid, which matches strapping. Of course Motorcomm
PHY driver took that into account and set registers accordingly.
Best regards,
Jernej
next prev parent reply other threads:[~2025-04-29 15:27 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-13 13:42 [PATCH 0/2] arm64: dts: allwinner: Support Orange Pi 3 LTS board Jernej Skrabec
2025-04-13 13:42 ` [PATCH 1/2] dt-bindings: arm: sunxi: Add " Jernej Skrabec
2025-04-15 21:56 ` Rob Herring (Arm)
2025-04-13 13:42 ` [PATCH 2/2] arm64: dts: allwinner: h6: Add OrangePi 3 LTS DTS Jernej Skrabec
2025-04-25 0:57 ` Andre Przywara
2025-04-25 12:54 ` Andre Przywara
2025-04-25 14:37 ` Chen-Yu Tsai
2025-04-25 15:34 ` Andrew Lunn
2025-04-26 18:00 ` Jernej Škrabec
2025-04-28 12:37 ` Andrew Lunn
2025-04-29 14:51 ` Jernej Škrabec
2025-04-29 15:09 ` Andrew Lunn
2025-04-29 15:24 ` Jernej Škrabec
2025-04-29 15:27 ` Jernej Škrabec [this message]
2025-04-29 15:45 ` Andrew Lunn
2025-04-29 15:52 ` Chen-Yu Tsai
2025-04-29 16:56 ` Andrew Lunn
2025-04-26 18:26 ` Jernej Škrabec
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