Re: [PATCH v5 02/11] drm/mediatek: Implement Display Stream Compression support

[AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>]

On 7/15/26 14:02, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 7 potential issue(s) to consider:
> - [High] Hardware Initialization Bypass due to skipped array element in DDP component loop.
> - [High] DSC configuration is written after the component is started, causing pipeline corruption.
> - [High] State leak of `dsc_config_done` breaks non-DSC display modes.
> - [High] DSI clock lane timing register `DSI_HSTX_CKL_WC` is destroyed by being overwritten with the pixel payload word count.
> - [High] Hardcoded 2x multiplier for DSC slice count results in incorrect DSI payload word count.
> - [High] Bandwidth calculations use uncompressed bits-per-pixel (bpp), falsely rejecting valid DSC modes and misconfiguring PHY clocks.
> - [Medium] Uninitialized variable `slice_chunk_size` is used for hardware configuration during DSI power-on.
> --
The same replies that I gave to Sashiko in v4 also apply to v5.

In short: Sashiko doesn't understand how the hardware works, so it throws random
issues.