Re: [PATCH v5 15/17] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection

[Guodong Xu <guodong.xu@oss.qualcomm.com>]

On Wed, 01 Jul 2026 14:22:29 +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] The RVA23U64 base detection wrongly mandates the legacy broad `B` extension superset instead of its required bitmanip constituent extensions (`Zba`, `Zbb`, `Zbs`).
> --
>
> commit e73d8757f0ce7270b4b39989368d4e83e5a355fc
> Author: Guodong Xu <docular.xu@gmail.com>
>
> riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection
>
> This commit introduces a per-hart and host-wide bitmap of conformant ISA
> profile bases, such as IMA and RVA23U64. The bitmap is computed during
> init by riscv_init_isa_bases() and registered as a subsys_initcall.
>
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 4c3bf813af052..fa8471aef42ee 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
>
> [ ... ]
>
> > @@ -1304,3 +1307,90 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
> >  	}
> >  }
> >  #endif
>
> [ ... ]
>
> > +	/* RVA23U64 */
> > +
> > +	/* Supm with PMLEN=7 */
> > +	if (!riscv_have_user_pmlen(7))
> > +		return;
> > +
> > +	__set_bit(RISCV_ISA_EXT_F, ext_mask);
> > +	__set_bit(RISCV_ISA_EXT_D, ext_mask);
> > +	__set_bit(RISCV_ISA_EXT_C, ext_mask);
> > +	__set_bit(RISCV_ISA_EXT_B, ext_mask);
>
> [Severity: Medium]
> Does this incorrectly mandate the legacy broad B extension for RVA23U64?
>
> If a RISC-V device tree advertises the RVA23U64 constituent bitmanip
> extensions (e.g., zba, zbb, zbs) but omits the legacy unratified 'b'
> string, it appears this check will fail because RISCV_ISA_EXT_B won't be
> synthesized. Should this instead check for the individual constituent
> extensions required by the profile?

No. This was raised and answered in the v2 and v3 rounds.

Guodong