[PATCH] arm64: dts: socfpga: agilex5: enable i3c0 and i3c1

[PATCH] arm64: dts: socfpga: agilex5: enable i3c0 and i3c1

[Adrian Ng Ho Yin]

Enable i3c0 and i3c1 for Agilex5 devkit.

Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 262bb3e8e5c7..7f6fab506867 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -61,6 +61,14 @@ &gpio1 {
 	status = "okay";
 };
 
+&i3c0 {
+	status = "okay";
+};
+
+&i3c1 {
+	status = "okay";
+};
+
 &osc1 {
 	clock-frequency = <25000000>;
 };
-- 
2.49.GIT

Re: [PATCH] arm64: dts: socfpga: agilex5: enable i3c0 and i3c1

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The i3c0 and i3c1 nodes are enabled but lack the required `resets` and `reset-names` properties, structurally exposing the system to initialization failures or kernel panics.
--

commit f5368d005c11d976c73173b7cd6fde413ccc26cb
Author: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>

arm64: dts: socfpga: agilex5: enable i3c0 and i3c1

This commit enables the i3c0 and i3c1 nodes for the Agilex5 development kit
by setting their status to okay.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> index 262bb3e8e5c72..7f6fab5068676 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
[ ... ]
> @@ -61,6 +61,14 @@ &gpio1 {
>  	status = "okay";
>  };
>  
> +&i3c0 {
> +	status = "okay";
> +};
> +
> +&i3c1 {
> +	status = "okay";
> +};

[Severity: High]
This is a pre-existing issue, but the i3c0 and i3c1 nodes defined in the
base socfpga_agilex5.dtsi file lack the resets and reset-names properties.

By enabling the nodes here, does this expose the system to initialization
failures or a bus hang during probe?

The Synopsys DesignWare I3C driver requests an optional reset control named
core_rst via devm_reset_control_get_optional_exclusive_deasserted(). If the
bootloader leaves these peripherals in reset, the driver will receive NULL
for the reset control and proceed without deasserting the reset line, which
can cause an AXI bus hang when accessing registers.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/219d67474c90843f4768cba2598e79cfafcc1ac2.1779778817.git.adrian.ho.yin.ng@altera.com?part=1

Re: [PATCH] arm64: dts: socfpga: agilex5: enable i3c0 and i3c1

[Dinh Nguyen]

On 5/26/26 02:03, Adrian Ng Ho Yin wrote:
> Enable i3c0 and i3c1 for Agilex5 devkit.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> ---
>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> index 262bb3e8e5c7..7f6fab506867 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
> @@ -61,6 +61,14 @@ &gpio1 {
>   	status = "okay";
>   };
>   
> +&i3c0 {
> +	status = "okay";
> +};
> +
> +&i3c1 {
> +	status = "okay";
> +};
> +
>   &osc1 {
>   	clock-frequency = <25000000>;
>   };

https://sashiko.dev/#/patchset/219d67474c90843f4768cba2598e79cfafcc1ac2.1779778817.git.adrian.ho.yin.ng%40altera.com