* [PATCH 8/8] ARM: dts: msm: Use Operation Points V2 for UFS on SM8650
[not found] <20250116091150.1167739-1-quic_ziqichen@quicinc.com>
@ 2025-01-16 9:11 ` Ziqi Chen
2025-01-16 9:22 ` Krzysztof Kozlowski
2025-01-16 9:24 ` neil.armstrong
0 siblings, 2 replies; 5+ messages in thread
From: Ziqi Chen @ 2025-01-16 9:11 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, beanhuo, avri.altman, junwoo80.lee,
martin.petersen, quic_ziqichen, quic_nguyenb, quic_nitirawa,
quic_rampraka
Cc: linux-scsi, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, open list:ARM/QUALCOMM SUPPORT,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Use Operation Points V2 for UFS on SM8650 so that multi-level
clock/gear scaling can be possible.
Co-developed-by: Can Guo <quic_cang@quicinc.com>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
Signed-off-by: Ziqi Chen <quic_ziqichen@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 51 +++++++++++++++++++++++-----
1 file changed, 43 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 01ac3769ffa6..5466f1217f64 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2557,18 +2557,11 @@ ufs_mem_hc: ufs@1d84000 {
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
- freq-table-hz = <100000000 403000000>,
- <0 0>,
- <0 0>,
- <100000000 403000000>,
- <100000000 403000000>,
- <0 0>,
- <0 0>,
- <0 0>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
+ operating-points-v2 = <&ufs_opp_table>;
interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
@@ -2590,6 +2583,48 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
#reset-cells = <1>;
status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ // LOW_SVS
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <100000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ // SVS
+ opp-201500000 {
+ opp-hz = /bits/ 64 <201500000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <201500000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ // NOM/TURBO
+ opp-403000000 {
+ opp-hz = /bits/ 64 <403000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <403000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
ice: crypto@1d88000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 8/8] ARM: dts: msm: Use Operation Points V2 for UFS on SM8650
2025-01-16 9:11 ` [PATCH 8/8] ARM: dts: msm: Use Operation Points V2 for UFS on SM8650 Ziqi Chen
@ 2025-01-16 9:22 ` Krzysztof Kozlowski
2025-01-20 12:12 ` Ziqi Chen
2025-01-16 9:24 ` neil.armstrong
1 sibling, 1 reply; 5+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-16 9:22 UTC (permalink / raw)
To: Ziqi Chen, quic_cang, bvanassche, mani, beanhuo, avri.altman,
junwoo80.lee, martin.petersen, quic_nguyenb, quic_nitirawa,
quic_rampraka
Cc: linux-scsi, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, open list:ARM/QUALCOMM SUPPORT,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
On 16/01/2025 10:11, Ziqi Chen wrote:
> Use Operation Points V2 for UFS on SM8650 so that multi-level
> clock/gear scaling can be possible.
>
> Co-developed-by: Can Guo <quic_cang@quicinc.com>
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> Signed-off-by: Ziqi Chen <quic_ziqichen@quicinc.com>
Please don't send downstream code directly, but fix it first. Actually -
rework it 100%.
Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 51 +++++++++++++++++++++++-----
> 1 file changed, 43 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 01ac3769ffa6..5466f1217f64 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -2557,18 +2557,11 @@ ufs_mem_hc: ufs@1d84000 {
> "tx_lane0_sync_clk",
> "rx_lane0_sync_clk",
> "rx_lane1_sync_clk";
> - freq-table-hz = <100000000 403000000>,
> - <0 0>,
> - <0 0>,
> - <100000000 403000000>,
> - <100000000 403000000>,
> - <0 0>,
> - <0 0>,
> - <0 0>;
>
> resets = <&gcc GCC_UFS_PHY_BCR>;
> reset-names = "rst";
>
> + operating-points-v2 = <&ufs_opp_table>;
> interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> @@ -2590,6 +2583,48 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> #reset-cells = <1>;
>
> status = "disabled";
> +
> + ufs_opp_table: opp-table {
> + compatible = "operating-points-v2";
Messed indentation.
> + // LOW_SVS
Drop
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>,
> + /bits/ 64 <0>,
Messed alignment.
> + /bits/ 64 <0>,
> + /bits/ 64 <100000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 8/8] ARM: dts: msm: Use Operation Points V2 for UFS on SM8650
2025-01-16 9:11 ` [PATCH 8/8] ARM: dts: msm: Use Operation Points V2 for UFS on SM8650 Ziqi Chen
2025-01-16 9:22 ` Krzysztof Kozlowski
@ 2025-01-16 9:24 ` neil.armstrong
2025-01-20 12:13 ` Ziqi Chen
1 sibling, 1 reply; 5+ messages in thread
From: neil.armstrong @ 2025-01-16 9:24 UTC (permalink / raw)
To: Ziqi Chen, quic_cang, bvanassche, mani, beanhuo, avri.altman,
junwoo80.lee, martin.petersen, quic_nguyenb, quic_nitirawa,
quic_rampraka
Cc: linux-scsi, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, open list:ARM/QUALCOMM SUPPORT,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Hi,
On 16/01/2025 10:11, Ziqi Chen wrote:
> Use Operation Points V2 for UFS on SM8650 so that multi-level
> clock/gear scaling can be possible.
I've already sent a similar one at https://lore.kernel.org/all/20250115-topic-sm8x50-upstream-dt-icc-update-v1-10-eaa8b10e2af7@linaro.org/
Neil
>
> Co-developed-by: Can Guo <quic_cang@quicinc.com>
> Signed-off-by: Can Guo <quic_cang@quicinc.com>
> Signed-off-by: Ziqi Chen <quic_ziqichen@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 51 +++++++++++++++++++++++-----
> 1 file changed, 43 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> index 01ac3769ffa6..5466f1217f64 100644
> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
> @@ -2557,18 +2557,11 @@ ufs_mem_hc: ufs@1d84000 {
> "tx_lane0_sync_clk",
> "rx_lane0_sync_clk",
> "rx_lane1_sync_clk";
> - freq-table-hz = <100000000 403000000>,
> - <0 0>,
> - <0 0>,
> - <100000000 403000000>,
> - <100000000 403000000>,
> - <0 0>,
> - <0 0>,
> - <0 0>;
>
> resets = <&gcc GCC_UFS_PHY_BCR>;
> reset-names = "rst";
>
> + operating-points-v2 = <&ufs_opp_table>;
> interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
> &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
> @@ -2590,6 +2583,48 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> #reset-cells = <1>;
>
> status = "disabled";
> +
> + ufs_opp_table: opp-table {
> + compatible = "operating-points-v2";
> + // LOW_SVS
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <100000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + // SVS
> + opp-201500000 {
> + opp-hz = /bits/ 64 <201500000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <201500000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + // NOM/TURBO
> + opp-403000000 {
> + opp-hz = /bits/ 64 <403000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <403000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> };
>
> ice: crypto@1d88000 {
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 8/8] ARM: dts: msm: Use Operation Points V2 for UFS on SM8650
2025-01-16 9:22 ` Krzysztof Kozlowski
@ 2025-01-20 12:12 ` Ziqi Chen
0 siblings, 0 replies; 5+ messages in thread
From: Ziqi Chen @ 2025-01-20 12:12 UTC (permalink / raw)
To: Krzysztof Kozlowski, quic_cang, bvanassche, mani, beanhuo,
avri.altman, junwoo80.lee, martin.petersen, quic_nguyenb,
quic_nitirawa, quic_rampraka
Cc: linux-scsi, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, open list:ARM/QUALCOMM SUPPORT,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
Hi Krzysztof,
Thanks for review and comments~
As Neil has submitted a similar patch:
https://lore.kernel.org/all/20250115-topic-sm8x50-upstream-dt-icc-update-v1-10-eaa8b10e2af7@linaro.org/
I will withdraw this patch in next version.
-Ziqi
On 1/16/2025 5:22 PM, Krzysztof Kozlowski wrote:
> On 16/01/2025 10:11, Ziqi Chen wrote:
>> Use Operation Points V2 for UFS on SM8650 so that multi-level
>> clock/gear scaling can be possible.
>>
>> Co-developed-by: Can Guo <quic_cang@quicinc.com>
>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>> Signed-off-by: Ziqi Chen <quic_ziqichen@quicinc.com>
>
> Please don't send downstream code directly, but fix it first. Actually -
> rework it 100%.
>
> Please use subject prefixes matching the subsystem. You can get them for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching. For bindings, the preferred subjects are
> explained here:
> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
> >> ---
>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 51 +++++++++++++++++++++++-----
>> 1 file changed, 43 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> index 01ac3769ffa6..5466f1217f64 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> @@ -2557,18 +2557,11 @@ ufs_mem_hc: ufs@1d84000 {
>> "tx_lane0_sync_clk",
>> "rx_lane0_sync_clk",
>> "rx_lane1_sync_clk";
>> - freq-table-hz = <100000000 403000000>,
>> - <0 0>,
>> - <0 0>,
>> - <100000000 403000000>,
>> - <100000000 403000000>,
>> - <0 0>,
>> - <0 0>,
>> - <0 0>;
>>
>> resets = <&gcc GCC_UFS_PHY_BCR>;
>> reset-names = "rst";
>>
>> + operating-points-v2 = <&ufs_opp_table>;
>> interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>> &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>> @@ -2590,6 +2583,48 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> #reset-cells = <1>;
>>
>> status = "disabled";
>> +
>> + ufs_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>
>
> Messed indentation.
>
>> + // LOW_SVS
>
>
> Drop
>
>> + opp-100000000 {
>> + opp-hz = /bits/ 64 <100000000>,
>> + /bits/ 64 <0>,
>
> Messed alignment.
>
>> + /bits/ 64 <0>,
>> + /bits/ 64 <100000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>
>
>
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 8/8] ARM: dts: msm: Use Operation Points V2 for UFS on SM8650
2025-01-16 9:24 ` neil.armstrong
@ 2025-01-20 12:13 ` Ziqi Chen
0 siblings, 0 replies; 5+ messages in thread
From: Ziqi Chen @ 2025-01-20 12:13 UTC (permalink / raw)
To: neil.armstrong, quic_cang, bvanassche, mani, beanhuo, avri.altman,
junwoo80.lee, martin.petersen, quic_nguyenb, quic_nitirawa,
quic_rampraka
Cc: linux-scsi, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, open list:ARM/QUALCOMM SUPPORT,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
On 1/16/2025 5:24 PM, neil.armstrong@linaro.org wrote:
> Hi,
>
> On 16/01/2025 10:11, Ziqi Chen wrote:
>> Use Operation Points V2 for UFS on SM8650 so that multi-level
>> clock/gear scaling can be possible.
>
>
> I've already sent a similar one at
> https://lore.kernel.org/all/20250115-topic-sm8x50-upstream-dt-icc-update-v1-10-eaa8b10e2af7@linaro.org/
>
> Neil
>
Hi Neil,
Thank you for reminder , I will withdraw this patch in next version.
- Ziqi
>>
>> Co-developed-by: Can Guo <quic_cang@quicinc.com>
>> Signed-off-by: Can Guo <quic_cang@quicinc.com>
>> Signed-off-by: Ziqi Chen <quic_ziqichen@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 51 +++++++++++++++++++++++-----
>> 1 file changed, 43 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> index 01ac3769ffa6..5466f1217f64 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> @@ -2557,18 +2557,11 @@ ufs_mem_hc: ufs@1d84000 {
>> "tx_lane0_sync_clk",
>> "rx_lane0_sync_clk",
>> "rx_lane1_sync_clk";
>> - freq-table-hz = <100000000 403000000>,
>> - <0 0>,
>> - <0 0>,
>> - <100000000 403000000>,
>> - <100000000 403000000>,
>> - <0 0>,
>> - <0 0>,
>> - <0 0>;
>> resets = <&gcc GCC_UFS_PHY_BCR>;
>> reset-names = "rst";
>> + operating-points-v2 = <&ufs_opp_table>;
>> interconnects = <&aggre1_noc MASTER_UFS_MEM
>> QCOM_ICC_TAG_ALWAYS
>> &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>> @@ -2590,6 +2583,48 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> #reset-cells = <1>;
>> status = "disabled";
>> +
>> + ufs_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> + // LOW_SVS
>> + opp-100000000 {
>> + opp-hz = /bits/ 64 <100000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <100000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + // SVS
>> + opp-201500000 {
>> + opp-hz = /bits/ 64 <201500000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <201500000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>;
>> + required-opps = <&rpmhpd_opp_svs>;
>> + };
>> +
>> + // NOM/TURBO
>> + opp-403000000 {
>> + opp-hz = /bits/ 64 <403000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <403000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + };
>> + };
>> };
>> ice: crypto@1d88000 {
>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2025-01-16 9:11 ` [PATCH 8/8] ARM: dts: msm: Use Operation Points V2 for UFS on SM8650 Ziqi Chen
2025-01-16 9:22 ` Krzysztof Kozlowski
2025-01-20 12:12 ` Ziqi Chen
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2025-01-20 12:13 ` Ziqi Chen
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