* [PATCH v6 0/4] serial: 8250_dw: Add support for UltraRISC DP1000 UART
@ 2026-04-29 9:05 Jia Wang
2026-04-29 9:05 ` [PATCH v6 1/4] serial: 8250_dwlib: move DesignWare register definitions to header Jia Wang
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Jia Wang @ 2026-04-29 9:05 UTC (permalink / raw)
To: Ilpo Järvinen, Andy Shevchenko, Greg Kroah-Hartman,
Jiri Slaby, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel, linux-serial, linux-riscv, devicetree, Jia Wang,
Conor Dooley
This patch series adds support for the UltraRISC DP1000 UART controller.
The series includes four patches. The first two are preparatory cleanups;
the last two add the DP1000 compatible and fixed CPR handling.
The patches have been tested on an UltraRISC DP1000 development board with
Linux v7.1-rc1, verifying basic UART functionality.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
Changes in v6:
- Patch 2:
* Simplify the FIFO size -> CPR FIFO_MODE helper.
- Patch 4:
* Use the updated FIFO helper.
- Link to v5: https://patch.msgid.link/20260428-ultrarisc-serial-v5-0-97de63b1e3eb@ultrarisc.com
Changes in v5:
- Rebased onto Linux v7.1-rc1.
- Patch 1:
* Reorder and document the moved DesignWare register/bit definitions.
- Patch 2:
* Add a FIFO size -> CPR FIFO_MODE helper and use it for RZ/N1.
- Patch 4:
* Use the FIFO_MODE helper for DP1000.
- Link to v4: https://patch.msgid.link/20260424-ultrarisc-serial-v4-0-1765a0b4c4a0@ultrarisc.com
Changes in v4:
- Added two preparatory patches before the original series, shifting patch
numbers (former 1/2 -> now 3/4).
- Patch 1:
* Move all DesignWare UART register/field definitions into 8250_dwlib.h
for shared use with 8250_dw.
- Patch 2:
* Converted the Renesas RZ/N1 CPR magic value to use DW_UART_CPR_* macros
and FIELD_PREP_CONST().
- Patch 4:
* Converted the UltraRISC DP1000 CPR magic value to use
DW_UART_CPR_* macros and FIELD_PREP_CONST() (value unchanged).
- Link to v3: https://patch.msgid.link/20260421-ultrarisc-serial-v3-0-3d7f09c2420e@ultrarisc.com
Changes in v3:
- Rebased on Linux v7.0-rc7.
- Patch 1:
* Removed separate `items` entry for DP1000, merging it into the
existing `enum` to comply with the schema.
* Updated commit message to describe DP1000 UART hardware differences.
- Patch 2:
* Drop the custom quirk for missing CPR register.
* Switch to using DW_UART_QUIRK_CPR_VALUE to provide a fixed CPR value.
- Link to v2: https://patch.msgid.link/20260316-ultrarisc-serial-v2-0-6ab3e7fa891c@ultrarisc.com
Changes in v2:
- Rebased on Linux v7.0-rc4 (previously on v7.0-rc2).
- Reordered patch series: DT binding patch comes before driver changes.
- Updated commit message for DT binding patch.
- Link to v1: https://patch.msgid.link/20260316-ultrarisc-serial-v1-0-c464f3e933a5@ultrarisc.com
---
Jia Wang (4):
serial: 8250_dwlib: move DesignWare register definitions to header
serial: 8250_dw: build Renesas RZN1 CPR value from DW_UART_CPR_* definitions
dt-bindings: serial: snps-dw-apb-uart: Add UltraRISC DP1000 UART
serial: 8250_dw: Use a fixed CPR value for UltraRISC DP1000 UART
.../bindings/serial/snps-dw-apb-uart.yaml | 1 +
drivers/tty/serial/8250/8250_dw.c | 31 +++++----
drivers/tty/serial/8250/8250_dwlib.c | 49 ---------------
drivers/tty/serial/8250/8250_dwlib.h | 73 ++++++++++++++++++++++
4 files changed, 93 insertions(+), 61 deletions(-)
---
base-commit: 3b3bea6d4b9c162f9e555905d96b8c1da67ecd5b
change-id: 20260309-ultrarisc-serial-64ff637edf26
Best regards,
--
Jia Wang <wangjia@ultrarisc.com>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v6 1/4] serial: 8250_dwlib: move DesignWare register definitions to header
2026-04-29 9:05 [PATCH v6 0/4] serial: 8250_dw: Add support for UltraRISC DP1000 UART Jia Wang
@ 2026-04-29 9:05 ` Jia Wang
2026-04-29 10:38 ` Ilpo Järvinen
2026-04-29 9:05 ` [PATCH v6 2/4] serial: 8250_dw: build Renesas RZN1 CPR value from DW_UART_CPR_* definitions Jia Wang
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Jia Wang @ 2026-04-29 9:05 UTC (permalink / raw)
To: Ilpo Järvinen, Andy Shevchenko, Greg Kroah-Hartman,
Jiri Slaby, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel, linux-serial, linux-riscv, devicetree, Jia Wang
Move the DW_UART_* register offsets and CPR bit/field definitions from
8250_dwlib.c into 8250_dwlib.h so they can be shared by 8250_dw and
8250_dwlib users.
Add an include guard for 8250_dwlib.h.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/tty/serial/8250/8250_dw.c | 11 ------
drivers/tty/serial/8250/8250_dwlib.c | 49 --------------------------
drivers/tty/serial/8250/8250_dwlib.h | 67 ++++++++++++++++++++++++++++++++++++
3 files changed, 67 insertions(+), 60 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 94beadb4024d..467755bf0092 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -34,22 +34,11 @@
#include "8250_dwlib.h"
-/* Offsets for the DesignWare specific registers */
-#define DW_UART_USR 0x1f /* UART Status Register */
-#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
-
#define OCTEON_UART_USR 0x27 /* UART Status Register */
#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
-/* DesignWare specific register fields */
-#define DW_UART_IIR_IID GENMASK(3, 0)
-
-#define DW_UART_MCR_SIRE BIT(6)
-
-#define DW_UART_USR_BUSY BIT(0)
-
/* Renesas specific register fields */
#define RZN1_UART_xDMACR_DMA_EN BIT(0)
#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c
index b055d89cfb39..8859e66d2d71 100644
--- a/drivers/tty/serial/8250/8250_dwlib.c
+++ b/drivers/tty/serial/8250/8250_dwlib.c
@@ -13,55 +13,6 @@
#include "8250_dwlib.h"
-/* Offsets for the DesignWare specific registers */
-#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
-#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
-#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
-#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
-#define DW_UART_RAR 0xc4 /* Receive Address Register */
-#define DW_UART_TAR 0xc8 /* Transmit Address Register */
-#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */
-#define DW_UART_CPR 0xf4 /* Component Parameter Register */
-#define DW_UART_UCV 0xf8 /* UART Component Version */
-
-/* Receive / Transmit Address Register bits */
-#define DW_UART_ADDR_MASK GENMASK(7, 0)
-
-/* Line Status Register bits */
-#define DW_UART_LSR_ADDR_RCVD BIT(8)
-
-/* Transceiver Control Register bits */
-#define DW_UART_TCR_RS485_EN BIT(0)
-#define DW_UART_TCR_RE_POL BIT(1)
-#define DW_UART_TCR_DE_POL BIT(2)
-#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
-#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
-#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
-#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
-
-/* Line Extended Control Register bits */
-#define DW_UART_LCR_EXT_DLS_E BIT(0)
-#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1)
-#define DW_UART_LCR_EXT_SEND_ADDR BIT(2)
-#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3)
-
-/* Component Parameter Register bits */
-#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0)
-#define DW_UART_CPR_AFCE_MODE BIT(4)
-#define DW_UART_CPR_THRE_MODE BIT(5)
-#define DW_UART_CPR_SIR_MODE BIT(6)
-#define DW_UART_CPR_SIR_LP_MODE BIT(7)
-#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8)
-#define DW_UART_CPR_FIFO_ACCESS BIT(9)
-#define DW_UART_CPR_FIFO_STAT BIT(10)
-#define DW_UART_CPR_SHADOW BIT(11)
-#define DW_UART_CPR_ENCODED_PARMS BIT(12)
-#define DW_UART_CPR_DMA_EXTRA BIT(13)
-#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)
-
-/* Helper for FIFO size calculation */
-#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
-
/*
* divisor = div(I) + div(F)
* "I" means integer, "F" means fractional
diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
index 7dd2a8e7b780..2f26f9ecacbe 100644
--- a/drivers/tty/serial/8250/8250_dwlib.h
+++ b/drivers/tty/serial/8250/8250_dwlib.h
@@ -1,11 +1,76 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* Synopsys DesignWare 8250 library header file. */
+#ifndef _SERIAL_8250_DWLIB_H_
+#define _SERIAL_8250_DWLIB_H_
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
#include <linux/io.h>
#include <linux/types.h>
#include "8250.h"
+/* Offsets for the DesignWare specific registers */
+#define DW_UART_USR 0x1f /* UART Status Register */
+#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
+#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
+#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
+#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
+#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
+#define DW_UART_RAR 0xc4 /* Receive Address Register */
+#define DW_UART_TAR 0xc8 /* Transmit Address Register */
+#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */
+#define DW_UART_CPR 0xf4 /* Component Parameter Register */
+#define DW_UART_UCV 0xf8 /* UART Component Version */
+
+/* Interrupt ID Register bits */
+#define DW_UART_IIR_IID GENMASK(3, 0)
+
+/* Modem Control Register bits */
+#define DW_UART_MCR_SIRE BIT(6)
+
+/* Line Status Register bits */
+#define DW_UART_LSR_ADDR_RCVD BIT(8)
+
+/* UART Status Register bits */
+#define DW_UART_USR_BUSY BIT(0)
+
+/* Transceiver Control Register bits */
+#define DW_UART_TCR_RS485_EN BIT(0)
+#define DW_UART_TCR_RE_POL BIT(1)
+#define DW_UART_TCR_DE_POL BIT(2)
+#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
+#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
+#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
+#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
+
+/* Receive / Transmit Address Register bits */
+#define DW_UART_ADDR_MASK GENMASK(7, 0)
+
+/* Line Extended Control Register bits */
+#define DW_UART_LCR_EXT_DLS_E BIT(0)
+#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1)
+#define DW_UART_LCR_EXT_SEND_ADDR BIT(2)
+#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3)
+
+/* Component Parameter Register bits */
+#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0)
+#define DW_UART_CPR_AFCE_MODE BIT(4)
+#define DW_UART_CPR_THRE_MODE BIT(5)
+#define DW_UART_CPR_SIR_MODE BIT(6)
+#define DW_UART_CPR_SIR_LP_MODE BIT(7)
+#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8)
+#define DW_UART_CPR_FIFO_ACCESS BIT(9)
+#define DW_UART_CPR_FIFO_STAT BIT(10)
+#define DW_UART_CPR_SHADOW BIT(11)
+#define DW_UART_CPR_ENCODED_PARMS BIT(12)
+#define DW_UART_CPR_DMA_EXTRA BIT(13)
+#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)
+
+/* Helper for FIFO size calculation */
+#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
+
struct dw8250_port_data {
/* Port properties */
int line;
@@ -38,3 +103,5 @@ static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
else
writel(reg, p->membase + offset);
}
+
+#endif /* _SERIAL_8250_DWLIB_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v6 2/4] serial: 8250_dw: build Renesas RZN1 CPR value from DW_UART_CPR_* definitions
2026-04-29 9:05 [PATCH v6 0/4] serial: 8250_dw: Add support for UltraRISC DP1000 UART Jia Wang
2026-04-29 9:05 ` [PATCH v6 1/4] serial: 8250_dwlib: move DesignWare register definitions to header Jia Wang
@ 2026-04-29 9:05 ` Jia Wang
2026-04-29 9:05 ` [PATCH v6 3/4] dt-bindings: serial: snps-dw-apb-uart: Add UltraRISC DP1000 UART Jia Wang
2026-04-29 9:05 ` [PATCH v6 4/4] serial: 8250_dw: Use a fixed CPR value for " Jia Wang
3 siblings, 0 replies; 8+ messages in thread
From: Jia Wang @ 2026-04-29 9:05 UTC (permalink / raw)
To: Ilpo Järvinen, Andy Shevchenko, Greg Kroah-Hartman,
Jiri Slaby, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel, linux-serial, linux-riscv, devicetree, Jia Wang
Replace the magic CPR value for Renesas RZ/N1 with a composition using
DW_UART_CPR_* bit/field definitions and FIELD_PREP_CONST().
Introduce a helper macro to convert a FIFO size (bytes) into the CPR
FIFO_MODE field value, with BUILD_BUG_ON_ZERO() checks for alignment and
bounds. Use it to replace the literal FIFO_MODE values in the RZN1.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/tty/serial/8250/8250_dw.c | 10 +++++++++-
drivers/tty/serial/8250/8250_dwlib.h | 8 +++++++-
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 467755bf0092..480f82d89856 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -937,7 +937,15 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = {
static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
.usr_reg = DW_UART_USR,
- .cpr_value = 0x00012f32,
+ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) |
+ DW_UART_CPR_AFCE_MODE |
+ DW_UART_CPR_THRE_MODE |
+ DW_UART_CPR_ADDITIONAL_FEATURES |
+ DW_UART_CPR_FIFO_ACCESS |
+ DW_UART_CPR_FIFO_STAT |
+ DW_UART_CPR_SHADOW |
+ DW_UART_CPR_DMA_EXTRA |
+ DW_UART_CPR_FIFO_MODE_FROM_SIZE(16),
.quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC,
};
diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
index 2f26f9ecacbe..1fe52332e774 100644
--- a/drivers/tty/serial/8250/8250_dwlib.h
+++ b/drivers/tty/serial/8250/8250_dwlib.h
@@ -6,6 +6,7 @@
#include <linux/bitfield.h>
#include <linux/bits.h>
+#include <linux/build_bug.h>
#include <linux/io.h>
#include <linux/types.h>
@@ -68,8 +69,13 @@
#define DW_UART_CPR_DMA_EXTRA BIT(13)
#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)
-/* Helper for FIFO size calculation */
+/* Helpers for FIFO size calculation */
#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
+#define DW_UART_CPR_FIFO_MODE_FROM_SIZE(size) \
+ (FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, \
+ BUILD_BUG_ON_ZERO((size) > 2048) + \
+ BUILD_BUG_ON_ZERO((size) % 16) + \
+ ((size) / 16)))
struct dw8250_port_data {
/* Port properties */
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v6 3/4] dt-bindings: serial: snps-dw-apb-uart: Add UltraRISC DP1000 UART
2026-04-29 9:05 [PATCH v6 0/4] serial: 8250_dw: Add support for UltraRISC DP1000 UART Jia Wang
2026-04-29 9:05 ` [PATCH v6 1/4] serial: 8250_dwlib: move DesignWare register definitions to header Jia Wang
2026-04-29 9:05 ` [PATCH v6 2/4] serial: 8250_dw: build Renesas RZN1 CPR value from DW_UART_CPR_* definitions Jia Wang
@ 2026-04-29 9:05 ` Jia Wang
2026-04-29 9:05 ` [PATCH v6 4/4] serial: 8250_dw: Use a fixed CPR value for " Jia Wang
3 siblings, 0 replies; 8+ messages in thread
From: Jia Wang @ 2026-04-29 9:05 UTC (permalink / raw)
To: Ilpo Järvinen, Andy Shevchenko, Greg Kroah-Hartman,
Jiri Slaby, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel, linux-serial, linux-riscv, devicetree, Jia Wang,
Conor Dooley
UltraRISC DP1000 integrates a Synopsys DesignWare APB UART, but it does
not provide the standard CPR and UCV registers.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 685c1eceb782..49f51b002879 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -78,6 +78,7 @@ properties:
- starfive,jh7100-hsuart
- starfive,jh7100-uart
- starfive,jh7110-uart
+ - ultrarisc,dp1000-uart
- const: snps,dw-apb-uart
- const: snps,dw-apb-uart
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v6 4/4] serial: 8250_dw: Use a fixed CPR value for UltraRISC DP1000 UART
2026-04-29 9:05 [PATCH v6 0/4] serial: 8250_dw: Add support for UltraRISC DP1000 UART Jia Wang
` (2 preceding siblings ...)
2026-04-29 9:05 ` [PATCH v6 3/4] dt-bindings: serial: snps-dw-apb-uart: Add UltraRISC DP1000 UART Jia Wang
@ 2026-04-29 9:05 ` Jia Wang
3 siblings, 0 replies; 8+ messages in thread
From: Jia Wang @ 2026-04-29 9:05 UTC (permalink / raw)
To: Ilpo Järvinen, Andy Shevchenko, Greg Kroah-Hartman,
Jiri Slaby, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel, linux-serial, linux-riscv, devicetree, Jia Wang
The UltraRISC DP1000 UART does not provide the standard CPR register used
by 8250_dw to discover port capabilities.
Provide a fixed CPR value for the DP1000-specific compatible so the
driver can configure the port correctly.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/tty/serial/8250/8250_dw.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 480f82d89856..55e40c10f46a 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -959,6 +959,15 @@ static const struct dw8250_platform_data dw8250_intc10ee = {
.quirks = DW_UART_QUIRK_IER_KICK,
};
+static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = {
+ .usr_reg = DW_UART_USR,
+ .cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) |
+ DW_UART_CPR_THRE_MODE |
+ DW_UART_CPR_DMA_EXTRA |
+ DW_UART_CPR_FIFO_MODE_FROM_SIZE(32),
+ .quirks = DW_UART_QUIRK_CPR_VALUE,
+};
+
static const struct of_device_id dw8250_of_match[] = {
{ .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
@@ -966,6 +975,7 @@ static const struct of_device_id dw8250_of_match[] = {
{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
{ .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data },
{ .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
+ { .compatible = "ultrarisc,dp1000-uart", .data = &dw8250_ultrarisc_dp1000_data },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dw8250_of_match);
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v6 1/4] serial: 8250_dwlib: move DesignWare register definitions to header
2026-04-29 9:05 ` [PATCH v6 1/4] serial: 8250_dwlib: move DesignWare register definitions to header Jia Wang
@ 2026-04-29 10:38 ` Ilpo Järvinen
2026-04-29 10:41 ` Andy Shevchenko
0 siblings, 1 reply; 8+ messages in thread
From: Ilpo Järvinen @ 2026-04-29 10:38 UTC (permalink / raw)
To: Jia Wang
Cc: Andy Shevchenko, Greg Kroah-Hartman, Jiri Slaby, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, LKML, linux-serial,
linux-riscv, devicetree
[-- Attachment #1: Type: text/plain, Size: 7786 bytes --]
On Wed, 29 Apr 2026, Jia Wang wrote:
> Move the DW_UART_* register offsets and CPR bit/field definitions from
> 8250_dwlib.c into 8250_dwlib.h so they can be shared by 8250_dw and
> 8250_dwlib users.
>
> Add an include guard for 8250_dwlib.h.
>
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> drivers/tty/serial/8250/8250_dw.c | 11 ------
> drivers/tty/serial/8250/8250_dwlib.c | 49 --------------------------
> drivers/tty/serial/8250/8250_dwlib.h | 67 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 67 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index 94beadb4024d..467755bf0092 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -34,22 +34,11 @@
>
> #include "8250_dwlib.h"
>
> -/* Offsets for the DesignWare specific registers */
> -#define DW_UART_USR 0x1f /* UART Status Register */
> -#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
> -
> #define OCTEON_UART_USR 0x27 /* UART Status Register */
>
> #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
> #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
>
> -/* DesignWare specific register fields */
> -#define DW_UART_IIR_IID GENMASK(3, 0)
> -
> -#define DW_UART_MCR_SIRE BIT(6)
> -
> -#define DW_UART_USR_BUSY BIT(0)
> -
> /* Renesas specific register fields */
> #define RZN1_UART_xDMACR_DMA_EN BIT(0)
> #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
> diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c
> index b055d89cfb39..8859e66d2d71 100644
> --- a/drivers/tty/serial/8250/8250_dwlib.c
> +++ b/drivers/tty/serial/8250/8250_dwlib.c
> @@ -13,55 +13,6 @@
>
> #include "8250_dwlib.h"
>
> -/* Offsets for the DesignWare specific registers */
> -#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
> -#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
> -#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
> -#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
> -#define DW_UART_RAR 0xc4 /* Receive Address Register */
> -#define DW_UART_TAR 0xc8 /* Transmit Address Register */
> -#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */
> -#define DW_UART_CPR 0xf4 /* Component Parameter Register */
> -#define DW_UART_UCV 0xf8 /* UART Component Version */
> -
> -/* Receive / Transmit Address Register bits */
> -#define DW_UART_ADDR_MASK GENMASK(7, 0)
> -
> -/* Line Status Register bits */
> -#define DW_UART_LSR_ADDR_RCVD BIT(8)
> -
> -/* Transceiver Control Register bits */
> -#define DW_UART_TCR_RS485_EN BIT(0)
> -#define DW_UART_TCR_RE_POL BIT(1)
> -#define DW_UART_TCR_DE_POL BIT(2)
> -#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
> -#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
> -#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
> -#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
> -
> -/* Line Extended Control Register bits */
> -#define DW_UART_LCR_EXT_DLS_E BIT(0)
> -#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1)
> -#define DW_UART_LCR_EXT_SEND_ADDR BIT(2)
> -#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3)
> -
> -/* Component Parameter Register bits */
> -#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0)
> -#define DW_UART_CPR_AFCE_MODE BIT(4)
> -#define DW_UART_CPR_THRE_MODE BIT(5)
> -#define DW_UART_CPR_SIR_MODE BIT(6)
> -#define DW_UART_CPR_SIR_LP_MODE BIT(7)
> -#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8)
> -#define DW_UART_CPR_FIFO_ACCESS BIT(9)
> -#define DW_UART_CPR_FIFO_STAT BIT(10)
> -#define DW_UART_CPR_SHADOW BIT(11)
> -#define DW_UART_CPR_ENCODED_PARMS BIT(12)
> -#define DW_UART_CPR_DMA_EXTRA BIT(13)
> -#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)
> -
> -/* Helper for FIFO size calculation */
> -#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
> -
> /*
> * divisor = div(I) + div(F)
> * "I" means integer, "F" means fractional
> diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
> index 7dd2a8e7b780..2f26f9ecacbe 100644
> --- a/drivers/tty/serial/8250/8250_dwlib.h
> +++ b/drivers/tty/serial/8250/8250_dwlib.h
> @@ -1,11 +1,76 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /* Synopsys DesignWare 8250 library header file. */
>
> +#ifndef _SERIAL_8250_DWLIB_H_
> +#define _SERIAL_8250_DWLIB_H_
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> #include <linux/io.h>
> #include <linux/types.h>
>
> #include "8250.h"
>
> +/* Offsets for the DesignWare specific registers */
> +#define DW_UART_USR 0x1f /* UART Status Register */
> +#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
> +#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
> +#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
> +#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
> +#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
> +#define DW_UART_RAR 0xc4 /* Receive Address Register */
> +#define DW_UART_TAR 0xc8 /* Transmit Address Register */
> +#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */
> +#define DW_UART_CPR 0xf4 /* Component Parameter Register */
> +#define DW_UART_UCV 0xf8 /* UART Component Version */
> +
> +/* Interrupt ID Register bits */
> +#define DW_UART_IIR_IID GENMASK(3, 0)
> +
> +/* Modem Control Register bits */
> +#define DW_UART_MCR_SIRE BIT(6)
> +
> +/* Line Status Register bits */
> +#define DW_UART_LSR_ADDR_RCVD BIT(8)
> +
> +/* UART Status Register bits */
> +#define DW_UART_USR_BUSY BIT(0)
> +
> +/* Transceiver Control Register bits */
> +#define DW_UART_TCR_RS485_EN BIT(0)
> +#define DW_UART_TCR_RE_POL BIT(1)
> +#define DW_UART_TCR_DE_POL BIT(2)
> +#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
> +#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
> +#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
> +#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
> +
> +/* Receive / Transmit Address Register bits */
> +#define DW_UART_ADDR_MASK GENMASK(7, 0)
> +
> +/* Line Extended Control Register bits */
> +#define DW_UART_LCR_EXT_DLS_E BIT(0)
> +#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1)
> +#define DW_UART_LCR_EXT_SEND_ADDR BIT(2)
> +#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3)
> +
> +/* Component Parameter Register bits */
> +#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0)
> +#define DW_UART_CPR_AFCE_MODE BIT(4)
> +#define DW_UART_CPR_THRE_MODE BIT(5)
> +#define DW_UART_CPR_SIR_MODE BIT(6)
> +#define DW_UART_CPR_SIR_LP_MODE BIT(7)
> +#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8)
> +#define DW_UART_CPR_FIFO_ACCESS BIT(9)
> +#define DW_UART_CPR_FIFO_STAT BIT(10)
> +#define DW_UART_CPR_SHADOW BIT(11)
> +#define DW_UART_CPR_ENCODED_PARMS BIT(12)
> +#define DW_UART_CPR_DMA_EXTRA BIT(13)
> +#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)
> +
> +/* Helper for FIFO size calculation */
> +#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
> +
> struct dw8250_port_data {
> /* Port properties */
> int line;
> @@ -38,3 +103,5 @@ static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
> else
> writel(reg, p->membase + offset);
> }
> +
> +#endif /* _SERIAL_8250_DWLIB_H_ */
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
--
i.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6 1/4] serial: 8250_dwlib: move DesignWare register definitions to header
2026-04-29 10:38 ` Ilpo Järvinen
@ 2026-04-29 10:41 ` Andy Shevchenko
2026-04-29 10:46 ` Ilpo Järvinen
0 siblings, 1 reply; 8+ messages in thread
From: Andy Shevchenko @ 2026-04-29 10:41 UTC (permalink / raw)
To: Ilpo Järvinen
Cc: Jia Wang, Greg Kroah-Hartman, Jiri Slaby, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, LKML, linux-serial,
linux-riscv, devicetree
On Wed, Apr 29, 2026 at 01:38:44PM +0300, Ilpo Järvinen wrote:
> On Wed, 29 Apr 2026, Jia Wang wrote:
> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
There is v7 already...
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6 1/4] serial: 8250_dwlib: move DesignWare register definitions to header
2026-04-29 10:41 ` Andy Shevchenko
@ 2026-04-29 10:46 ` Ilpo Järvinen
0 siblings, 0 replies; 8+ messages in thread
From: Ilpo Järvinen @ 2026-04-29 10:46 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Jia Wang, Greg Kroah-Hartman, Jiri Slaby, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, LKML, linux-serial,
linux-riscv, devicetree
[-- Attachment #1: Type: text/plain, Size: 423 bytes --]
On Wed, 29 Apr 2026, Andy Shevchenko wrote:
> On Wed, Apr 29, 2026 at 01:38:44PM +0300, Ilpo Järvinen wrote:
> > On Wed, 29 Apr 2026, Jia Wang wrote:
>
> > Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
>
> There is v7 already...
I noticed it after sending the message out. For sport, I also reviewed v7
1/4 now as the diff-of-diffs command was still fresh in the shell history. :-)
--
i.
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-04-29 10:46 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-04-29 9:05 [PATCH v6 0/4] serial: 8250_dw: Add support for UltraRISC DP1000 UART Jia Wang
2026-04-29 9:05 ` [PATCH v6 1/4] serial: 8250_dwlib: move DesignWare register definitions to header Jia Wang
2026-04-29 10:38 ` Ilpo Järvinen
2026-04-29 10:41 ` Andy Shevchenko
2026-04-29 10:46 ` Ilpo Järvinen
2026-04-29 9:05 ` [PATCH v6 2/4] serial: 8250_dw: build Renesas RZN1 CPR value from DW_UART_CPR_* definitions Jia Wang
2026-04-29 9:05 ` [PATCH v6 3/4] dt-bindings: serial: snps-dw-apb-uart: Add UltraRISC DP1000 UART Jia Wang
2026-04-29 9:05 ` [PATCH v6 4/4] serial: 8250_dw: Use a fixed CPR value for " Jia Wang
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