Re: [PATCH v4 02/14] dt-bindings: iio: adc: Add AD7768

[David Lechner <dlechner@baylibre.com>]

On 8/21/26 9:06 AM, Janani Sunil wrote:
> Devicetree Bindings for AD7768-4 (4 channel) and AD7768 (8 channel)
> simultaneous sampling ADCs.
> 
> Signed-off-by: Janani Sunil <janani.sunil@analog.com>
> ---
>  .../devicetree/bindings/iio/adc/adi,ad7768.yaml    | 314 +++++++++++++++++++++
>  MAINTAINERS                                        |   7 +
>  2 files changed, 321 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml
> new file mode 100644
> index 000000000000..df4b179df988
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768.yaml
> @@ -0,0 +1,314 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/adc/adi,ad7768.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices AD7768 and AD7768-4 ADC
> +
> +maintainers:
> +  - Janani Sunil <janani.sunil@analog.com>
> +
> +description: |
> +  The AD7768 is an 8-channel, 24-bit simultaneous sampling ADC with configurable
> +  power and performance modes. The AD7768-4 is a 4-channel version.
> +
> +  This binding covers SPI mode only (register access via SPI). Pin control mode,
> +  where configuration is set via hardware pins rather than SPI registers, is not
> +  supported.
> +
> +  The io-backend represents the high-speed data output interface, consuming the
> +  DOUTx data lines, DCLK (data clock), and DRDY (data ready) signals.
> +
> +  Datasheet at:
> +    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-ad7768-4.pdf
> +
> +  HDL reference design:
> +    https://github.com/analogdevicesinc/hdl/tree/main/projects/ad7768evb
> +
> +properties:
> +  compatible:
> +    enum:
> +      - adi,ad7768
> +      - adi,ad7768-4
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +    description:
> +      Master clock (MCLK). Can be supplied as a CMOS clock on the XTAL2/MCLK
> +      pin, a crystal oscillator connected between the XTAL1 and XTAL2 pins, or
> +      an LVDS differential clock on the XTAL1/XTAL2 pin pair. CMOS and LVDS
> +      clocks must operate from 1.15 MHz to 34 MHz. Crystals must operate from
> +      8 MHz to 34 MHz.
> +
> +  clock-names:
> +    description:
> +      Identifies the master clock source.

It would be more accurate to say that this describes the type of clock that is
attached to the XTAL1 and XTAL2/MCLK pins. In other words, drop the description
from clocks and move it here.

> +    enum:
> +      - mclk
> +      - xtal
> +      - lvds
> +    default: mclk
> +
> +  avdd1-supply:
> +    description:
> +      Analog supply voltage for the AVDD1A and AVDD1B pins (5V ± 10% with
> +      respect to AVSS). Powers the analog front end, reference input, and
> +      common-mode output circuitry. Both pins must be tied to the same
> +      potential.
> +
> +  avss-supply:
> +    description:
> +      Negative analog supply rail for the AVSS1A, AVSS1B, AVSS2A, AVSS2B,
> +      and AVSS pins. This rail is referenced to DGND and all AVSS pins must
> +      be tied to the same potential. In single-supply operation AVSS is
> +      nominally 0 V; in split-supply operation it can range from 0 V to
> +      -2.75 V with respect to DGND. If omitted, AVSS is assumed to be at
> +      system ground (0 V).
> +
> +  avdd2-supply:
> +    description:
> +      Analog supply voltage for the AVDD2A and AVDD2B pins (2V to 5.5V with
> +      respect to AVSS). Connects to internal 1.8V analog LDO regulators that
> +      power the ADC core. Both pins must be tied to the same potential.
> +
> +  iovdd-supply:
> +    description:
> +      Digital supply voltage IOVDD (2.25V to 3.6V with respect to DGND).
> +      Sets the logic levels for all interface pins and powers the digital
> +      processing core via an internal LDO. For 1.8V operation (1.72V to
> +      1.88V), IOVDD must be tied to the DREGCAP pin.
> +
> +  ref1p-supply:
> +    description:
> +      Positive reference input supply for REF1+. The voltage range is from
> +      (AVSS + 1 V) to AVDD1. Together, REF1+ and REF1- must provide a
> +      differential reference voltage from 1 V to |AVDD1 - AVSS|. This
> +      reference is used by channels 0 to 3 on the AD7768 and channels 0 and 1
> +      on the AD7768-4.
> +
> +  ref1n-supply:
> +    description:
> +      Negative reference input supply for REF1-. The voltage range is from
> +      AVSS to (AVDD1 - 1 V).
> +
> +  ref2p-supply:
> +    description:
> +      Positive reference input supply for REF2+. The voltage range is from
> +      (AVSS + 1 V) to AVDD1. Together, REF2+ and REF2- must provide a
> +      differential reference voltage from 1 V to |AVDD1 - AVSS|. This
> +      reference is used by channels 4 to 7 on the AD7768 and channels 2 and 3
> +      on the AD7768-4.
> +
> +  ref2n-supply:
> +    description:
> +      Negative reference input supply for REF2-. The voltage range is from
> +      AVSS to (AVDD1 - 1 V).

For all of the supplies, I don't think we need to repeat so much of what the
datasheet says. It is getting quite noisy and makes it hard to see the parts
of the description that are actually relevant to how the devicetree is to be
interpreted. (includes VCM as well)

> +
> +  reset-gpios:
> +    maxItems: 1
> +    description: GPIO connected to the active-low RESET pin
> +
> +  start-gpios:
> +    maxItems: 1
> +    description:
> +      GPIO connected to the START pin. An active-low pulse on this pin
> +      synchronizes the device to other AD7768 devices. When not used, this
> +      pin must be tied to a logic high level through a pull-up resistor.
> +      When used, SYNC_OUT must be wired back to SYNC_IN on all devices in
> +      the synchronization chain.
> +
> +  sync-in-gpios:
> +    maxItems: 1
> +    description:
> +      GPIO connected to the SYNC_IN pin. Receives the synchronization pulse
> +      generated on SYNC_OUT in response to a START pulse. Must be synchronous
> +      to the MCLK clock domain. In multi-device or daisy-chained systems,
> +      two successive synchronization pulses must be applied to guarantee all
> +      ADCs are synchronized.
> +
> +  sync-out-gpios:

Unusual to have an output pin connected to a GPIO. Usually this would be an
interrupt or trigger-sources.

> +    maxItems: 1
> +    description:
> +      GPIO connected to the SYNC_OUT pin. Outputs a synchronization pulse
> +      synchronous to MCLK in response to a START pulse or SPI_SYNC command.
> +      In single-device configurations this pin must be wired back to SYNC_IN.
> +      In multi-device configurations it can be routed to the SYNC_IN pins of
> +      all devices in the chain.

Although this description makes it sounds like the SYNC_OUT pin is only ever
wired to SYNC_IN. So wouldn't be described here at all.

> +
> +  gpio-controller: true
> +
> +  '#gpio-cells':
> +    const: 2
> +
> +  adi,data-lines-number:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [1, 2, 4, 8]
> +    description:
> +      Number of DOUTx lines used for the high-speed data output interface
> +      (distinct from the SPI control interface). AD7768 supports 1, 2, or 8
> +      lines; AD7768-4 supports 1 or 4 lines. Defaults to the maximum number
> +      of lines for the selected variant if omitted.
> +
> +  regulators:
> +    type: object
> +    description: Container for the on-chip VCM regulator.
> +    additionalProperties: false
> +
> +    properties:
> +      vcm-output:
> +        type: object
> +        description:
> +          The VCM pin provides a buffered common-mode voltage output used to
> +          bias the analog inputs. It supports three fixed output levels of
> +          1650000 uV, 2500000 uV, and 2140000 uV, as well as a
> +          supply-dependent (AVDD1 - AVSS) / 2 output derived from
> +          avdd1-supply. Select the voltage by setting regulator-min-microvolt
> +          and regulator-max-microvolt to the same value. Use
> +          regulator-always-on when no DT consumer node references the VCM
> +          output. The VCM circuitry is associated with channel 0. When VCM is
> +          used externally, channel@0 must be present and kept enabled because
> +          placing channel 0 in standby disables the VCM output.
> +        $ref: /schemas/regulator/regulator.yaml#
> +        unevaluatedProperties: false
> +
> +  io-backends:
> +    maxItems: 1
> +