From: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
To: Jonathan Cameron <jic23@kernel.org>
Cc: "David Lechner" <dlechner@baylibre.com>,
"Nuno Sá" <nuno.sa@analog.com>,
"Andy Shevchenko" <andy@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Amit Kucheria" <amitk@kernel.org>,
"Thara Gopinath" <thara.gopinath@gmail.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
"Daniel Lezcano" <daniel.lezcano@kernel.org>,
"Zhang Rui" <rui.zhang@intel.com>,
"Lukasz Luba" <lukasz.luba@arm.com>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konradybcio@kernel.org>,
linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-pm@vger.kernel.org,
"Kamal Wadhwa" <kamal.wadhwa@oss.qualcomm.com>,
"Anjelique Melendez" <anjelique.melendez@oss.qualcomm.com>,
"Manaf Meethalavalappu Pallikunhi"
<manaf.pallikunhi@oss.qualcomm.com>,
"Priyansh Jain" <priyansh.jain@oss.qualcomm.com>
Subject: Re: [PATCH 3/7] thermal: qcom: qcom-spmi-adc-tm5-gen3: Add support for QCOM PMIC5 Gen4 ADC
Date: Thu, 6 Aug 2026 16:22:35 +0530 [thread overview]
Message-ID: <752aaae3-10bf-4714-bfef-e075ce30604c@oss.qualcomm.com> (raw)
In-Reply-To: <20260803011709.31cf83f2@jic23-huawei>
Hi Jonathan,
On 8/3/2026 5:47 AM, Jonathan Cameron wrote:
> On Fri, 31 Jul 2026 23:36:16 +0530
> Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> wrote:
>
>> PMIC5 Gen4 ADC is similar to PMIC5 Gen3 ADC, with several changes made
>> for improved performance, mostly at the hardware level.
>>
>> One significant software change is that ratiometric conversion resolution
>> has been increased from 14 bits to 16 bits. Add a reverse scaling function
>> for Gen4 ADC thermistor channels.
>>
>> In the latest PMIC arbiter version (v8), there can be up to 4 buses
>> under the PMIC arbiter and 32 PMICs under each bus. In order to
>> support communication between ADC on the master PMIC and ADCs on any
>> of the other PMICs, a field of width 2 bits is added for bus index
>> and the bits for SID are extended from 4 to 5 bits, in the SID
>> register. Add support for this.
>>
>> Co-developed-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com>
>> Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com>
>> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
> Hi Jishnu, Anjelique
>
> Code looks fine, but I just wanted to check. What happens if
> for some reason the patch before ends up in a tree and this one doesn't
> Do we read the wrong temperatures given 'bus' isn't specified?
>
Actually from what I see, patches 2 and 3 need to go in together, else
there would be a compilation error in one driver. This is because patch 2
replaces two macros, which are used in both the IIO and thermal drivers:
ADC5_GEN3_SID_MASK -> ADC5_GEN4_SID_MASK
ADC5_GEN3_V_CHAN -> ADC5_GEN4_V_CHAN
It looks like I missed checking for bisectability, sorry about that.
To avoid this, I'll add the new macros in patch 2 and remove the
old ones in a separate new patch after patch 3.
To answer your question once bisectability is fixed:
The changes in this TM file affect the flow in the .set_trips() call, which
is used for setting high/low temperature thresholds. The .get_temp() is
not affected, as it directly calls into the main ADC driver using the
exported function adc5_gen3_get_scaled_reading().
For the specific situation you mentioned - temperature reading for Gen4
channels using get_temp() would work correctly with patch 2 in place, but
setting high/low thresholds would go wrong for all Gen4 channels as the
conversion formula is different. Bus index not being specified would
also cause errors for configuring channels on bus numbers other than 0.
Thanks,
Jishnu
> Jonathan
>
next prev parent reply other threads:[~2026-08-06 10:52 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-31 18:06 [PATCH 0/7] Add support for QCOM SPMI PMIC5 Gen4 ADC Jishnu Prakash
2026-07-31 18:06 ` [PATCH 1/7] dt-bindings: iio: adc: Add support for QCOM " Jishnu Prakash
2026-08-02 23:49 ` Jonathan Cameron
2026-08-06 10:52 ` Jishnu Prakash
2026-08-06 23:14 ` Jonathan Cameron
2026-08-04 8:20 ` Krzysztof Kozlowski
2026-08-06 10:53 ` Jishnu Prakash
2026-07-31 18:06 ` [PATCH 2/7] iio: adc: qcom-spmi-adc5-gen3: " Jishnu Prakash
2026-08-03 0:14 ` Jonathan Cameron
2026-08-06 10:52 ` Jishnu Prakash
2026-08-06 23:18 ` Jonathan Cameron
2026-08-07 8:07 ` Jishnu Prakash
2026-07-31 18:06 ` [PATCH 3/7] thermal: qcom: qcom-spmi-adc-tm5-gen3: " Jishnu Prakash
2026-08-03 0:17 ` Jonathan Cameron
2026-08-06 10:52 ` Jishnu Prakash [this message]
2026-07-31 18:06 ` [PATCH 4/7] arm64: dts: qcom: Add header file for ADC5 Gen4 channel macros Jishnu Prakash
2026-07-31 18:06 ` [PATCH 5/7] arm64: dts: qcom: pmk8850: Add ADC5 Gen4 peripheral Jishnu Prakash
2026-07-31 18:06 ` [PATCH 6/7] arm64: dts: qcom: glymur: Add ADC support for Glymur CRD Jishnu Prakash
2026-07-31 18:06 ` [PATCH 7/7] arm64: dts: qcom: kaanapali: Add ADC support for Kaanapali boards Jishnu Prakash
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