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From: Qiang Yu <quic_qianyu@quicinc.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: <manivannan.sadhasivam@linaro.org>, <vkoul@kernel.org>,
	<kishon@kernel.org>, <robh@kernel.org>, <andersson@kernel.org>,
	<konradybcio@kernel.org>, <krzk+dt@kernel.org>,
	<conor+dt@kernel.org>, <mturquette@baylibre.com>,
	<sboyd@kernel.org>, <abel.vesa@linaro.org>,
	<quic_msarkar@quicinc.com>, <quic_devipriy@quicinc.com>,
	<dmitry.baryshkov@linaro.org>, <kw@linux.com>,
	<lpieralisi@kernel.org>, <neil.armstrong@linaro.org>,
	<linux-arm-msm@vger.kernel.org>, <linux-phy@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH 1/8] phy: qcom-qmp: pcs-pcie: Add v6.30 register offsets
Date: Wed, 28 Aug 2024 17:41:32 +0800	[thread overview]
Message-ID: <79a294b3-90a7-4900-bac1-281d321c9a55@quicinc.com> (raw)
In-Reply-To: <2ojutgxk4kplxwrxxcq5zorejuohbow7dr6lhl4cwndkwzvxf6@lxg4um6krdnh>


On 8/27/2024 7:37 PM, Krzysztof Kozlowski wrote:
> On Mon, Aug 26, 2024 at 11:36:24PM -0700, Qiang Yu wrote:
>> x1e80100 SoC uses QMP phy with version v6.30 for PCIe Gen4 x8. Add the new
>> PCS PCIE specific offsets in a dedicated header file.
>>
>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
>> ---
>>   .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h    | 25 +++++++++++++++++++
>>   1 file changed, 25 insertions(+)
>>   create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h
>> new file mode 100644
>> index 000000000000..5a58ff197e6e
>> --- /dev/null
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (c) 2024 Qualcomm Innovation Center. All rights reserved.
>> + */
>> +
>> +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_30_H_
>> +#define QCOM_PHY_QMP_PCS_PCIE_V6_30_H_
>> +
>> +/* Only for QMP V6_30 PHY - PCIE have different offsets than V6 */
>> +#define QPHY_PCIE_V6_30_PCS_POWER_STATE_CONFIG2		0x014
>> +#define QPHY_PCIE_V6_30_PCS_TX_RX_CONFIG		0x020
>> +#define QPHY_PCIE_V6_30_PCS_ENDPOINT_REFCLK_DRIVE	0x024
>> +#define QPHY_PCIE_V6_30_PCS_OSC_DTCT_ACTIONS		0x098
>> +#define QPHY_PCIE_V6_30_PCS_EQ_CONFIG1			0x0a8
>> +#define QPHY_PCIE_V6_30_PCS_G3_RXEQEVAL_TIME		0x0f8
>> +#define QPHY_PCIE_V6_30_PCS_G4_RXEQEVAL_TIME		0x0fc
>> +#define QPHY_PCIE_V6_30_PCS_G4_EQ_CONFIG5		0x110
>> +#define QPHY_PCIE_V6_30_PCS_G4_PRE_GAIN			0x164
>> +#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG1	0x184
>> +#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG3	0x18c
>> +#define QPHY_PCIE_V6_30_PCS_RX_MARGINING_CONFIG5	0x194
>> +#define QPHY_PCIE_V6_30_PCS_G3_FOM_EQ_CONFIG5		0x1b4
>> +#define QPHY_PCIE_V6_30_PCS_G4_FOM_EQ_CONFIG5		0x1c8
> There is no user of these. Squash it with the user, because there is
> little point in adding dead code.
>
> Best regards,
> Krzysztof
OK, will squash this three patches related to phy setting into one patch.

Thanks,
Qiang

  reply	other threads:[~2024-08-28  9:41 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-27  6:36 [PATCH 0/8] Add support for PCIe3 on x1e80100 Qiang Yu
2024-08-27  6:36 ` [PATCH 1/8] phy: qcom-qmp: pcs-pcie: Add v6.30 register offsets Qiang Yu
2024-08-27 11:37   ` Krzysztof Kozlowski
2024-08-28  9:41     ` Qiang Yu [this message]
2024-08-27  6:36 ` [PATCH 2/8] phy: qcom-qmp: pcs: " Qiang Yu
2024-08-27 10:13   ` Konrad Dybcio
2024-08-27  6:36 ` [PATCH 3/8] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 Qiang Yu
2024-08-27 10:33   ` Konrad Dybcio
2024-08-28  9:47     ` Qiang Yu
2024-08-27 11:38   ` Krzysztof Kozlowski
2024-08-28  9:52     ` Qiang Yu
2024-08-27  6:36 ` [PATCH 4/8] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 Qiang Yu
2024-08-27 10:42   ` Konrad Dybcio
2024-08-28 13:36     ` Qiang Yu
2024-09-11  8:22       ` Qiang Yu
2024-08-27 11:39   ` Krzysztof Kozlowski
2024-08-27  6:36 ` [PATCH 5/8] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 Qiang Yu
2024-08-27 11:36   ` Krzysztof Kozlowski
2024-08-27  6:36 ` [PATCH 6/8] clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks Qiang Yu
2024-08-27 10:10   ` Konrad Dybcio
2024-08-27  6:36 ` [PATCH 7/8] arm64: dts: qcom: x1e80100-qcp: Add power supply and sideband signal for pcie3 Qiang Yu
2024-08-27 11:41   ` Krzysztof Kozlowski
2024-08-27  6:36 ` [PATCH 8/8] PCI: qcom: Add support to PCIe slot power supplies Qiang Yu
2024-08-27 11:02   ` Konrad Dybcio
2024-08-27 11:44   ` Dmitry Baryshkov
2024-08-27 16:58     ` Manivannan Sadhasivam
2024-09-11  8:17       ` Qiang Yu
2024-09-11 15:32         ` Manivannan Sadhasivam
2024-09-12 13:39           ` Qiang Yu
2024-09-12 14:15             ` Konrad Dybcio
2024-09-12 14:44               ` Manivannan Sadhasivam
2024-09-12 14:49                 ` Dmitry Baryshkov
2024-09-13  8:41                   ` Qiang Yu
2024-08-28 13:44     ` Qiang Yu
2024-08-27 12:31 ` [PATCH 0/8] Add support for PCIe3 on x1e80100 Rob Herring (Arm)

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