From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: "Thomas Gleixner" <tglx@kernel.org>,
"Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>,
"Benoît Monin" <benoit.monin@bootlin.com>,
"Théo Lebrun" <theo.lebrun@bootlin.com>,
"Radu Rendec" <radu@rendec.net>, "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 2/4] irqchip: irq-eyeq5-msi: add EyeQ5 PCIe MSI controller driver
Date: Mon, 02 Nov 2026 17:17:43 +0100 [thread overview]
Message-ID: <875wyf2ons.fsf@BLaptop.bootlin.com> (raw)
In-Reply-To: <87v76ly4jy.ffs@fw13>
Hello Thomas,
> On Wed, Oct 28 2026 at 16:58, Gregory CLEMENT wrote:
>> +/*
>> + * The caller must hold msi->lock.
>
> Instead of a non-enforcable comment can you please put a
> lockdep_assert_held() into the code.
OK
>
>> + */
>> +static void __eyeq_msi_mask_irq(struct eyeq_msi *msi, unsigned int bit)
>> +{
>> + u16 value;
>> +
>> + value = readw(msi->gcsr_base + GCSR_IRQMASK);
>> + value &= ~FIELD_PREP(GCSR_IRQMASK_MASK, BIT(bit));
>> + writew(value, msi->gcsr_base + GCSR_IRQMASK);
>> +}
>
>> +static struct irq_chip eyeq_msi_irq_chip = {
>> + .name = "EyeQ5-MSI",
>> + .irq_mask = eyeq_msi_mask_irq,
>> + .irq_unmask = eyeq_msi_unmask_irq,
>> + .irq_compose_msi_msg = eyeq_msi_compose_msg,
>> +};
>> +
>> +static void eyeq_msi_isr(struct irq_desc *desc)
>> +{
>> + struct irq_chip *parent_chip = irq_desc_get_chip(desc);
>> + struct eyeq_msi *msi = irq_desc_get_handler_data(desc);
>> + void __iomem *status_reg;
>> + unsigned long pending;
>> + unsigned int bit;
>> + int ret;
>> +
>> + chained_irq_enter(parent_chip, desc);
>> +
>> + status_reg = msi->gcsr_base + GCSR_IRQSTATUS;
>> +
>> + while (true) {
>> + pending = FIELD_GET(GCSR_IRQSTATUS_MASK,
>> + readw(status_reg));
>> + if (!pending)
>> + break;
>> +
>> + /*
>> + * Write-one-to-clear status register.
>> + */
>> + writew(FIELD_PREP(GCSR_IRQSTATUS_MASK, pending),
>> + status_reg);
>> +
>> + for_each_set_bit(bit, &pending, msi->num_vectors) {
>> + ret = generic_handle_domain_irq(msi->msi_domain, bit);
>
> You want to look at generic_handle_demux_domain_irq() and related
> functionality so you can actually provide a irq_set_affinity() callback
> for these demultiplexed interrupts.
Thanks for the pointer! Indeed, once I used
generic_handle_demux_domain_irq(), it was possible to use affinity, I
managed to test it on the hardware.
>
>> + if (ret)
>> + pr_err_ratelimited("unmapped MSI interrupt %u\n",
>> + bit);
>
> No line break required. You have 100 characters. Otherwise this needs
> curly brackets around the "two-liner".
>
I took into account this remarks and all the other ones about style and
formatting.
Thanks,
Gregory
--
Grégory CLEMENT, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
next prev parent reply other threads:[~2026-11-02 16:17 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-28 15:58 [PATCH 0/4] irqchip: add EyeQ5 PCIe MSI controller Gregory CLEMENT
2026-10-28 15:58 ` [PATCH 1/4] dt-bindings: interrupt-controller: add Mobileye " Gregory CLEMENT
2026-10-28 16:17 ` sashiko-bot
2026-10-29 7:35 ` Krzysztof Kozlowski
2026-11-02 15:55 ` Gregory CLEMENT
2026-10-28 15:58 ` [PATCH 2/4] irqchip: irq-eyeq5-msi: add EyeQ5 PCIe MSI controller driver Gregory CLEMENT
2026-10-28 16:22 ` sashiko-bot
2026-10-28 20:05 ` Thomas Gleixner
2026-11-02 16:17 ` Gregory CLEMENT [this message]
2026-10-28 15:58 ` [PATCH 3/4] MIPS: dts: eyeq5: add MSI controllers Gregory CLEMENT
2026-10-29 7:36 ` Krzysztof Kozlowski
2026-10-28 15:58 ` [PATCH 4/4] MAINTAINERS: add EyeQ5 MSI controller entry Gregory CLEMENT
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