* Re: [PATCH v9 04/12] reset: realtek: Add RTD1625-ISO reset controller driver
From: Philipp Zabel @ 2026-06-25 10:22 UTC (permalink / raw)
To: Yu-Chun Lin [林祐君], mturquette@baylibre.com,
sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, Edgar Lee [李承諭],
afaerber@suse.com, Jyan Chou [周芷安],
bmasney@redhat.com
Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-realtek-soc@lists.infradead.org,
James Tai [戴志峰],
CY_Huang[黃鉦晏],
Stanley Chang[昌育德]
In-Reply-To: <f3b747e20110424c8a434cbd271edb87@realtek.com>
On Do, 2026-06-25 at 10:05 +0000, Yu-Chun Lin [林祐君] wrote:
> Hi Philipp,
>
> > On Mi, 2026-06-24 at 19:29 +0800, Yu-Chun Lin wrote:
> > > From: Cheng-Yu Lee <cylee12@realtek.com>
> > >
> > > Add support for the ISO (Isolation) domain reset controller on the
> > > Realtek
> > > RTD1625 SoC.
> > >
> > > The reset controller shares the same register space with the ISO clock
> > > controller. To handle this shared register space, the reset driver is
> > > implemented as an auxiliary driver. It will be instantiated and probed
> > > via the auxiliary bus by the RTD1625-ISO clock controller driver.
> > >
> > > Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com>
> > > Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> > > Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> > > ---
> > > Changes in v9:
> > > - Extract reset-related code from the previous clock driver patch
> > > (formerly patch 9 in v8).
> > > ---
> > > drivers/reset/realtek/Makefile | 2 +-
> > > drivers/reset/realtek/reset-rtd1625-iso.c | 99
> > > +++++++++++++++++++++++
> > > 2 files changed, 100 insertions(+), 1 deletion(-) create mode 100644
> > > drivers/reset/realtek/reset-rtd1625-iso.c
> > >
> > > diff --git a/drivers/reset/realtek/Makefile
> > > b/drivers/reset/realtek/Makefile index c3f605ffb11c..9007c9d5683b
> > > 100644
> > > --- a/drivers/reset/realtek/Makefile
> > > +++ b/drivers/reset/realtek/Makefile
> > > @@ -1,3 +1,3 @@
> > > # SPDX-License-Identifier: GPL-2.0-only
> > > obj-$(CONFIG_RESET_RTK_COMMON) += reset-rtk-common.o
> > > -obj-$(CONFIG_RESET_RTD1625) += reset-rtd1625-crt.o
> > > +obj-$(CONFIG_RESET_RTD1625) += reset-rtd1625-crt.o
> > > +reset-rtd1625-iso.o
> >
> > Is there any benefit to these two being separate modules?
> > I suggest you merge them into one: reset-rtd1625.o
> >
>
> If I merge them into a single 'reset-rtd1625' module,
> both the 'crt' and 'iso' clock drivers would trigger the probe
> process for the same reset driver name, which would lead to a
> duplicate driver registration error.
What do you mean by duplicate driver registration error?
There would only be one auxiliary_driver, with support for all three
auxiliary_device_id's.
regards
Philipp
^ permalink raw reply
* [PATCH] dt-bindings: arm: qcom: sort compatibles alphabetically by base SoC
From: Kathiravan Thirumoorthy @ 2026-06-25 10:32 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Konrad Dybcio,
Kathiravan Thirumoorthy
The compatible entries in qcom.yaml were not in alphabetical order by
their base SoC compatible string (the last const: qcom,* in each block),
making the file harder to audit and maintain. Sort the entries for
better maintenance.
No functional change; reordering only.
Assisted-by: Claude:claude-sonnet-4-6
Suggested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 490 ++++++++++++------------
1 file changed, 245 insertions(+), 245 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 50cc18a6ec5e..dfbc82377fcf 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -49,18 +49,31 @@ properties:
- qcom,apq8074-dragonboard
- const: qcom,apq8074
- - items:
- - enum:
- - qcom,apq8060-dragonboard
- - qcom,msm8660-surf
- - const: qcom,msm8660
-
- items:
- enum:
- qcom,apq8084-mtp
- qcom,apq8084-sbc
- const: qcom,apq8084
+ - items:
+ - enum:
+ - sony,karin_windy
+ - const: qcom,apq8094
+
+ - items:
+ - enum:
+ - arrow,apq8096-db820c
+ - inforce,ifc6640
+ - const: qcom,apq8096-sbc
+ - const: qcom,apq8096
+
+ - items:
+ - const: arrow,apq8096sg-db820c
+ - const: arrow,apq8096-db820c
+ - const: qcom,apq8096-sbc
+ - const: qcom,apq8096sg
+ - const: qcom,apq8096
+
- items:
- enum:
- qcom,eliza-mtp
@@ -73,102 +86,126 @@ properties:
- items:
- enum:
- - qcom,mahua-crd
- - const: qcom,mahua
+ - 8dev,jalapeno
+ - alfa-network,ap120c-ac
+ - const: qcom,ipq4018
- items:
- enum:
- - fairphone,fp6
- - nothing,asteroids
- - const: qcom,milos
+ - qcom,ipq4019-ap-dk01.1-c1
+ - qcom,ipq4019-ap-dk04.1-c3
+ - qcom,ipq4019-ap-dk07.1-c1
+ - qcom,ipq4019-ap-dk07.1-c2
+ - qcom,ipq4019-dk04.1-c1
+ - const: qcom,ipq4019
- items:
- enum:
- - microsoft,dempsey
- - microsoft,makepeace
- - microsoft,moneypenny
- - motorola,falcon
- - samsung,ms013g
- - samsung,s3ve3g
- - const: qcom,msm8226
+ - qcom,ipq5018-rdp432-c2
+ - tplink,archer-ax55-v1
+ - const: qcom,ipq5018
- items:
- enum:
- - htc,memul
- - microsoft,superman-lte
- - microsoft,tesla
- - motorola,peregrine
- - samsung,matisselte
- - const: qcom,msm8926
- - const: qcom,msm8226
+ - qcom,ipq5210-rdp504
+ - const: qcom,ipq5210
- items:
- enum:
- - wingtech,wt82918hd
- - const: qcom,msm8929
+ - qcom,ipq5332-ap-mi01.2
+ - qcom,ipq5332-ap-mi01.3
+ - qcom,ipq5332-ap-mi01.6
+ - qcom,ipq5332-ap-mi01.9
+ - const: qcom,ipq5332
- items:
- enum:
- - asus,z00t
- - huawei,kiwi
- - longcheer,l9100
- - samsung,a7
- - sony,kanuti-tulip
- - square,apq8039-t2
- - wingtech,wt82918
- - wingtech,wt82918hdhw39
- - const: qcom,msm8939
+ - qcom,ipq5424-rdp466
+ - const: qcom,ipq5424
- items:
- enum:
- - sony,kugo-row
- - sony,suzu-row
- - const: qcom,msm8956
+ - qcom,ipq6018-cp01
+ - qcom,ipq6018-cp01-c1
+ - const: qcom,ipq6018
- items:
- enum:
- - qcom,msm8960-cdp
- - samsung,expressatt
- - const: qcom,msm8960
+ - mikrotik,rb3011
+ - qcom,ipq8064-ap148
+ - const: qcom,ipq8064
- items:
- enum:
- - sony,huashan
- - const: qcom,msm8960t
- - const: qcom,msm8960
+ - qcom,ipq8074-hk01
+ - qcom,ipq8074-hk10-c1
+ - qcom,ipq8074-hk10-c2
+ - const: qcom,ipq8074
- items:
- enum:
- - lge,hammerhead
- - samsung,hlte
- - sony,xperia-amami
- - sony,xperia-honami
- - sony,xperia-togari
- - const: qcom,msm8974
+ - qcom,ipq9574-ap-al02-c2
+ - qcom,ipq9574-ap-al02-c2-emmc
+ - qcom,ipq9574-ap-al02-c6
+ - qcom,ipq9574-ap-al02-c7
+ - qcom,ipq9574-ap-al02-c7-emmc
+ - qcom,ipq9574-ap-al02-c8
+ - qcom,ipq9574-ap-al02-c9
+ - const: qcom,ipq9574
- items:
- enum:
- - fairphone,fp2
- - htc,m8
- - oneplus,bacon
- - samsung,klte
- - sony,xperia-aries
- - sony,xperia-castor
- - sony,xperia-leo
- - const: qcom,msm8974pro
- - const: qcom,msm8974
+ - qcom,ipq9650-rdp488
+ - const: qcom,ipq9650
- items:
- enum:
- - samsung,kltechn
- - const: samsung,klte
- - const: qcom,msm8974pro
- - const: qcom,msm8974
+ - qcom,kaanapali-mtp
+ - qcom,kaanapali-qrd
+ - const: qcom,kaanapali
- items:
- enum:
- - longcheer,l9360
- - const: qcom,msm8976
+ - qcom,mahua-crd
+ - const: qcom,mahua
+
+ - description: Sierra Wireless MangOH Green with WP8548 Module
+ items:
+ - const: swir,mangoh-green-wp8548
+ - const: swir,wp8548
+ - const: qcom,mdm9615
+
+ - items:
+ - enum:
+ - fairphone,fp6
+ - nothing,asteroids
+ - const: qcom,milos
+
+ - items:
+ - enum:
+ - microsoft,dempsey
+ - microsoft,makepeace
+ - microsoft,moneypenny
+ - motorola,falcon
+ - samsung,ms013g
+ - samsung,s3ve3g
+ - const: qcom,msm8226
+
+ - items:
+ - enum:
+ - htc,memul
+ - microsoft,superman-lte
+ - microsoft,tesla
+ - motorola,peregrine
+ - samsung,matisselte
+ - const: qcom,msm8926
+ - const: qcom,msm8226
+
+ - items:
+ - enum:
+ - qcom,apq8060-dragonboard
+ - qcom,msm8660-surf
+ - const: qcom,msm8660
- items:
- enum:
@@ -217,11 +254,28 @@ properties:
- xiaomi,tiare
- const: qcom,msm8917
+ - items:
+ - enum:
+ - wingtech,wt82918hd
+ - const: qcom,msm8929
+
- items:
- enum:
- xiaomi,land
- const: qcom,msm8937
+ - items:
+ - enum:
+ - asus,z00t
+ - huawei,kiwi
+ - longcheer,l9100
+ - samsung,a7
+ - sony,kanuti-tulip
+ - square,apq8039-t2
+ - wingtech,wt82918
+ - wingtech,wt82918hdhw39
+ - const: qcom,msm8939
+
- items:
- enum:
- flipkart,rimob
@@ -232,6 +286,57 @@ properties:
- xiaomi,vince
- const: qcom,msm8953
+ - items:
+ - enum:
+ - sony,kugo-row
+ - sony,suzu-row
+ - const: qcom,msm8956
+
+ - items:
+ - enum:
+ - qcom,msm8960-cdp
+ - samsung,expressatt
+ - const: qcom,msm8960
+
+ - items:
+ - enum:
+ - sony,huashan
+ - const: qcom,msm8960t
+ - const: qcom,msm8960
+
+ - items:
+ - enum:
+ - lge,hammerhead
+ - samsung,hlte
+ - sony,xperia-amami
+ - sony,xperia-honami
+ - sony,xperia-togari
+ - const: qcom,msm8974
+
+ - items:
+ - enum:
+ - fairphone,fp2
+ - htc,m8
+ - oneplus,bacon
+ - samsung,klte
+ - sony,xperia-aries
+ - sony,xperia-castor
+ - sony,xperia-leo
+ - const: qcom,msm8974pro
+ - const: qcom,msm8974
+
+ - items:
+ - enum:
+ - samsung,kltechn
+ - const: samsung,klte
+ - const: qcom,msm8974pro
+ - const: qcom,msm8974
+
+ - items:
+ - enum:
+ - longcheer,l9360
+ - const: qcom,msm8976
+
- items:
- enum:
- lg,bullhead
@@ -240,11 +345,6 @@ properties:
- xiaomi,libra
- const: qcom,msm8992
- - items:
- - enum:
- - sony,karin_windy
- - const: qcom,apq8094
-
- items:
- enum:
- huawei,angler
@@ -256,20 +356,6 @@ properties:
- sony,suzuran-row
- const: qcom,msm8994
- - items:
- - enum:
- - arrow,apq8096-db820c
- - inforce,ifc6640
- - const: qcom,apq8096-sbc
- - const: qcom,apq8096
-
- - items:
- - const: arrow,apq8096sg-db820c
- - const: arrow,apq8096-db820c
- - const: qcom,apq8096-sbc
- - const: qcom,apq8096sg
- - const: qcom,apq8096
-
- items:
- enum:
- oneplus,oneplus3
@@ -303,86 +389,6 @@ properties:
- xiaomi,sagit
- const: qcom,msm8998
- - items:
- - enum:
- - 8dev,jalapeno
- - alfa-network,ap120c-ac
- - const: qcom,ipq4018
-
- - items:
- - enum:
- - qcom,ipq4019-ap-dk01.1-c1
- - qcom,ipq4019-ap-dk04.1-c3
- - qcom,ipq4019-ap-dk07.1-c1
- - qcom,ipq4019-ap-dk07.1-c2
- - qcom,ipq4019-dk04.1-c1
- - const: qcom,ipq4019
-
- - items:
- - enum:
- - qcom,ipq5018-rdp432-c2
- - tplink,archer-ax55-v1
- - const: qcom,ipq5018
-
- - items:
- - enum:
- - qcom,ipq5210-rdp504
- - const: qcom,ipq5210
-
- - items:
- - enum:
- - qcom,ipq5332-ap-mi01.2
- - qcom,ipq5332-ap-mi01.3
- - qcom,ipq5332-ap-mi01.6
- - qcom,ipq5332-ap-mi01.9
- - const: qcom,ipq5332
-
- - items:
- - enum:
- - qcom,ipq5424-rdp466
- - const: qcom,ipq5424
-
- - items:
- - enum:
- - mikrotik,rb3011
- - qcom,ipq8064-ap148
- - const: qcom,ipq8064
-
- - items:
- - enum:
- - qcom,ipq8074-hk01
- - qcom,ipq8074-hk10-c1
- - qcom,ipq8074-hk10-c2
- - const: qcom,ipq8074
-
- - items:
- - enum:
- - qcom,ipq9574-ap-al02-c2
- - qcom,ipq9574-ap-al02-c2-emmc
- - qcom,ipq9574-ap-al02-c6
- - qcom,ipq9574-ap-al02-c7
- - qcom,ipq9574-ap-al02-c7-emmc
- - qcom,ipq9574-ap-al02-c8
- - qcom,ipq9574-ap-al02-c9
- - const: qcom,ipq9574
-
- - items:
- - enum:
- - qcom,ipq9650-rdp488
- - const: qcom,ipq9650
-
- - items:
- - enum:
- - qcom,kaanapali-mtp
- - qcom,kaanapali-qrd
- - const: qcom,kaanapali
-
- - description: Sierra Wireless MangOH Green with WP8548 Module
- items:
- - const: swir,mangoh-green-wp8548
- - const: swir,wp8548
- - const: qcom,mdm9615
-
- description: Qualcomm Technologies, Inc. Robotics RB1
items:
- enum:
@@ -403,6 +409,20 @@ properties:
- thundercomm,rubikpi3
- const: qcom,qcm6490
+ - items:
+ - enum:
+ - qcom,qcs404-evb-1000
+ - qcom,qcs404-evb-4000
+ - const: qcom,qcs404-evb
+ - const: qcom,qcs404
+
+ - items:
+ - enum:
+ - arduino,monza
+ - qcom,monaco-evk
+ - qcom,qcs8300-ride
+ - const: qcom,qcs8300
+
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
items:
- enum:
@@ -416,6 +436,31 @@ properties:
- qcom,qru1000-idp
- const: qcom,qru1000
+ - items:
+ - enum:
+ - qcom,sa8155p-adp
+ - const: qcom,sa8155p
+
+ - items:
+ - enum:
+ - qcom,sa8295p-adp
+ - qcom,sa8540p-ride
+ - const: qcom,sa8540p
+
+ - items:
+ - enum:
+ - qcom,sa8775p-ride
+ - qcom,sa8775p-ride-r3
+ - const: qcom,sa8775p
+
+ - items:
+ - enum:
+ - qcom,lemans-evk
+ - qcom,qcs9100-ride
+ - qcom,qcs9100-ride-r3
+ - const: qcom,qcs9100
+ - const: qcom,sa8775p
+
- description: Qualcomm AR2 Gen1 platform
items:
- enum:
@@ -828,14 +873,6 @@ properties:
- const: google,zombie-sku514
- const: qcom,sc7280
- - description: Xiaomi Poco F1
- items:
- - enum:
- - xiaomi,beryllium-ebbg
- - xiaomi,beryllium-tianma
- - const: xiaomi,beryllium
- - const: qcom,sdm845
-
- items:
- enum:
- lenovo,flex-5g
@@ -853,6 +890,11 @@ properties:
- qcom,sc8280xp-qrd
- const: qcom,sc8280xp
+ - items:
+ - enum:
+ - inforce,ifc6560
+ - const: qcom,sda660
+
- items:
- enum:
- lenovo,tbx605f
@@ -867,11 +909,6 @@ properties:
- sony,voyager-row
- const: qcom,sdm630
- - items:
- - enum:
- - inforce,ifc6560
- - const: qcom,sda660
-
- items:
- enum:
- fairphone,fp3
@@ -899,74 +936,13 @@ properties:
- const: google,bonito
- const: qcom,sdm670
- - items:
- - enum:
- - qcom,sdx55-mtp
- - qcom,sdx55-telit-fn980-tlb
- - qcom,sdx55-t55
- - const: qcom,sdx55
-
- - items:
- - enum:
- - qcom,sdx65-mtp
- - const: qcom,sdx65
-
- - items:
- - enum:
- - qcom,sdx75-idp
- - const: qcom,sdx75
-
- - items:
- - enum:
- - qcom,ipq6018-cp01
- - qcom,ipq6018-cp01-c1
- - const: qcom,ipq6018
-
- - items:
- - enum:
- - qcom,qcs404-evb-1000
- - qcom,qcs404-evb-4000
- - const: qcom,qcs404-evb
- - const: qcom,qcs404
-
- - items:
- - enum:
- - arduino,monza
- - qcom,monaco-evk
- - qcom,qcs8300-ride
- - const: qcom,qcs8300
-
- - items:
- - enum:
- - qcom,qcs615-ride
- - qcom,talos-evk
- - const: qcom,qcs615
- - const: qcom,sm6150
-
- - items:
- - enum:
- - qcom,sa8155p-adp
- - const: qcom,sa8155p
-
- - items:
- - enum:
- - qcom,sa8295p-adp
- - qcom,sa8540p-ride
- - const: qcom,sa8540p
-
- - items:
- - enum:
- - qcom,sa8775p-ride
- - qcom,sa8775p-ride-r3
- - const: qcom,sa8775p
-
- - items:
+ - description: Xiaomi Poco F1
+ items:
- enum:
- - qcom,lemans-evk
- - qcom,qcs9100-ride
- - qcom,qcs9100-ride-r3
- - const: qcom,qcs9100
- - const: qcom,sa8775p
+ - xiaomi,beryllium-ebbg
+ - xiaomi,beryllium-tianma
+ - const: xiaomi,beryllium
+ - const: qcom,sdm845
- items:
- enum:
@@ -989,6 +965,23 @@ properties:
- xiaomi,polaris
- const: qcom,sdm845
+ - items:
+ - enum:
+ - qcom,sdx55-mtp
+ - qcom,sdx55-telit-fn980-tlb
+ - qcom,sdx55-t55
+ - const: qcom,sdx55
+
+ - items:
+ - enum:
+ - qcom,sdx65-mtp
+ - const: qcom,sdx65
+
+ - items:
+ - enum:
+ - qcom,sdx75-idp
+ - const: qcom,sdx75
+
- items:
- enum:
- oneplus,billie2
@@ -1024,6 +1017,13 @@ properties:
- xiaomi,willow
- const: qcom,sm6125
+ - items:
+ - enum:
+ - qcom,qcs615-ride
+ - qcom,talos-evk
+ - const: qcom,qcs615
+ - const: qcom,sm6150
+
- items:
- enum:
- sony,pdx213
---
base-commit: 4e5dfb7c84012007c3c7061126491bbc92d71bf1
change-id: 20260623-reorg_qcom_binding-0648bdef8db8
Best regards,
--
Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
^ permalink raw reply related
* Re: [PATCH v6 3/6 RESEND] dt-bindings: mfd: motorola-cpcap: convert to DT schema
From: sashiko-bot @ 2026-06-25 10:34 UTC (permalink / raw)
To: Svyatoslav Ryhel
Cc: dmitry.torokhov, linux-input, lee, linux-leds, robh, conor+dt,
devicetree
In-Reply-To: <20260625081812.33474-4-clamor95@gmail.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] The YAML schema introduces a `ports` wrapper node for the `audio-codec`, which conflicts with the original TXT binding and existing device trees that define `port@X` directly as children.
- [Medium] The schema explicitly expects the power button subnode to be named exactly `key-power`, but the in-tree device tree uses `button`.
- [Medium] The `spi-cs-high` property, which is physically required by the hardware and was explicitly listed as required in the legacy text binding, has been omitted from the `required` list in the YAML schema.
--
commit 30a40e2d4eb937fd9bbca306ed8246e061a54ab4
Author: Svyatoslav Ryhel <clamor95@gmail.com>
dt-bindings: mfd: motorola-cpcap: convert to DT schema
Convert devicetree bindings for the Motorola CPCAP MFD from TXT to YAML.
> diff --git a/Documentation/devicetree/bindings/mfd/motorola,cpcap.yaml b/Documentation/devicetree/bindings/mfd/motorola,cpcap.yaml
> new file mode 100644
> index 0000000000000..76705ea56805a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/motorola,cpcap.yaml
[ ... ]
> + audio-codec:
> + type: object
> + additionalProperties: false
> +
> + properties:
[ ... ]
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
[Severity: Medium]
Will this break validation for existing device trees?
The legacy text binding example shows port@0 and port@1 directly under the
audio-codec node, but this schema requires them to be wrapped in a ports
node. Because additionalProperties is set to false on audio-codec, direct
port@X nodes in existing device trees will be rejected.
[ ... ]
> + charger:
> + $ref: /schemas/power/supply/cpcap-charger.yaml#
> +
> + key-power:
> + $ref: /schemas/input/motorola,cpcap-pwrbutton.yaml#
[Severity: Medium]
Is it intentional to restrict the subnode name strictly to key-power?
Existing in-tree device trees use button for this node. By strictly matching
key-power, existing configurations will be rejected as an undocumented
property during schema validation.
[ ... ]
> +patternProperties:
> + "^led(-[a-z]+)?$":
> + $ref: /schemas/leds/motorola,cpcap-leds.yaml#
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-controller
> + - "#interrupt-cells"
> + - spi-max-frequency
[Severity: Medium]
Does this schema incorrectly omit spi-cs-high from the required list?
The legacy text binding explicitly listed spi-cs-high as a required property.
Without it, incomplete device trees lacking this hardware-critical property
will incorrectly pass validation.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260625081812.33474-1-clamor95@gmail.com?part=3
^ permalink raw reply
* [PATCH v6 0/3] pwm: add support for Andes platform
From: Ben Zong-You Xie via B4 Relay @ 2026-06-25 10:35 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-pwm, devicetree, linux-kernel, Ben Zong-You Xie
The ATCPIT100 is a set of compact multi-function timers, which can be
a simple timer or PWM, or a combination of the timer and the PWM. This
IP block is a core component of the Andes AE350 platform, which serves
as a reference architecture for SoC designs. The QiLai SoC also
integrates this controller.
This device driver was previously part of the Linux Kernel, and the
compatible was its IP name "andestech,atcpit100". However, the driver
and its binding were removed due to the deprecation of the NDS32
architecture [1]. Although Andes now dedicates our effort on RISC-V,
ATCPIT100 is still one of our peripheral IPs, and that's why we are
re-introducing it now. Since only using the IP block name as the
compatible is forbidden now, change the compatible to
"andestech,ae350-pwm" and "andestech,qilai-pwm".
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=aec499c75cf8e0b599be4d559e6922b613085f8f
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
Changes in v6:
- Rebased on ukleinek/pwm/for-next.
- (2/3)
- Round a too-large period or duty cycle down to the largest achievable
value, and emulate 0%/100% relative duty cycles by parking the channel,
instead of erroring out. (Uwe)
- Choose the period from the requested period alone, so it no longer
depends on the requested duty cycle. (Uwe)
- Convert the period to ticks and compute the high/low phases in the tick
domain to avoid rounding errors. (Uwe)
- Reconstruct the period in .get_state() with a single DIV_ROUND_UP_ULL()
over both phases, shared by both polarities, and read the control
register with FIELD_GET(). (Uwe)
- Set an out-of-range clock rate to 0 so that source cannot be selected,
and name both rates in the "no usable clock" error message. (Uwe)
- Rename to_andes_pwm() to andes_pwm_from_chip(). (Uwe)
- Capitalize error messages. (Uwe)
- Tidy up the in-function comment and the limitations list.
- Link to v5: https://patch.msgid.link/20260330-andes-pwm-v5-0-01c59a659d2c@andestech.com
Changes in v5:
- Rebased on ukleinek/pwm/for-next
- (1/3)
- Added Rob's reviewed-by tag.
- Link to v4: https://patch.msgid.link/20260204-andes-pwm-v4-0-67016bb13555@andestech.com
Changes in v4:
- Updated cover letter title and its commit message.
- (1/3)
- Updated the compatibles and the binding file name.
- Added the description to the binding.
- Corrected device register size.
- Dropped the changes to the MAINTAINERS file.
- (2/3)
- Updated the driver name.
- Made the driver support inversed polarity.
- Changed the clock selection algorithm.
- Made the configuration depend on ARCH_ANDES, instead of RISCV. (Krzysztof)
- Dropped the changes to the MAINTAINERS file.
- (3/3) (new)
- Collected all changes to the MAINTAINERS file into a single patch.
- Link to v3: https://patch.msgid.link/20250123193534.874256-1-ben717@andestech.com
Changes in v3:
- (1/2):
- modified the compatible string. (Krzysztof)
- (2/2):
- added a check for the clock rate to prevent the overflow warning.
(kernel test robot)
- removed the unnecessary check in .apply(). (kernel test robot)
- Link to v2: https://patch.msgid.link/20241202060147.1271264-1-ben717@andestech.com
Changes in v2:
- (1/2):
- changed "title" in the yaml file.
- removed vendor-specific property, and added clocks property.
- (2/2):
- added a description for hardware limitations. (Uwe)
- switched the clock parent depending on the requested setting
instead of statically configuring the clock source in DT. (Uwe)
- Link to v1: https://patch.msgid.link/20241028102721.1961289-1-ben717@andestech.com
---
Ben Zong-You Xie (3):
dt-bindings: pwm: add support for AE350 PWM controller
pwm: add Andes PWM driver support
MAINTAINERS: add an entry for Andes PWM driver
.../bindings/pwm/andestech,ae350-pwm.yaml | 61 ++++
MAINTAINERS | 6 +
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-andes.c | 343 +++++++++++++++++++++
5 files changed, 421 insertions(+)
---
base-commit: 898ab0f30e008e411ce93ddf81c4099abd9d4e46
change-id: 20260204-andes-pwm-10ea6611c3cf
Best regards,
--
Ben Zong-You Xie <ben717@andestech.com>
^ permalink raw reply
* [PATCH v6 1/3] dt-bindings: pwm: add support for AE350 PWM controller
From: Ben Zong-You Xie via B4 Relay @ 2026-06-25 10:35 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-pwm, devicetree, linux-kernel, Ben Zong-You Xie
In-Reply-To: <20260625-andes-pwm-v6-0-3aef11711017@andestech.com>
From: Ben Zong-You Xie <ben717@andestech.com>
The ATCPIT100 is a set of compact multi-function timers, which can be
used as pulse width modulators (PWM) as well as simple timers.
ATCPIT100 supports up to 4 PIT channels, and each PIT channel may be
configured as a simple timer or PWM, or a combination of the timer and
the PWM. This IP block is a core component of the Andes AE350 platform,
which serves as a reference architecture for SoC designs. The QiLai SoC
also integrates this controller.
The binding introduces the following compatible strings:
- "andestech,qilai-pwm": For the implementation integrated into the
Andes QiLai SoC.
- "andestech,ae350-pwm": As a fallback compatible string representing
the base IP design used across the AE350 platform architecture.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
.../bindings/pwm/andestech,ae350-pwm.yaml | 61 ++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml b/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml
new file mode 100644
index 000000000000..287f3c62965f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/andestech,ae350-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes PWM controller on AE350 platform
+
+description:
+ This controller has 4 channels and two clock sources. Each channel can
+ switch the clock source by programming the corresponding register.
+
+maintainers:
+ - Ben Zong-You Xie <ben717@andestech.com>
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - andestech,qilai-pwm
+ - const: andestech,ae350-pwm
+ - const: andestech,ae350-pwm
+
+ reg:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+
+ clocks:
+ items:
+ - description: APB bus clock
+ - description: External clock
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: extclk
+
+required:
+ - compatible
+ - reg
+ - "#pwm-cells"
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pwm@f0400000 {
+ compatible = "andestech,ae350-pwm";
+ reg = <0xf0400000 0x100000>;
+ #pwm-cells = <3>;
+ clocks = <&pclk>, <&extclk>;
+ clock-names = "pclk", "extclk";
+ };
--
2.34.1
^ permalink raw reply related
* [PATCH v6 2/3] pwm: add Andes PWM driver support
From: Ben Zong-You Xie via B4 Relay @ 2026-06-25 10:36 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-pwm, devicetree, linux-kernel, Ben Zong-You Xie
In-Reply-To: <20260625-andes-pwm-v6-0-3aef11711017@andestech.com>
From: Ben Zong-You Xie <ben717@andestech.com>
Add a driver for the PWM controller found in Andes AE350 platforms and
QiLai SoCs.
The Andes PWM controller features:
- 4 independent channels.
- Dual clock source support (APB clock and external clock) to provide
a flexible range of frequencies.
- Support for normal and inversed polarity.
The driver implements the .apply() and .get_state() callbacks. Since the
clock source of each channel can be selected by programming the
register, clock selection logic is implemented to prioritize the
external clock to maximize the supported period range, falling back to
the APB clock for higher frequency requirements.
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
drivers/pwm/Kconfig | 10 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-andes.c | 343 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 354 insertions(+)
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index e8886a9b64d9..52dee4b7f081 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -73,6 +73,16 @@ config PWM_AIROHA
To compile this driver as a module, choose M here: the module
will be called pwm-airoha.
+config PWM_ANDES
+ tristate "Andes PWM support"
+ depends on ARCH_ANDES || COMPILE_TEST
+ help
+ Generic PWM framework driver for Andes platform, such as QiLai SoC
+ and AE350 platform.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-andes.
+
config PWM_APPLE
tristate "Apple SoC PWM support"
depends on ARCH_APPLE || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 5630a521a7cf..c92369ee251d 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
obj-$(CONFIG_PWM_ADP5585) += pwm-adp5585.o
obj-$(CONFIG_PWM_AIROHA) += pwm-airoha.o
+obj-$(CONFIG_PWM_ANDES) += pwm-andes.o
obj-$(CONFIG_PWM_APPLE) += pwm-apple.o
obj-$(CONFIG_PWM_ARGON_FAN_HAT) += pwm-argon-fan-hat.o
obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
diff --git a/drivers/pwm/pwm-andes.c b/drivers/pwm/pwm-andes.c
new file mode 100644
index 000000000000..580e673d2cff
--- /dev/null
+++ b/drivers/pwm/pwm-andes.c
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Andes PWM, used in Andes AE350 platform and QiLai SoC
+ *
+ * Copyright (C) 2026 Andes Technology Corporation.
+ *
+ * Limitations:
+ * - When disabling a channel, the current period is not completed and the
+ * output is driven to the PARK level (low when ANDES_PWM_CH_CTRL_PARK is
+ * clear, high when it is set).
+ * - The current period will be completed first if reconfiguring.
+ * - Further, if the reconfiguration changes the clock source, the output will
+ * not be the old one nor the new one. And the output will be the new one
+ * after writing to the reload register.
+ * - The hardware cannot run a 0% or 100% relative duty cycle; the driver
+ * emulates these by disabling the channel and parking the output at the
+ * constant level.
+ * - A period or duty cycle larger than the selected clock can represent is
+ * rounded down to the largest achievable value rather than rejected.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/math64.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
+#include <linux/time.h>
+#include <linux/types.h>
+
+#define ANDES_PWM_CH_ENABLE 0x1C
+#define ANDES_PWM_CH_ENABLE_PWM(ch) BIT(3 + (4 * (ch)))
+
+#define ANDES_PWM_CH_CTRL(ch) (0x20 + (0x10 * (ch)))
+#define ANDES_PWM_CH_CTRL_MODE_PWM BIT(2)
+#define ANDES_PWM_CH_CTRL_CLK BIT(3)
+#define ANDES_PWM_CH_CTRL_PARK BIT(4)
+#define ANDES_PWM_CH_CTRL_MASK GENMASK(4, 0)
+
+#define ANDES_PWM_CH_RELOAD(ch) (0x24 + (0x10 * (ch)))
+#define ANDES_PWM_CH_RELOAD_HIGH GENMASK(31, 16)
+#define ANDES_PWM_CH_RELOAD_LOW GENMASK(15, 0)
+
+#define ANDES_PWM_CH_COUNTER(ch) (0x28 + (0x10 * (ch)))
+
+#define ANDES_PWM_CH_MAX 4
+#define ANDES_PWM_CYCLE_MIN 1
+#define ANDES_PWM_CYCLE_MAX 0x10000
+
+struct andes_pwm {
+ struct regmap *regmap;
+ struct clk *pclk;
+ struct clk *extclk;
+ unsigned int pclk_rate;
+ unsigned int extclk_rate;
+};
+
+static const struct regmap_config andes_pwm_regmap_config = {
+ .name = "andes_pwm",
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .pad_bits = 0,
+ .max_register = ANDES_PWM_CH_COUNTER(ANDES_PWM_CH_MAX - 1),
+ .cache_type = REGCACHE_NONE,
+};
+
+static inline struct andes_pwm *andes_pwm_from_chip(struct pwm_chip *chip)
+{
+ return pwmchip_get_drvdata(chip);
+}
+
+static int andes_pwm_enable(struct pwm_chip *chip, unsigned int channel,
+ bool enable)
+{
+ struct andes_pwm *ap = andes_pwm_from_chip(chip);
+
+ return regmap_assign_bits(ap->regmap, ANDES_PWM_CH_ENABLE,
+ ANDES_PWM_CH_ENABLE_PWM(channel), enable);
+}
+
+/*
+ * Hold the output at a constant level by parking the disabled channel. A
+ * disabled channel drives its output to the PARK level (low when @high is
+ * false, high when @high is true), which is used to emulate a 0% or 100%
+ * relative duty cycle.
+ */
+static int andes_pwm_park(struct pwm_chip *chip, unsigned int channel,
+ bool high)
+{
+ struct andes_pwm *ap = andes_pwm_from_chip(chip);
+
+ regmap_assign_bits(ap->regmap, ANDES_PWM_CH_CTRL(channel),
+ ANDES_PWM_CH_CTRL_PARK, high);
+
+ return andes_pwm_enable(chip, channel, false);
+}
+
+static int andes_pwm_config(struct pwm_chip *chip, unsigned int channel,
+ const struct pwm_state *state)
+{
+ struct andes_pwm *ap = andes_pwm_from_chip(chip);
+ unsigned int clk_rate = ap->extclk_rate;
+ unsigned int ctrl = ANDES_PWM_CH_CTRL_MODE_PWM;
+ bool use_pclk = false;
+ u64 high_cycles;
+ u64 low_cycles;
+ u64 period_cycles;
+ u64 duty_cycles;
+ u32 reload;
+
+ /*
+ * Reload register for PWM mode:
+ *
+ * 31 : 16 15 : 0
+ * PWM16_Hi | PWM16_Lo
+ *
+ * The high duration is (PWM16_Hi + 1) cycles and the low duration is
+ * (PWM16_Lo + 1) cycles, so each phase spans ANDES_PWM_CYCLE_MIN to
+ * ANDES_PWM_CYCLE_MAX cycles. The hardware period (their sum) can reach
+ * 2 * ANDES_PWM_CYCLE_MAX cycles, but the PWM core requires the period
+ * to be chosen from the requested period alone, independent of the duty
+ * cycle. That holds only while both phases stay within
+ * ANDES_PWM_CYCLE_MAX for every duty split, so the usable period is
+ * capped at ANDES_PWM_CYCLE_MAX + ANDES_PWM_CYCLE_MIN cycles.
+ *
+ * The controller has two clock sources, the APB clock and an external
+ * clock. Since the external clock frequency must be slower than the APB
+ * clock, it is tried first for its wider period range; the APB clock is
+ * used only when the external clock is too fast to represent the period
+ * (it resolves fewer than two cycles) or is absent.
+ */
+ period_cycles = mul_u64_u64_div_u64(clk_rate, state->period,
+ NSEC_PER_SEC);
+ if (period_cycles < 2 * ANDES_PWM_CYCLE_MIN) {
+ use_pclk = true;
+ clk_rate = ap->pclk_rate;
+ period_cycles = mul_u64_u64_div_u64(clk_rate, state->period,
+ NSEC_PER_SEC);
+ if (period_cycles < 2 * ANDES_PWM_CYCLE_MIN)
+ return -EINVAL;
+ }
+
+ /*
+ * Round the period down to the largest value representable for every
+ * duty cycle, so the chosen period depends on the requested period
+ * alone. With both phases capped at ANDES_PWM_CYCLE_MAX, that bound is
+ * ANDES_PWM_CYCLE_MAX + ANDES_PWM_CYCLE_MIN cycles.
+ */
+ period_cycles = min_t(u64, period_cycles,
+ ANDES_PWM_CYCLE_MAX + ANDES_PWM_CYCLE_MIN);
+
+ /* The duty cycle cannot exceed the (possibly clamped) period. */
+ duty_cycles = mul_u64_u64_div_u64(clk_rate, state->duty_cycle,
+ NSEC_PER_SEC);
+ duty_cycles = min_t(u64, duty_cycles, period_cycles);
+ if (state->polarity == PWM_POLARITY_INVERSED) {
+ low_cycles = duty_cycles;
+ high_cycles = period_cycles - low_cycles;
+ } else {
+ high_cycles = duty_cycles;
+ low_cycles = period_cycles - high_cycles;
+ }
+
+ /*
+ * A zero-length phase means a 0% or 100% relative duty cycle, which the
+ * hardware cannot run. Emit the matching constant level by parking the
+ * channel: high_cycles == 0 stays low, low_cycles == 0 stays high.
+ */
+ if (!high_cycles)
+ return andes_pwm_park(chip, channel, false);
+ if (!low_cycles)
+ return andes_pwm_park(chip, channel, true);
+
+ /*
+ * If changing the clock source here, the output will not be the old one
+ * nor the new one. And the output will be the new one after writing to
+ * the reload register.
+ */
+ ctrl |= use_pclk ? ANDES_PWM_CH_CTRL_CLK : 0;
+ ctrl |= (state->polarity == PWM_POLARITY_INVERSED) ?
+ ANDES_PWM_CH_CTRL_PARK : 0;
+ regmap_update_bits(ap->regmap, ANDES_PWM_CH_CTRL(channel),
+ ANDES_PWM_CH_CTRL_MASK, ctrl);
+ reload = FIELD_PREP(ANDES_PWM_CH_RELOAD_HIGH, high_cycles - 1) |
+ FIELD_PREP(ANDES_PWM_CH_RELOAD_LOW, low_cycles - 1);
+ regmap_write(ap->regmap, ANDES_PWM_CH_RELOAD(channel), reload);
+ return andes_pwm_enable(chip, channel, true);
+}
+
+static int andes_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ unsigned int channel = pwm->hwpwm;
+
+ if (!state->enabled) {
+ if (pwm->state.enabled)
+ andes_pwm_enable(chip, channel, false);
+
+ return 0;
+ }
+
+ return andes_pwm_config(chip, channel, state);
+}
+
+static int andes_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct andes_pwm *ap = andes_pwm_from_chip(chip);
+ unsigned int channel = pwm->hwpwm;
+ unsigned int ctrl;
+ unsigned int clk_rate;
+ unsigned int reload;
+ u64 high_cycles;
+ u64 low_cycles;
+
+ regmap_read(ap->regmap, ANDES_PWM_CH_CTRL(channel), &ctrl);
+ clk_rate = FIELD_GET(ANDES_PWM_CH_CTRL_CLK, ctrl) ? ap->pclk_rate
+ : ap->extclk_rate;
+ if (!clk_rate) {
+ /*
+ * The selected clock source is unavailable, so the channel
+ * cannot be running; report it as disabled and avoid the
+ * division by zero below.
+ */
+ state->enabled = false;
+ state->period = 0;
+ state->duty_cycle = 0;
+ return 0;
+ }
+
+ state->enabled = regmap_test_bits(ap->regmap, ANDES_PWM_CH_ENABLE,
+ ANDES_PWM_CH_ENABLE_PWM(channel)) > 0;
+ state->polarity = FIELD_GET(ANDES_PWM_CH_CTRL_PARK, ctrl) ?
+ PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
+ regmap_read(ap->regmap, ANDES_PWM_CH_RELOAD(channel), &reload);
+ high_cycles = FIELD_GET(ANDES_PWM_CH_RELOAD_HIGH, reload) + 1;
+ low_cycles = FIELD_GET(ANDES_PWM_CH_RELOAD_LOW, reload) + 1;
+
+ /*
+ * high_cycles and low_cycles are each at most ANDES_PWM_CYCLE_MAX
+ * (0x10000, 17 bits) and NSEC_PER_SEC is below 2^30, so the products
+ * below are safe from 64-bit overflow.
+ */
+ if (state->polarity == PWM_POLARITY_INVERSED)
+ state->duty_cycle = DIV_ROUND_UP_ULL(low_cycles * NSEC_PER_SEC,
+ clk_rate);
+ else
+ state->duty_cycle = DIV_ROUND_UP_ULL(high_cycles * NSEC_PER_SEC,
+ clk_rate);
+
+ state->period = DIV_ROUND_UP_ULL((high_cycles + low_cycles) *
+ NSEC_PER_SEC, clk_rate);
+
+ return 0;
+}
+
+static const struct pwm_ops andes_pwm_ops = {
+ .apply = andes_pwm_apply,
+ .get_state = andes_pwm_get_state,
+};
+
+static int andes_pwm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pwm_chip *chip;
+ struct andes_pwm *ap;
+ void __iomem *reg_base;
+ unsigned long pclk_rate;
+ unsigned long extclk_rate;
+ int ret;
+
+ chip = devm_pwmchip_alloc(dev, ANDES_PWM_CH_MAX, sizeof(*ap));
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
+
+ ap = andes_pwm_from_chip(chip);
+ reg_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg_base))
+ return dev_err_probe(dev, PTR_ERR(reg_base),
+ "Failed to map I/O space\n");
+
+ ap->pclk = devm_clk_get_enabled(dev, "pclk");
+ if (IS_ERR(ap->pclk))
+ return dev_err_probe(dev, PTR_ERR(ap->pclk),
+ "Failed to get APB clock\n");
+
+ ap->extclk = devm_clk_get_optional_enabled(dev, "extclk");
+ if (IS_ERR(ap->extclk))
+ return dev_err_probe(dev, PTR_ERR(ap->extclk),
+ "Failed to get external clock\n");
+
+ /*
+ * If the clock rate is greater than 10^9, there may be an overflow when
+ * calculating the cycles in andes_pwm_config()
+ */
+ pclk_rate = clk_get_rate(ap->pclk);
+ extclk_rate = clk_get_rate(ap->extclk);
+
+ ap->pclk_rate = pclk_rate > NSEC_PER_SEC ? 0 : pclk_rate;
+ ap->extclk_rate = extclk_rate > NSEC_PER_SEC ? 0 : extclk_rate;
+
+ if (!ap->pclk_rate && !ap->extclk_rate)
+ return dev_err_probe(dev, -EINVAL,
+ "No usable clock: pclk %lu Hz, extclk %lu Hz\n",
+ pclk_rate, extclk_rate);
+
+ ap->regmap = devm_regmap_init_mmio(dev, reg_base,
+ &andes_pwm_regmap_config);
+ if (IS_ERR(ap->regmap))
+ return dev_err_probe(dev, PTR_ERR(ap->regmap),
+ "Failed to initialize regmap\n");
+
+ chip->ops = &andes_pwm_ops;
+ ret = devm_pwmchip_add(dev, chip);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
+
+ return 0;
+}
+
+static const struct of_device_id andes_pwm_of_match[] = {
+ { .compatible = "andestech,ae350-pwm" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, andes_pwm_of_match);
+
+static struct platform_driver andes_pwm_driver = {
+ .driver = {
+ .name = "andes_pwm",
+ .of_match_table = andes_pwm_of_match,
+ },
+ .probe = andes_pwm_probe,
+};
+module_platform_driver(andes_pwm_driver);
+
+MODULE_AUTHOR("Ben Zong-You Xie <ben717@andestech.com>");
+MODULE_DESCRIPTION("Andes PWM driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related
* [PATCH v6 3/3] MAINTAINERS: add an entry for Andes PWM driver
From: Ben Zong-You Xie via B4 Relay @ 2026-06-25 10:36 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-pwm, devicetree, linux-kernel, Ben Zong-You Xie
In-Reply-To: <20260625-andes-pwm-v6-0-3aef11711017@andestech.com>
From: Ben Zong-You Xie <ben717@andestech.com>
Add an entry for the Andes PWM driver to the MAINTAINERS file.
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2fb1c75afd16..2461683a5bbb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1874,6 +1874,12 @@ S: Supported
F: Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml
F: drivers/spi/spi-atcspi200.c
+ANDES PWM DRIVER
+M: Ben Zong-You Xie <ben717@andestech.com>
+S: Supported
+F: Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml
+F: drivers/pwm/pwm-andes.c
+
ANDROID DRIVERS
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
M: Arve Hjønnevåg <arve@android.com>
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 1/2] arm64: dts: qcom: sm8250-xiaomi-elish: Add pm8008 PMIC
From: Xin Xu @ 2026-06-25 10:37 UTC (permalink / raw)
To: konrad.dybcio
Cc: andersson, devicetree, konradybcio, linux-arm-msm, linux-kernel,
xxsemail
In-Reply-To: <07fd4bcb-f55f-4856-9b93-7f4569a27b7f@oss.qualcomm.com>
On Wed, 2026-06-24 at 13:57 +0200, Konrad Dybcio wrote:
> On 6/22/26 8:46 PM, Xin Xu wrote:
> > Add the pm8008 PMIC node on i2c15 with seven LDOs,
> > using GPIO84 as interrupt and GPIO76 as reset.
> >
> > Signed-off-by: Xin Xu <xxsemail@qq.com>
> > ---
>
> [...]
>
> > + pm8008_default: pm8008-default-state {
> > + int-pins {
> > + pins = "gpio84";
> > + function = "gpio";
> > + bias-disable;
> > + drive-strength = <2>;
> > + input-enable;
> > + };
> > +
> > + reset-pins {
> > + pins = "gpio76";
> > + function = "gpio";
> > + bias-pull-up;
> > + drive-strength = <2>;
>
> nit: bias properties after drive-strength (I now noticed that 8250
> dtsi
> has it ""wrong"", we'll mass-touch it up once we have a tool for
> that..
> sorry for the trouble)
>
> otherwise
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Konrad
On Wed, 2026-06-24 at 14:00 +0200, Konrad Dybcio wrote:
> On 6/22/26 8:46 PM, Xin Xu wrote:
> > Add the pm8008 PMIC node on i2c15 with seven LDOs,
> > using GPIO84 as interrupt and GPIO76 as reset.
> >
> > Signed-off-by: Xin Xu <xxsemail@qq.com>
> > ---
>
> [...]
>
>
> > + pm8008_default: pm8008-default-state {
> > + int-pins {
> > + pins = "gpio84";
> > + function = "gpio";
> > + bias-disable;
> > + drive-strength = <2>;
> > + input-enable;
> > + };
>
> arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dtb: pinctrl@f100000
> (qcom,sm8250-pinctrl): pm8008-default-state: 'oneOf' conditional
> failed, one must be fixed:
> 'function' is a required property
> 'pins' is a required property
> Unevaluated properties are not allowed ('int-pins', 'reset-
> pins' were unexpected)
> False schema does not allow True
> from schema $id:
> http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml
>
> Please drop input-enable, it's not a thing on TLMM pins
>
> Konrad
Thank you for the review and the Reviewed-by tag!
I will fix these coding style issues (splitting the pinctrl nodes,
dropping input-enable, and reordering the bias properties) in the next
version.
Best regards,
Xin Xu
^ permalink raw reply
* Re: [PATCH v6 1/3] dt-bindings: pwm: add support for AE350 PWM controller
From: sashiko-bot @ 2026-06-25 10:45 UTC (permalink / raw)
To: Ben Zong-You Xie via B4 Relay; +Cc: devicetree, conor+dt, robh
In-Reply-To: <20260625-andes-pwm-v6-1-3aef11711017@andestech.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The DT binding defines a specific software use-case (PWM) rather than holistically describing the underlying multi-function hardware block (ATCPIT100), omitting inherent hardware properties like `interrupts`.
--
commit efdd46b6c3b84eb1768cdcc54800ffa3c62afeef
Author: Ben Zong-You Xie <ben717@andestech.com>
dt-bindings: pwm: add support for AE350 PWM controller
This commit adds the device tree binding for the ATCPIT100 PWM controller
used in the Andes AE350 platform and QiLai SoC.
> diff --git a/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml b/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/andestech,ae350-pwm.yaml
[ ... ]
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - andestech,qilai-pwm
> + - const: andestech,ae350-pwm
> + - const: andestech,ae350-pwm
[ ... ]
> +required:
> + - compatible
> + - reg
> + - "#pwm-cells"
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
[Severity: Medium]
The commit message mentions that the ATCPIT100 block is a set of
multi-function timers that can be used as PWMs or simple timers. Does
this binding restrict the hardware description to only the PWM software
use-case?
Since unevaluatedProperties is set to false and the properties block omits
inherent hardware properties like interrupts, will dtbs_check fail if a
device tree author attempts to accurately describe the full ATCPIT100
multi-function hardware block by wiring its interrupt lines?
Would it be better to describe the complete hardware capabilities upfront,
such as timer functionality and interrupts, to prevent redesigns breaking
backward compatibility (like transitioning to an MFD or adding #timer-cells)
when timer support is needed later?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260625-andes-pwm-v6-0-3aef11711017@andestech.com?part=1
^ permalink raw reply
* Re: [PATCH v6 2/3] pwm: add Andes PWM driver support
From: sashiko-bot @ 2026-06-25 10:46 UTC (permalink / raw)
To: Ben Zong-You Xie via B4 Relay; +Cc: conor+dt, robh, devicetree
In-Reply-To: <20260625-andes-pwm-v6-2-3aef11711017@andestech.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The driver fails to update the hardware PARK level to the inactive state when disabling the PWM channel, leaving the output stuck ON or at the wrong polarity.
--
commit 6823cc7ba3d3233c8090db2e53dc0a9b52b74a25
Author: Ben Zong-You Xie <ben717@andestech.com>
pwm: add Andes PWM driver support
Add a driver for the PWM controller found in Andes AE350 platforms and
QiLai SoCs.
> diff --git a/drivers/pwm/pwm-andes.c b/drivers/pwm/pwm-andes.c
> new file mode 100644
> index 0000000000000..580e673d2cff0
> --- /dev/null
> +++ b/drivers/pwm/pwm-andes.c
[ ... ]
> +static int andes_pwm_config(struct pwm_chip *chip, unsigned int channel,
> + const struct pwm_state *state)
> +{
[ ... ]
> + /*
> + * A zero-length phase means a 0% or 100% relative duty cycle, which the
> + * hardware cannot run. Emit the matching constant level by parking the
> + * channel: high_cycles == 0 stays low, low_cycles == 0 stays high.
> + */
> + if (!high_cycles)
> + return andes_pwm_park(chip, channel, false);
> + if (!low_cycles)
> + return andes_pwm_park(chip, channel, true);
[Severity: High]
When configuring a 100 percent duty cycle, this code sets the PARK bit to the
active state to emulate the output. If the channel is subsequently disabled,
could the output remain stuck ON?
> +
> + /*
> + * If changing the clock source here, the output will not be the old one
[ ... ]
> +static int andes_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> + const struct pwm_state *state)
> +{
> + unsigned int channel = pwm->hwpwm;
> +
> + if (!state->enabled) {
> + if (pwm->state.enabled)
> + andes_pwm_enable(chip, channel, false);
> +
> + return 0;
> + }
[Severity: High]
Does this early return path disable the channel but fail to update the
hardware's PARK bit to reflect the inactive state of the current polarity?
If the PWM was previously configured to 100 percent duty cycle where the PARK
bit was set active, it appears bypassing the PARK bit configuration on the
disable path leaves the output driven at the active level.
Additionally, if the polarity changes while the channel is disabled, will the
hardware's inactive level fail to update?
> +
> + return andes_pwm_config(chip, channel, state);
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260625-andes-pwm-v6-0-3aef11711017@andestech.com?part=2
^ permalink raw reply
* [PATCH v19 0/7] coresight: ctcu: Enable byte-cntr function for TMC ETR
From: Jie Gan @ 2026-06-25 10:45 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Alexander Shishkin, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jie Gan, Bjorn Andersson,
Konrad Dybcio, Yuanfang Zhang, Mao Jinlong
Cc: coresight, linux-arm-kernel, linux-kernel, linux-arm-msm,
devicetree, Konrad Dybcio, Mike Leach, Krzysztof Kozlowski
The byte-cntr function provided by the CTCU device is used to count the
trace data entering the ETR. An interrupt is triggered if the data size
exceeds the threshold set in the BYTECNTRVAL register. The interrupt
handler counts the number of triggered interruptions.
Based on this concept, the irq_cnt can be used to determine whether
the etr_buf is full. The ETR device will be disabled when the active
etr_buf is nearly full or a timeout occurs. The nearly full buffer will
be switched to background after synced. A new buffer will be picked from
the etr_buf_list, then restart the ETR device.
The byte-cntr reading functions can access data from the synced and
deactivated buffer, transferring trace data from the etr_buf to userspace
without stopping the ETR device.
The byte-cntr read operation has integrated with the file node tmc_etr,
for example:
/dev/tmc_etr0
/dev/tmc_etr1
There are two scenarios for the tmc_etr file node with byte-cntr function:
1. BYTECNTRVAL register is configured and byte-cntr is enabled -> byte-cntr read
2. BYTECNTRVAL register is reset or byte-cntr is disabled -> original behavior
Shell commands to enable byte-cntr reading for etr0:
echo 1 > /sys/bus/coresight/devices/ctcu0/irq_enabled0
echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink
echo 1 > /sys/bus/coresight/devices/etm0/enable_source
cat /dev/tmc_etr0
Reset the BYTECNTR register for etr0:
echo 0 > /sys/bus/coresight/devices/ctcu0/irq_enabled0
---
Changes in v19:
1. coresight: tmc: add create/clean functions for etr_buf_list:
- Simplified the kernel-doc "Locking:" note on tmc_create_etr_buf_list()
and tmc_clean_etr_buf_list() to state only the required contract
(caller must guarantee exclusive access to drvdata->etr_buf_list),
dropping the over-specific call-path details.
- Lock the required code block in create/clean functions.
2. coresight: ctcu: enable byte-cntr for TMC ETR devices:
- Fixed a stale reading-state / double-free when irq_enabled was
cleared between prepare and unprepare: the byte-cntr read_unprepare
would return an error and tmc_read_unprepare_etr() would fall back
to the normal unprepare path, freeing drvdata->sysfs_buf while it
was still owned by the byte-cntr buffer list. irq_enabled_store()
now returns -EBUSY while byte_cntr_data->reading is set, so the flag
can no longer change mid-session, and tmc_read_unprepare_byte_cntr()
additionally guards on byte_cntr_data->reading.
- Moved enable_irq_wake()/disable_irq_wake() out of the
byte_cntr_data->spin_lock critical section in
tmc_read_prepare_byte_cntr()/tmc_read_unprepare_byte_cntr().
irq_set_irq_wake() may sleep on slow-bus irqchips, so it must not
be called under a raw spinlock. The threshold IRQ is already
disabled by the in-lock register write before disable_irq_wake() on
the unprepare path, so no wake event can race in the gap.
- Added a comment on the byte_cntr_sysfs_ops pointer documenting the
single-CTCU-instance-per-system assumption.
- Link to v18: https://lore.kernel.org/r/20260507-enable-byte-cntr-for-ctcu-v18-0-2b2d590463a3@oss.qualcomm.com
Changes in v18:
1. add a NULL check for the in_conns instance in patch 1.
2. fix a bug in patch 2: the tmc_alloc_etr_buf never return NULL and the
previous check for the return value is incorrect.
3. add more kernel_doc description for tmc_clean_etr_buf_list function
in patch 2
- Link to v17: https://lore.kernel.org/r/20260421-enable-byte-cntr-for-ctcu-v17-0-9cf36ff55fc0@oss.qualcomm.com
Changes in v17:
1. fix race issue during allocat buffer.
2. fix user after free issue observed when remove module.
- Link to v16: https://lore.kernel.org/r/20260323-enable-byte-cntr-for-ctcu-v16-0-7a413d211b8d@oss.qualcomm.com
Changes in v16:
1. Remove lock/unlock processes in patch "coresight: tmc: add create/clean
functions for etr_buf_list" because we are allocating/freeing memory.
- Link to v15: https://lore.kernel.org/r/20260313-enable-byte-cntr-for-ctcu-v15-0-1777f14ed319@oss.qualcomm.com
Changes in v15:
1. add lockdep_assert_held in patch "coresight: tmc: add create/clean
functions for etr_buf_list"
2. optimize tmc_clean_etr_buf_list function
3. optimize the patch "enable byte-cntr for TMC ETR devices" according
to Suzuki's comments
- call byte_cntr_sysfs_ops from etr_sysfs_ops
- optimize the lock usage in all functions
- remove the buf_node parameter in etr_drvdata, move it to
byte_cntr_data
- move the tmc_reset_sysfs_buf function to tmc-etr.c
- add a read flag to struct etr_buf_node to allow updating pos while
traversing etr_buf_list during data reads.
Link to v14: https://lore.kernel.org/r/20260309-enable-byte-cntr-for-ctcu-v14-0-c08823e5a8e6@oss.qualcomm.com
Changes in V14:
1. Drop the patch: integrate byte-cntr's sysfs_ops with tmc sysfs file_ops
2. Replace tmc_sysfs_ops with byte_cntr_sysfs_ops in byte_cntr_start
function and restore etr_sysfs_ops in byte_cntr_unprepare function.
3. Remove redundant checks in byte‑cntr functions.
Link to V13: https://lore.kernel.org/all/20260223-enable-byte-cntr-for-ctcu-v13-0-9cb44178b250@oss.qualcomm.com/
Changes in v13:
1. initilize the byte_cntr_data->raw_spin_lock before using.
2. replace kzalloc with kzalloc_obj.
Link to V12: https://lore.kernel.org/all/20260203-enable-byte-cntr-for-ctcu-v12-0-7bf81b86b70e@oss.qualcomm.com/
Changes in v12:
1. Add a new function for retrieving the CTCU's coresight_dev instead of
refactor the existing function.
Link to v11: https://lore.kernel.org/r/20260126-enable-byte-cntr-for-ctcu-v11-0-c0af66ba15cf@oss.qualcomm.com
Changes in v11:
1. Correct the description in patch1 for the function coresight_get_in_port.
2. Renaming the sysfs_ops to tmc_sysfs_ops per Suzuki's suggestion.
Link to v10: https://lore.kernel.org/r/20260122-enable-byte-cntr-for-ctcu-v10-0-22978e3c169f@oss.qualcomm.com
Changes in v10:
1. fix a free memory issue that is reported by robot for patch 2.
Link to v9: https://lore.kernel.org/r/20251224-enable-byte-cntr-for-ctcu-v9-0-886c4496fed4@oss.qualcomm.com
Changes in v9:
1. Drop the patch: add a new API to retrieve the helper device
2. Add a new patch to refactor the tmc_etr_get_catu_device function,
making it generic to support all types of helper devices associated with ETR.
3. Optimizing the code for creating irq_threshold sysfs node.
4. Remove interrupt-name property and obtain the IRQ based on the
in-port number.
Link to v8: https://lore.kernel.org/r/20251211-enable-byte-cntr-for-ctcu-v8-0-3e12ff313191@oss.qualcomm.com
Changes in V8:
1. Optimizing the patch 1 and patch 2 according to Suzuki's comments.
2. Combine the patch 3 and patch 4 together.
3. Rename the interrupt-name to prevent confusion, for example:etr0->etrirq0.
Link to V7 - https://lore.kernel.org/all/20251013-enable-byte-cntr-for-ctcu-v7-0-e1e8f41e15dd@oss.qualcomm.com/
Changes in V7:
1. rebased on tag next-20251010
2. updated info for sysfs node document
Link to V6 - https://lore.kernel.org/all/20250908-enable-byte-cntr-for-tmc-v6-0-1db9e621441a@oss.qualcomm.com/
Changes in V6:
1. rebased on next-20250905.
2. fixed the issue that the dtsi file has re-named from sa8775p.dtsi to
lemans.dtsi.
3. fixed some minor issues about comments.
Link to V5 - https://lore.kernel.org/all/20250812083731.549-1-jie.gan@oss.qualcomm.com/
Changes in V5:
1. Add Mike's reviewed-by tag for patchset 1,2,5.
2. Remove the function pointer added to helper_ops according to Mike's
comment, it also results the patchset has been removed.
3. Optimizing the paired create/clean functions for etr_buf_list.
4. Remove the unneeded parameter "reading" from the etr_buf_node.
Link to V4 - https://lore.kernel.org/all/20250725100806.1157-1-jie.gan@oss.qualcomm.com/
Changes in V4:
1. Rename the function to coresight_get_in_port_dest regarding to Mike's
comment (patch 1/10).
2. Add lock to protect the connections regarding to Mike's comment
(patch 2/10).
3. Move all byte-cntr functions to coresight-ctcu-byte-cntr file.
4. Add tmc_read_ops to wrap all read operations for TMC device.
5. Add a function in helper_ops to check whether the byte-cntr is
enabkled.
6. Call byte-cntr's read_ops if byte-cntr is enabled when reading data
from the sysfs node.
Link to V3 resend - https://lore.kernel.org/all/20250714063109.591-1-jie.gan@oss.qualcomm.com/
Changes in V3 resend:
1. rebased on next-20250711.
Link to V3 - https://lore.kernel.org/all/20250624060438.7469-1-jie.gan@oss.qualcomm.com/
Changes in V3:
1. The previous solution has been deprecated.
2. Add a etr_buf_list to manage allcated etr buffers.
3. Add a logic to switch buffer for ETR.
4. Add read functions to read trace data from synced etr buffer.
Link to V2 - https://lore.kernel.org/all/20250410013330.3609482-1-jie.gan@oss.qualcomm.com/
Changes in V2:
1. Removed the independent file node /dev/byte_cntr.
2. Integrated the byte-cntr's file operations with current ETR file
node.
3. Optimized the driver code of the CTCU that associated with byte-cntr.
4. Add kernel document for the export API tmc_etr_get_rwp_offset.
5. Optimized the way to read the rwp_offset according to Mike's
suggestion.
6. Removed the dependency of the dts patch.
Link to V1 - https://lore.kernel.org/all/20250310090407.2069489-1-quic_jiegan@quicinc.com/
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Jie Gan (7):
coresight: core: refactor ctcu_get_active_port and make it generic
coresight: tmc: add create/clean functions for etr_buf_list
coresight: tmc: introduce tmc_sysfs_ops to wrap sysfs read operations
coresight: etr: add a new function to retrieve the CTCU device
dt-bindings: arm: add an interrupt property for Coresight CTCU
coresight: ctcu: enable byte-cntr for TMC ETR devices
arm64: dts: qcom: lemans: add interrupts to CTCU device
.../ABI/testing/sysfs-bus-coresight-devices-ctcu | 9 +
.../bindings/arm/qcom,coresight-ctcu.yaml | 10 +
arch/arm64/boot/dts/qcom/lemans.dtsi | 3 +
drivers/hwtracing/coresight/Makefile | 2 +-
drivers/hwtracing/coresight/coresight-core.c | 27 ++
.../hwtracing/coresight/coresight-ctcu-byte-cntr.c | 327 +++++++++++++++++++++
drivers/hwtracing/coresight/coresight-ctcu-core.c | 146 +++++++--
drivers/hwtracing/coresight/coresight-ctcu.h | 81 ++++-
drivers/hwtracing/coresight/coresight-priv.h | 2 +
drivers/hwtracing/coresight/coresight-tmc-core.c | 55 ++--
drivers/hwtracing/coresight/coresight-tmc-etr.c | 265 ++++++++++++++++-
drivers/hwtracing/coresight/coresight-tmc.h | 42 +++
12 files changed, 896 insertions(+), 73 deletions(-)
---
base-commit: 4e5dfb7c84012007c3c7061126491bbc92d71bf1
change-id: 20260309-enable-byte-cntr-for-ctcu-ff86e6198b7f
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
^ permalink raw reply
* [PATCH v19 1/7] coresight: core: refactor ctcu_get_active_port and make it generic
From: Jie Gan @ 2026-06-25 10:45 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Alexander Shishkin, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jie Gan, Bjorn Andersson,
Konrad Dybcio, Yuanfang Zhang, Mao Jinlong
Cc: coresight, linux-arm-kernel, linux-kernel, linux-arm-msm,
devicetree, Mike Leach
In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com>
Remove ctcu_get_active_port from CTCU module and add it to the core
framework.
The port number is crucial for the CTCU device to identify which ETR
it serves. With the port number we can correctly get required parameters
of the CTCU device in TMC module.
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
drivers/hwtracing/coresight/coresight-core.c | 27 +++++++++++++++++++++++
drivers/hwtracing/coresight/coresight-ctcu-core.c | 19 +---------------
drivers/hwtracing/coresight/coresight-priv.h | 2 ++
3 files changed, 30 insertions(+), 18 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index 6d65c43d574f..7a7a85acdca0 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -773,6 +773,33 @@ struct coresight_device *coresight_get_sink(struct coresight_path *path)
}
EXPORT_SYMBOL_GPL(coresight_get_sink);
+/**
+ * coresight_get_in_port: Find the input port number at @remote where the @csdev
+ * device is connected to.
+ *
+ * @csdev: csdev of the device.
+ * @remote: csdev of the remote device which is connected to @csdev.
+ *
+ * Return: port number upon success or -EINVAL for fail.
+ */
+int coresight_get_in_port(struct coresight_device *csdev,
+ struct coresight_device *remote)
+{
+ struct coresight_platform_data *pdata = remote->pdata;
+ int i;
+
+ for (i = 0; i < pdata->nr_inconns; ++i) {
+ if (!pdata->in_conns[i])
+ continue;
+
+ if (pdata->in_conns[i]->src_dev == csdev)
+ return pdata->in_conns[i]->dest_port;
+ }
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(coresight_get_in_port);
+
u32 coresight_get_sink_id(struct coresight_device *csdev)
{
if (!csdev->ea)
diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c
index 9043cad42f01..e8720026c9e3 100644
--- a/drivers/hwtracing/coresight/coresight-ctcu-core.c
+++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c
@@ -116,23 +116,6 @@ static int __ctcu_set_etr_traceid(struct coresight_device *csdev, u8 traceid, in
return 0;
}
-/*
- * Searching the sink device from helper's view in case there are multiple helper devices
- * connected to the sink device.
- */
-static int ctcu_get_active_port(struct coresight_device *sink, struct coresight_device *helper)
-{
- struct coresight_platform_data *pdata = helper->pdata;
- int i;
-
- for (i = 0; i < pdata->nr_inconns; ++i) {
- if (pdata->in_conns[i]->src_dev == sink)
- return pdata->in_conns[i]->dest_port;
- }
-
- return -EINVAL;
-}
-
static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight_path *path,
bool enable)
{
@@ -145,7 +128,7 @@ static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight
return -EINVAL;
}
- port_num = ctcu_get_active_port(sink, csdev);
+ port_num = coresight_get_in_port(sink, csdev);
if (port_num < 0)
return -EINVAL;
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index dddac946659f..854c0a3cb080 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -155,6 +155,8 @@ void coresight_remove_links(struct coresight_device *orig,
u32 coresight_get_sink_id(struct coresight_device *csdev);
int coresight_path_assign_trace_id(struct coresight_path *path,
enum cs_mode mode);
+int coresight_get_in_port(struct coresight_device *csdev,
+ struct coresight_device *remote);
#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
int etm_readl_cp14(u32 off, unsigned int *val);
--
2.34.1
^ permalink raw reply related
* [PATCH v19 2/7] coresight: tmc: add create/clean functions for etr_buf_list
From: Jie Gan @ 2026-06-25 10:45 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Alexander Shishkin, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jie Gan, Bjorn Andersson,
Konrad Dybcio, Yuanfang Zhang, Mao Jinlong
Cc: coresight, linux-arm-kernel, linux-kernel, linux-arm-msm,
devicetree, Mike Leach
In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com>
Introduce functions for creating and inserting or removing the
etr_buf_node to/from the etr_buf_list.
The byte-cntr functionality requires two etr_buf to receive trace data.
The active etr_buf collects the trace data from source device, while the
byte-cntr reading function accesses the deactivated etr_buf after is
has been filled and synced, transferring data to the userspace.
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
drivers/hwtracing/coresight/coresight-tmc-core.c | 1 +
drivers/hwtracing/coresight/coresight-tmc-etr.c | 126 +++++++++++++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 17 +++
3 files changed, 144 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index bc5a133ada3e..bc7dd676da47 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -835,6 +835,7 @@ static int __tmc_probe(struct device *dev, struct resource *res)
idr_init(&drvdata->idr);
mutex_init(&drvdata->idr_mutex);
dev_list = "tmc_etr";
+ INIT_LIST_HEAD(&drvdata->etr_buf_list);
break;
case TMC_CONFIG_TYPE_ETF:
desc.groups = coresight_etf_groups;
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 361a433e6f0c..9b3ef73e9cf2 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1918,6 +1918,132 @@ const struct coresight_ops tmc_etr_cs_ops = {
.panic_ops = &tmc_etr_sync_ops,
};
+/**
+ * tmc_clean_etr_buf_list - clean the etr_buf_list.
+ * @drvdata: driver data of the TMC device.
+ *
+ * Remove all nodes from @drvdata->etr_buf_list and free their buffers.
+ * If a node holds the live sysfs_buf and the device is active, the node is
+ * removed but the buffer is not freed; ownership stays with drvdata->sysfs_buf.
+ *
+ * Locking: callers must guarantee exclusive access to @drvdata->etr_buf_list
+ * and must not hold @drvdata->spinlock. The spinlock is taken internally only
+ * to serialise the @drvdata->sysfs_buf accesses against the ETR sink
+ * enable/disable paths. Must be called from process context: buffers are freed
+ * with the lock released.
+ */
+void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata)
+{
+ struct etr_buf_node *nd, *next;
+ unsigned long flags;
+
+ list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, link) {
+ raw_spin_lock_irqsave(&drvdata->spinlock, flags);
+ if (nd->sysfs_buf == drvdata->sysfs_buf) {
+ if (coresight_get_mode(drvdata->csdev) != CS_MODE_DISABLED)
+ /*
+ * The device is still active. Keep the live
+ * buffer owned by drvdata->sysfs_buf and only
+ * drop the list's reference to it.
+ */
+ nd->sysfs_buf = NULL;
+ else
+ /* Free the buffer below through nd->sysfs_buf */
+ drvdata->sysfs_buf = NULL;
+ }
+ raw_spin_unlock_irqrestore(&drvdata->spinlock, flags);
+
+ /* Free the buffer (NULL is ignored) and the node out of the lock */
+ tmc_etr_free_sysfs_buf(nd->sysfs_buf);
+ list_del(&nd->link);
+ kfree(nd);
+ }
+}
+EXPORT_SYMBOL_GPL(tmc_clean_etr_buf_list);
+
+/**
+ * tmc_create_etr_buf_list - create a list to manage the etr_buf_node.
+ * @drvdata: driver data of the TMC device.
+ * @num_nodes: number of nodes want to create with the list.
+ *
+ * Locking: callers must guarantee exclusive access to @drvdata->etr_buf_list
+ * and must not hold @drvdata->spinlock. The spinlock is taken internally only
+ * to serialise the @drvdata->sysfs_buf accesses against the ETR sink
+ * enable/disable paths. Must be called from process context: buffers and nodes
+ * are allocated with the lock released.
+ *
+ * Return 0 upon success and return the error number if fail.
+ */
+int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes)
+{
+ struct etr_buf_node *new_node;
+ struct etr_buf *sysfs_buf;
+ unsigned long flags;
+ int i = 0, ret = 0;
+
+ /* We don't need a list if there is only one node */
+ if (num_nodes < 2)
+ return -EINVAL;
+
+ /*
+ * We expect that sysfs_buf in drvdata has already been allocated.
+ * Wrap the live sysfs_buf into the first node so the captured trace
+ * data is preserved. The list is owned by the caller, so no lock is
+ * needed to read sysfs_buf or to add the node here.
+ */
+ if (drvdata->sysfs_buf) {
+ new_node = kzalloc_obj(*new_node, GFP_KERNEL);
+ if (!new_node)
+ return -ENOMEM;
+
+ new_node->sysfs_buf = drvdata->sysfs_buf;
+ new_node->is_free = false;
+ list_add(&new_node->link, &drvdata->etr_buf_list);
+ i++;
+ }
+
+ while (i < num_nodes) {
+ new_node = kzalloc_obj(*new_node, GFP_KERNEL);
+ if (!new_node) {
+ ret = -ENOMEM;
+ break;
+ }
+
+ /* Allocate the buffer with the lock released */
+ sysfs_buf = tmc_alloc_etr_buf(drvdata, drvdata->size, 0, cpu_to_node(0), NULL);
+ if (IS_ERR(sysfs_buf)) {
+ kfree(new_node);
+ ret = PTR_ERR(sysfs_buf);
+ break;
+ }
+
+ new_node->sysfs_buf = sysfs_buf;
+ /*
+ * Only the drvdata->sysfs_buf write needs the spinlock, to
+ * serialise against the ETR sink enable/disable paths.
+ */
+ raw_spin_lock_irqsave(&drvdata->spinlock, flags);
+ /* We don't have an available sysfs_buf in drvdata, set one up */
+ if (!drvdata->sysfs_buf) {
+ drvdata->sysfs_buf = sysfs_buf;
+ new_node->is_free = false;
+ } else {
+ new_node->is_free = true;
+ }
+ raw_spin_unlock_irqrestore(&drvdata->spinlock, flags);
+
+ list_add_tail(&new_node->link, &drvdata->etr_buf_list);
+ i++;
+ }
+
+ /* Clean the list if there is an error */
+ if (ret)
+ tmc_clean_etr_buf_list(drvdata);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(tmc_create_etr_buf_list);
+
int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
{
int ret = 0;
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 319a354ede9f..6e994678f926 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -208,6 +208,19 @@ struct tmc_resrv_buf {
s64 len;
};
+/**
+ * @sysfs_buf: Allocated sysfs_buf.
+ * @is_free: Indicates whether the buffer is free to choose.
+ * @pos: Offset to the start of the buffer.
+ * @link: list_head of the node.
+ */
+struct etr_buf_node {
+ struct etr_buf *sysfs_buf;
+ bool is_free;
+ loff_t pos;
+ struct list_head link;
+};
+
/**
* struct tmc_drvdata - specifics associated to an TMC component
* @atclk: optional clock for the core parts of the TMC.
@@ -245,6 +258,7 @@ struct tmc_resrv_buf {
* (after crash) by default.
* @crash_mdata: Reserved memory for storing tmc crash metadata.
* Used by ETR/ETF.
+ * @etr_buf_list: List that is used to manage allocated etr_buf.
*/
struct tmc_drvdata {
struct clk *atclk;
@@ -275,6 +289,7 @@ struct tmc_drvdata {
struct etr_buf *perf_buf;
struct tmc_resrv_buf resrv_buf;
struct tmc_resrv_buf crash_mdata;
+ struct list_head etr_buf_list;
};
struct etr_buf_operations {
@@ -447,5 +462,7 @@ struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev,
enum cs_mode mode,
struct coresight_path *path);
extern const struct attribute_group coresight_etr_group;
+void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata);
+int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes);
#endif
--
2.34.1
^ permalink raw reply related
* [PATCH v19 3/7] coresight: tmc: introduce tmc_sysfs_ops to wrap sysfs read operations
From: Jie Gan @ 2026-06-25 10:45 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Alexander Shishkin, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jie Gan, Bjorn Andersson,
Konrad Dybcio, Yuanfang Zhang, Mao Jinlong
Cc: coresight, linux-arm-kernel, linux-kernel, linux-arm-msm,
devicetree, Mike Leach
In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com>
Introduce tmc_sysfs_ops as a wrapper, wrap sysfs read operations,
for reading trace data from the TMC buffer.
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
drivers/hwtracing/coresight/coresight-tmc-core.c | 51 ++++++++++--------------
drivers/hwtracing/coresight/coresight-tmc.h | 15 +++++++
2 files changed, 37 insertions(+), 29 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index bc7dd676da47..4b40b692be4d 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -228,17 +228,10 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata)
{
int ret = 0;
- switch (drvdata->config_type) {
- case TMC_CONFIG_TYPE_ETB:
- case TMC_CONFIG_TYPE_ETF:
- ret = tmc_read_prepare_etb(drvdata);
- break;
- case TMC_CONFIG_TYPE_ETR:
- ret = tmc_read_prepare_etr(drvdata);
- break;
- default:
+ if (drvdata->sysfs_ops)
+ ret = drvdata->sysfs_ops->read_prepare(drvdata);
+ else
ret = -EINVAL;
- }
if (!ret)
dev_dbg(&drvdata->csdev->dev, "TMC read start\n");
@@ -250,17 +243,10 @@ static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
{
int ret = 0;
- switch (drvdata->config_type) {
- case TMC_CONFIG_TYPE_ETB:
- case TMC_CONFIG_TYPE_ETF:
- ret = tmc_read_unprepare_etb(drvdata);
- break;
- case TMC_CONFIG_TYPE_ETR:
- ret = tmc_read_unprepare_etr(drvdata);
- break;
- default:
+ if (drvdata->sysfs_ops)
+ ret = drvdata->sysfs_ops->read_unprepare(drvdata);
+ else
ret = -EINVAL;
- }
if (!ret)
dev_dbg(&drvdata->csdev->dev, "TMC read end\n");
@@ -287,15 +273,7 @@ static int tmc_open(struct inode *inode, struct file *file)
static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len,
char **bufpp)
{
- switch (drvdata->config_type) {
- case TMC_CONFIG_TYPE_ETB:
- case TMC_CONFIG_TYPE_ETF:
- return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp);
- case TMC_CONFIG_TYPE_ETR:
- return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
- }
-
- return -EINVAL;
+ return drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp);
}
static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
@@ -764,6 +742,18 @@ static void register_crash_dev_interface(struct tmc_drvdata *drvdata,
"Valid crash tracedata found\n");
}
+static const struct tmc_sysfs_ops etb_sysfs_ops = {
+ .read_prepare = tmc_read_prepare_etb,
+ .read_unprepare = tmc_read_unprepare_etb,
+ .get_trace_data = tmc_etb_get_sysfs_trace,
+};
+
+static const struct tmc_sysfs_ops etr_sysfs_ops = {
+ .read_prepare = tmc_read_prepare_etr,
+ .read_unprepare = tmc_read_unprepare_etr,
+ .get_trace_data = tmc_etr_get_sysfs_trace,
+};
+
static int __tmc_probe(struct device *dev, struct resource *res)
{
int ret = 0;
@@ -823,6 +813,7 @@ static int __tmc_probe(struct device *dev, struct resource *res)
desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
desc.ops = &tmc_etb_cs_ops;
dev_list = "tmc_etb";
+ drvdata->sysfs_ops = &etb_sysfs_ops;
break;
case TMC_CONFIG_TYPE_ETR:
desc.groups = coresight_etr_groups;
@@ -835,6 +826,7 @@ static int __tmc_probe(struct device *dev, struct resource *res)
idr_init(&drvdata->idr);
mutex_init(&drvdata->idr_mutex);
dev_list = "tmc_etr";
+ drvdata->sysfs_ops = &etr_sysfs_ops;
INIT_LIST_HEAD(&drvdata->etr_buf_list);
break;
case TMC_CONFIG_TYPE_ETF:
@@ -844,6 +836,7 @@ static int __tmc_probe(struct device *dev, struct resource *res)
desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
desc.ops = &tmc_etf_cs_ops;
dev_list = "tmc_etf";
+ drvdata->sysfs_ops = &etb_sysfs_ops;
break;
default:
pr_err("%s: Unsupported TMC config\n", desc.name);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 6e994678f926..a14645b04624 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -259,6 +259,7 @@ struct etr_buf_node {
* @crash_mdata: Reserved memory for storing tmc crash metadata.
* Used by ETR/ETF.
* @etr_buf_list: List that is used to manage allocated etr_buf.
+ * @sysfs_ops: Read operations for the sysfs mode.
*/
struct tmc_drvdata {
struct clk *atclk;
@@ -290,6 +291,20 @@ struct tmc_drvdata {
struct tmc_resrv_buf resrv_buf;
struct tmc_resrv_buf crash_mdata;
struct list_head etr_buf_list;
+ const struct tmc_sysfs_ops *sysfs_ops;
+};
+
+/**
+ * struct tmc_sysfs_ops - read operations for TMC and its helper devices
+ * @read_prepare: prepare operation.
+ * @read_unprepare: unprepare operation.
+ * @get_trace_data: read operation.
+ */
+struct tmc_sysfs_ops {
+ int (*read_prepare)(struct tmc_drvdata *drvdata);
+ int (*read_unprepare)(struct tmc_drvdata *drvdata);
+ ssize_t (*get_trace_data)(struct tmc_drvdata *drvdata, loff_t pos,
+ size_t len, char **bufpp);
};
struct etr_buf_operations {
--
2.34.1
^ permalink raw reply related
* [PATCH v3] dt-bindings: pwm: st,pwm: convert to DT schema
From: Charan Pedumuru @ 2026-06-25 10:46 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones
Cc: linux-pwm, devicetree, linux-kernel, Charan Pedumuru
Convert STMicroelectronics STiH41x PWM/Capture controller binding
to DT schema.
Changes during conversion:
- Fix compatible string from "st,pwm" to "st,sti-pwm" to match the
actual hardware variant naming convention used across STi bindings.
- Drop pinctrl-names from the required list as pinctrl properties are
inherited and validated by the pinctrl schema.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
Changes in v3:
- Fix compatible to "st,sti-pwm".
- Drop pinctrl-names from required.
- Modify the commit message to explain the changes made.
- Change maintainer to "Lee Jones <lee.jones@linaro.org>".
- Link to v2: https://patch.msgid.link/20260618-st-pwm-v2-1-c792d5795ce2@gmail.com
Changes in v2:
- Add the missing interrupts to the required following the old binding.
- Modify the commit message to explain the changes made.
- Link to v1: https://patch.msgid.link/20260613-st-pwm-v1-1-458c2c89709a@gmail.com
---
Documentation/devicetree/bindings/pwm/pwm-st.txt | 43 ----------
.../devicetree/bindings/pwm/st,sti-pwm.yaml | 92 ++++++++++++++++++++++
2 files changed, 92 insertions(+), 43 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-st.txt b/Documentation/devicetree/bindings/pwm/pwm-st.txt
deleted file mode 100644
index 19fce774cafa..000000000000
--- a/Documentation/devicetree/bindings/pwm/pwm-st.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-STMicroelectronics PWM driver bindings
---------------------------------------
-
-Required parameters:
-- compatible : "st,pwm"
-- #pwm-cells : Number of cells used to specify a PWM. First cell
- specifies the per-chip index of the PWM to use and the
- second cell is the period in nanoseconds - fixed to 2
- for STiH41x.
-- reg : Physical base address and length of the controller's
- registers.
-- pinctrl-names: Set to "default".
-- pinctrl-0: List of phandles pointing to pin configuration nodes
- for PWM module.
- For Pinctrl properties, please refer to [1].
-- clock-names: Valid entries are "pwm" and/or "capture".
-- clocks: phandle of the clock used by the PWM module.
- For Clk properties, please refer to [2].
-- interrupts: IRQ for the Capture device
-
-Optional properties:
-- st,pwm-num-chan: Number of available PWM channels. Default is 0.
-- st,capture-num-chan: Number of available Capture channels. Default is 0.
-
-[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
-[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Example:
-
-pwm1: pwm@fe510000 {
- compatible = "st,pwm";
- reg = <0xfe510000 0x68>;
- #pwm-cells = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm1_chan0_default
- &pinctrl_pwm1_chan1_default
- &pinctrl_pwm1_chan2_default
- &pinctrl_pwm1_chan3_default>;
- clocks = <&clk_sysin>;
- clock-names = "pwm";
- st,pwm-num-chan = <4>;
- st,capture-num-chan = <2>;
-};
diff --git a/Documentation/devicetree/bindings/pwm/st,sti-pwm.yaml b/Documentation/devicetree/bindings/pwm/st,sti-pwm.yaml
new file mode 100644
index 000000000000..c69073e79ce9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/st,sti-pwm.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/st,sti-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STiH41x PWM/Capture controller
+
+maintainers:
+ - Lee Jones <lee.jones@linaro.org>
+
+description:
+ The STiH41x PWM controller supports both PWM output and input capture
+ functionality. It provides multiple PWM output channels for generating
+ variable duty-cycle waveforms, and multiple input capture channels for
+ measuring external signal periods and pulse widths. PWM output channels
+ and input capture channels are configured independently via
+ st,pwm-num-chan and st,capture-num-chan respectively.
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ const: st,sti-pwm
+
+ reg:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+ pinctrl-names:
+ const: default
+
+ clock-names:
+ items:
+ enum: [pwm, capture]
+ minItems: 1
+ maxItems: 2
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ interrupts:
+ description: IRQ line for the capture device.
+ maxItems: 1
+
+ st,pwm-num-chan:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Number of available PWM output channels.
+ minimum: 0
+ maximum: 4
+ default: 0
+
+ st,capture-num-chan:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Number of available input capture channels.
+ minimum: 0
+ maximum: 4
+ default: 0
+
+required:
+ - reg
+ - compatible
+ - "#pwm-cells"
+ - clock-names
+ - clocks
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ pwm@fe510000 {
+ compatible = "st,pwm";
+ reg = <0xfe510000 0x68>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1_chan0_default
+ &pinctrl_pwm1_chan1_default
+ &pinctrl_pwm1_chan2_default
+ &pinctrl_pwm1_chan3_default>;
+ clocks = <&clk_sysin>;
+ clock-names = "pwm";
+ st,pwm-num-chan = <4>;
+ st,capture-num-chan = <2>;
+ };
+...
---
base-commit: c425609d6ac4012c8bbf01ec2e10e801b1923a7b
change-id: 20260613-st-pwm-1feade6cfea3
Best regards,
--
Charan Pedumuru <charan.pedumuru@gmail.com>
^ permalink raw reply related
* [PATCH v19 4/7] coresight: etr: add a new function to retrieve the CTCU device
From: Jie Gan @ 2026-06-25 10:45 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Alexander Shishkin, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jie Gan, Bjorn Andersson,
Konrad Dybcio, Yuanfang Zhang, Mao Jinlong
Cc: coresight, linux-arm-kernel, linux-kernel, linux-arm-msm,
devicetree
In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com>
Add tmc_etr_get_ctcu_device function to find the ptr of the
coresight_device of the CTCU device if the CTCU device is connected to
the TMC ETR device.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 24 ++++++++++++++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
2 files changed, 25 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 9b3ef73e9cf2..2b26ce6455a7 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -865,6 +865,30 @@ tmc_etr_get_catu_device(struct tmc_drvdata *drvdata)
}
EXPORT_SYMBOL_GPL(tmc_etr_get_catu_device);
+/*
+ * TMC ETR could be connected to a CTCU device, which can provide ATID filter
+ * and byte-cntr service. This is represented by the output port of the TMC
+ * (ETR) connected to the input port of the CTCU.
+ *
+ * Returns : coresight_device ptr for the CTCU device if a CTCU is found.
+ * : NULL otherwise.
+ */
+struct coresight_device *
+tmc_etr_get_ctcu_device(struct tmc_drvdata *drvdata)
+{
+ struct coresight_device *etr = drvdata->csdev;
+ union coresight_dev_subtype ctcu_subtype = {
+ .helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU
+ };
+
+ if (!IS_ENABLED(CONFIG_CORESIGHT_CTCU))
+ return NULL;
+
+ return coresight_find_output_type(etr->pdata, CORESIGHT_DEV_TYPE_HELPER,
+ ctcu_subtype);
+}
+EXPORT_SYMBOL_GPL(tmc_etr_get_ctcu_device);
+
static const struct etr_buf_operations *etr_buf_ops[] = {
[ETR_MODE_FLAT] = &etr_flat_buf_ops,
[ETR_MODE_ETR_SG] = &etr_sg_buf_ops,
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index a14645b04624..fbb015079872 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -470,6 +470,7 @@ static inline uint32_t find_crash_tracedata_crc(struct tmc_drvdata *drvdata,
}
struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata);
+struct coresight_device *tmc_etr_get_ctcu_device(struct tmc_drvdata *drvdata);
void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu);
void tmc_etr_remove_catu_ops(void);
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 2/3] dt-bindings: phy: rockchip-inno-csi-dphy: add rockchip,clk-lane-phase property
From: Gerald Loacker @ 2026-06-25 10:46 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Vinod Koul, Neil Armstrong, Heiko Stuebner, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-phy, linux-arm-kernel,
linux-rockchip, linux-kernel, devicetree
In-Reply-To: <20260625-lean-debonair-anteater-c22f83@quoll>
Am 25.06.2026 um 08:43 schrieb Krzysztof Kozlowski:
> On Fri, Jun 19, 2026 at 11:13:40AM +0200, Gerald Loacker wrote:
>> Add support for the optional rockchip,clk-lane-phase device tree property
>> to allow board-specific tuning of the clock lane sampling phase for
>> improved signal integrity across supported data rates.
>>
>> Signed-off-by: Gerald Loacker <gerald.loacker@wolfvision.net>
>> ---
>> .../devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
>> index 03950b3cad08c..010950a8a8856 100644
>> --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
>> @@ -56,6 +56,15 @@ properties:
>> description:
>> Some additional phy settings are access through GRF regs.
>>
>> + rockchip,clk-lane-phase:
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + minimum: 0
>> + maximum: 7
>
> Missing default here. If default is unknown, explain that in commit msg.
>
You're right, I missed the default.
I'll add it in the next revision.
Gerald
> Best regards,
> Krzysztof
>
^ permalink raw reply
* [PATCH v19 5/7] dt-bindings: arm: add an interrupt property for Coresight CTCU
From: Jie Gan @ 2026-06-25 10:45 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Alexander Shishkin, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jie Gan, Bjorn Andersson,
Konrad Dybcio, Yuanfang Zhang, Mao Jinlong
Cc: coresight, linux-arm-kernel, linux-kernel, linux-arm-msm,
devicetree, Krzysztof Kozlowski, Mike Leach
In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com>
Add an interrupt property to CTCU device. The interrupt will be triggered
when the data size in the ETR buffer exceeds the threshold of the
BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register
of CTCU device will enable the interrupt.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
index e002f87361ad..2981001a7d7f 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
@@ -44,6 +44,11 @@ properties:
items:
- const: apb
+ interrupts:
+ items:
+ - description: Interrupt for the ETR device connected to in-port0.
+ - description: Interrupt for the ETR device connected to in-port1.
+
label:
description:
Description of a coresight device.
@@ -65,6 +70,8 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
ctcu@1001000 {
compatible = "qcom,sa8775p-ctcu";
reg = <0x1001000 0x1000>;
@@ -72,6 +79,9 @@ examples:
clocks = <&aoss_qmp>;
clock-names = "apb";
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
+
in-ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.34.1
^ permalink raw reply related
* [PATCH v19 6/7] coresight: ctcu: enable byte-cntr for TMC ETR devices
From: Jie Gan @ 2026-06-25 10:45 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Alexander Shishkin, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jie Gan, Bjorn Andersson,
Konrad Dybcio, Yuanfang Zhang, Mao Jinlong
Cc: coresight, linux-arm-kernel, linux-kernel, linux-arm-msm,
devicetree
In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com>
The byte-cntr function provided by the CTCU device is used to transfer data
from the ETR buffer to the userspace. An interrupt is triggered if the data
size exceeds the threshold set in the BYTECNTRVAL register. The interrupt
handler counts the number of triggered interruptions and the read function
will read the data from the synced ETR buffer.
Switching the sysfs_buf when current buffer is full or the timeout is
triggered and resets rrp and rwp registers after switched the buffer.
The synced buffer will become available for reading after the switch.
Byte-cntr workflow:
start -> ctcu_enable(ctcu_byte_cntr_start) -> tmc_enable_etr_sink ->
tmc_read_prepare_etr(jump to tmc_read_prepare_byte_cntr) ->
tmc_etr_get_sysfs_trace(jump to tmc_byte_cntr_get_data) ->
tmc_disable_etr_sink -> ctcu_disable(ctcu_byte_cntr_stop) ->
tmc_read_unprepare_etr(jump to tmc_read_unprepare_byte_cntr) -> finish
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
.../ABI/testing/sysfs-bus-coresight-devices-ctcu | 9 +
drivers/hwtracing/coresight/Makefile | 2 +-
.../hwtracing/coresight/coresight-ctcu-byte-cntr.c | 327 +++++++++++++++++++++
drivers/hwtracing/coresight/coresight-ctcu-core.c | 127 +++++++-
drivers/hwtracing/coresight/coresight-ctcu.h | 81 ++++-
drivers/hwtracing/coresight/coresight-tmc-core.c | 3 +-
drivers/hwtracing/coresight/coresight-tmc-etr.c | 115 +++++++-
drivers/hwtracing/coresight/coresight-tmc.h | 9 +
8 files changed, 647 insertions(+), 26 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu
new file mode 100644
index 000000000000..beef0be21969
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu
@@ -0,0 +1,9 @@
+What: /sys/bus/coresight/devices/<ctcu-name>/irq_enabled[0:1]
+Date: June 2026
+KernelVersion: 7.3
+Contact: Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>; Jinlong Mao <jinlong.mao@oss.qualcomm.com>; Jie Gan <jie.gan@oss.qualcomm.com>
+Description:
+ (RW) Configure the flag to enable interrupt to count data during CTCU enablement.
+ An interrupt is generated when the data size exceeds the value set in the IRQ register.
+ 0 : disable
+ 1 : enable
diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
index ab16d06783a5..821a1b06b20c 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -55,5 +55,5 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o
obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o
obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o
-coresight-ctcu-y := coresight-ctcu-core.o
+coresight-ctcu-y := coresight-ctcu-core.o coresight-ctcu-byte-cntr.o
obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) += coresight-kunit-tests.o
diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c
new file mode 100644
index 000000000000..5ab97a71f02f
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c
@@ -0,0 +1,327 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/coresight.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/of_irq.h>
+#include <linux/uaccess.h>
+
+#include "coresight-ctcu.h"
+#include "coresight-priv.h"
+#include "coresight-tmc.h"
+
+static irqreturn_t byte_cntr_handler(int irq, void *data)
+{
+ struct ctcu_byte_cntr *byte_cntr_data = data;
+
+ atomic_inc(&byte_cntr_data->irq_cnt);
+ wake_up(&byte_cntr_data->wq);
+
+ return IRQ_HANDLED;
+}
+
+static void ctcu_cfg_byte_cntr_reg(struct ctcu_drvdata *drvdata, u32 val,
+ u32 offset)
+{
+ /* A one value for IRQCTRL register represents 8 bytes */
+ ctcu_program_register(drvdata, val / 8, offset);
+}
+
+static struct ctcu_byte_cntr *ctcu_get_byte_cntr(struct coresight_device *ctcu,
+ struct coresight_device *etr)
+{
+ struct ctcu_drvdata *drvdata = dev_get_drvdata(ctcu->dev.parent);
+ int port;
+
+ port = coresight_get_in_port(etr, ctcu);
+ if (port < 0 || port > 1)
+ return NULL;
+
+ return &drvdata->byte_cntr_data[port];
+}
+
+static bool ctcu_byte_cntr_switch_buffer(struct tmc_drvdata *etr_drvdata,
+ struct ctcu_byte_cntr *byte_cntr_data)
+{
+ struct etr_buf_node *nd, *next, *curr_node = NULL, *picked_node = NULL;
+ struct etr_buf *curr_buf = etr_drvdata->sysfs_buf;
+ bool found_free_buf = false;
+ unsigned long flags;
+
+ if (WARN_ON(!etr_drvdata || !byte_cntr_data))
+ return false;
+
+ /* Stop the ETR before initiating the switch */
+ if (coresight_get_mode(etr_drvdata->csdev) != CS_MODE_DISABLED)
+ tmc_etr_enable_disable_hw(etr_drvdata, false);
+
+ /*
+ * Serialise the sysfs_buf/etr_buf swap against the ETR sink
+ * enable/disable paths which also touch these fields under the
+ * spinlock. tmc_etr_enable_disable_hw() takes the same lock, so it
+ * must be called outside this critical section.
+ */
+ raw_spin_lock_irqsave(&etr_drvdata->spinlock, flags);
+ list_for_each_entry_safe(nd, next, &etr_drvdata->etr_buf_list, link) {
+ /* curr_buf is free for next round */
+ if (nd->sysfs_buf == curr_buf) {
+ nd->is_free = true;
+ curr_node = nd;
+ } else if (!found_free_buf && nd->is_free) {
+ picked_node = nd;
+ found_free_buf = true;
+ }
+ }
+
+ if (found_free_buf) {
+ curr_node->pos = 0;
+ curr_node->reading = true;
+ byte_cntr_data->buf_node = curr_node;
+ etr_drvdata->sysfs_buf = picked_node->sysfs_buf;
+ etr_drvdata->etr_buf = picked_node->sysfs_buf;
+ picked_node->is_free = false;
+ /* Reset irq_cnt for next etr_buf */
+ atomic_set(&byte_cntr_data->irq_cnt, 0);
+ }
+ raw_spin_unlock_irqrestore(&etr_drvdata->spinlock, flags);
+
+ /* Restart the ETR once a free buffer is available */
+ if (found_free_buf &&
+ coresight_get_mode(etr_drvdata->csdev) != CS_MODE_DISABLED)
+ tmc_etr_enable_disable_hw(etr_drvdata, true);
+
+ return found_free_buf;
+}
+
+/*
+ * ctcu_byte_cntr_get_data() - reads data from the deactivated and filled buffer.
+ * The byte-cntr reading work reads data from the deactivated and filled buffer.
+ * The read operation waits for a buffer to become available, either filled or
+ * upon timeout, and then reads trace data from the synced buffer.
+ */
+static ssize_t tmc_byte_cntr_get_data(struct tmc_drvdata *etr_drvdata, loff_t pos,
+ size_t len, char **bufpp)
+{
+ struct coresight_device *ctcu = tmc_etr_get_ctcu_device(etr_drvdata);
+ struct device *dev = &etr_drvdata->csdev->dev;
+ struct ctcu_byte_cntr *byte_cntr_data;
+ struct etr_buf *sysfs_buf;
+ atomic_t *irq_cnt;
+ ssize_t actual;
+ int ret;
+
+ byte_cntr_data = ctcu_get_byte_cntr(ctcu, etr_drvdata->csdev);
+ if (!byte_cntr_data || !byte_cntr_data->irq_enabled)
+ return -EINVAL;
+
+ irq_cnt = &byte_cntr_data->irq_cnt;
+
+wait_buffer:
+ if (!byte_cntr_data->buf_node) {
+ ret = wait_event_interruptible_timeout(byte_cntr_data->wq,
+ (atomic_read(irq_cnt) >= MAX_IRQ_CNT - 1) ||
+ !byte_cntr_data->enable,
+ BYTE_CNTR_TIMEOUT);
+ if (ret < 0)
+ return ret;
+ /*
+ * The current etr_buf is almost full or timeout is triggered,
+ * so switch the buffer and mark the switched buffer as reading.
+ */
+ if (byte_cntr_data->enable) {
+ if (!ctcu_byte_cntr_switch_buffer(etr_drvdata, byte_cntr_data)) {
+ dev_err(dev, "Switch buffer failed for the byte-cntr\n");
+ return -ENOMEM;
+ }
+ } else {
+ /* Exit byte-cntr reading */
+ return 0;
+ }
+ }
+
+ /* Check the status of current etr_buf */
+ if (atomic_read(irq_cnt) >= MAX_IRQ_CNT)
+ dev_warn(dev, "Data overwrite happened\n");
+
+ pos = byte_cntr_data->buf_node->pos;
+ sysfs_buf = byte_cntr_data->buf_node->sysfs_buf;
+ actual = tmc_etr_read_sysfs_buf(sysfs_buf, pos, len, bufpp);
+ if (actual <= 0) {
+ /* Reset buf_node upon reading is finished or failed */
+ byte_cntr_data->buf_node->reading = false;
+ byte_cntr_data->buf_node = NULL;
+
+ /*
+ * Nothing in the buffer, waiting for the next buffer
+ * to be filled.
+ */
+ if (actual == 0)
+ goto wait_buffer;
+ }
+
+ return actual;
+}
+
+static int tmc_read_prepare_byte_cntr(struct tmc_drvdata *etr_drvdata)
+{
+ struct coresight_device *ctcu = tmc_etr_get_ctcu_device(etr_drvdata);
+ struct ctcu_byte_cntr *byte_cntr_data;
+ unsigned long flags;
+ int ret = 0;
+
+ /* byte-cntr is operating with SYSFS mode being enabled only */
+ if (coresight_get_mode(etr_drvdata->csdev) != CS_MODE_SYSFS)
+ return -EINVAL;
+
+ byte_cntr_data = ctcu_get_byte_cntr(ctcu, etr_drvdata->csdev);
+ if (!byte_cntr_data || !byte_cntr_data->irq_enabled)
+ return -EINVAL;
+
+ raw_spin_lock_irqsave(&byte_cntr_data->spin_lock, flags);
+ if (byte_cntr_data->reading) {
+ raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags);
+ return -EBUSY;
+ }
+
+ /* byte_cntr_data->enable may race with ctcu_platform_remove() */
+ if (!byte_cntr_data->enable) {
+ raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags);
+ return -ENODEV;
+ }
+
+ byte_cntr_data->reading = true;
+ raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags);
+ /* Setup an available etr_buf_list for byte-cntr */
+ ret = tmc_create_etr_buf_list(etr_drvdata, 2);
+ if (ret) {
+ byte_cntr_data->reading = false;
+ return ret;
+ }
+
+ scoped_guard(raw_spinlock_irqsave, &byte_cntr_data->spin_lock) {
+ atomic_set(&byte_cntr_data->irq_cnt, 0);
+ /*
+ * Configure the byte-cntr register to enable IRQ. The
+ * configured size is 5% of the buffer_size.
+ */
+ ctcu_cfg_byte_cntr_reg(byte_cntr_data->ctcu_drvdata,
+ etr_drvdata->size / MAX_IRQ_CNT,
+ byte_cntr_data->irq_ctrl_offset);
+ byte_cntr_data->buf_node = NULL;
+ }
+ /* enable_irq_wake() may sleep on slow-bus irqchips, call it unlocked */
+ enable_irq_wake(byte_cntr_data->irq);
+
+ return 0;
+}
+
+static int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *etr_drvdata)
+{
+ struct coresight_device *ctcu = tmc_etr_get_ctcu_device(etr_drvdata);
+ struct ctcu_byte_cntr *byte_cntr_data;
+
+ /*
+ * Do the unprepare operation only when the byte_cntr_data->reading
+ * is truly set
+ */
+ byte_cntr_data = ctcu_get_byte_cntr(ctcu, etr_drvdata->csdev);
+ if (!byte_cntr_data || !byte_cntr_data->irq_enabled ||
+ !byte_cntr_data->reading)
+ return -EINVAL;
+
+ tmc_clean_etr_buf_list(etr_drvdata);
+ scoped_guard(raw_spinlock_irqsave, &byte_cntr_data->spin_lock) {
+ /* Configure the byte-cntr register to disable IRQ */
+ ctcu_cfg_byte_cntr_reg(byte_cntr_data->ctcu_drvdata, 0,
+ byte_cntr_data->irq_ctrl_offset);
+ byte_cntr_data->buf_node = NULL;
+ byte_cntr_data->reading = false;
+ }
+ /*
+ * The threshold IRQ is already disabled by the register write above,
+ * so no wake event can arrive here. disable_irq_wake() may sleep on
+ * slow-bus irqchips, so call it outside the spin_lock.
+ */
+ disable_irq_wake(byte_cntr_data->irq);
+ wake_up(&byte_cntr_data->wq);
+
+ return 0;
+}
+
+const struct tmc_sysfs_ops byte_cntr_sysfs_ops = {
+ .read_prepare = tmc_read_prepare_byte_cntr,
+ .read_unprepare = tmc_read_unprepare_byte_cntr,
+ .get_trace_data = tmc_byte_cntr_get_data,
+};
+
+/* Start the byte-cntr function when the path is enabled. */
+void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path)
+{
+ struct coresight_device *sink = coresight_get_sink(path);
+ struct ctcu_byte_cntr *byte_cntr_data;
+
+ byte_cntr_data = ctcu_get_byte_cntr(csdev, sink);
+ if (!byte_cntr_data)
+ return;
+
+ /* Don't start byte-cntr function when irq_enabled is not set. */
+ if (!byte_cntr_data->irq_enabled || byte_cntr_data->enable)
+ return;
+
+ guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock);
+ byte_cntr_data->enable = true;
+}
+
+/* Stop the byte-cntr function when the path is disabled. */
+void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path)
+{
+ struct coresight_device *sink = coresight_get_sink(path);
+ struct ctcu_byte_cntr *byte_cntr_data;
+
+ if (coresight_get_mode(sink) == CS_MODE_SYSFS)
+ return;
+
+ byte_cntr_data = ctcu_get_byte_cntr(csdev, sink);
+ if (!byte_cntr_data)
+ return;
+
+ guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock);
+ byte_cntr_data->enable = false;
+}
+
+void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int etr_num)
+{
+ struct ctcu_byte_cntr *byte_cntr_data;
+ struct device_node *nd = dev->of_node;
+ int irq_num, ret, i, irq_registered = 0;
+
+ for (i = 0; i < etr_num; i++) {
+ byte_cntr_data = &drvdata->byte_cntr_data[i];
+ irq_num = of_irq_get(nd, i);
+ if (irq_num < 0) {
+ dev_err(dev, "Failed to get IRQ from DT for port%d\n", i);
+ continue;
+ }
+
+ ret = devm_request_irq(dev, irq_num, byte_cntr_handler,
+ IRQF_TRIGGER_RISING | IRQF_SHARED,
+ dev_name(dev), byte_cntr_data);
+ if (ret) {
+ dev_err(dev, "Failed to register IRQ for port%d\n", i);
+ continue;
+ }
+
+ byte_cntr_data->irq = irq_num;
+ byte_cntr_data->ctcu_drvdata = drvdata;
+ init_waitqueue_head(&byte_cntr_data->wq);
+ raw_spin_lock_init(&byte_cntr_data->spin_lock);
+ irq_registered++;
+ }
+
+ if (irq_registered)
+ tmc_etr_set_byte_cntr_sysfs_ops(&byte_cntr_sysfs_ops);
+}
diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c
index e8720026c9e3..2da1a6f3d29f 100644
--- a/drivers/hwtracing/coresight/coresight-ctcu-core.c
+++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024-2026 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk.h>
@@ -18,6 +19,7 @@
#include "coresight-ctcu.h"
#include "coresight-priv.h"
+#include "coresight-tmc.h"
#define ctcu_writel(drvdata, val, offset) __raw_writel((val), drvdata->base + offset)
#define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base + offset)
@@ -43,17 +45,21 @@
#define CTCU_ATID_REG_BIT(traceid) (traceid % 32)
#define CTCU_ATID_REG_SIZE 0x10
+#define CTCU_ETR0_IRQCTRL 0x6c
+#define CTCU_ETR1_IRQCTRL 0x70
#define CTCU_ETR0_ATID0 0xf8
#define CTCU_ETR1_ATID0 0x108
static const struct ctcu_etr_config sa8775p_etr_cfgs[] = {
{
- .atid_offset = CTCU_ETR0_ATID0,
- .port_num = 0,
+ .atid_offset = CTCU_ETR0_ATID0,
+ .irq_ctrl_offset = CTCU_ETR0_IRQCTRL,
+ .port_num = 0,
},
{
- .atid_offset = CTCU_ETR1_ATID0,
- .port_num = 1,
+ .atid_offset = CTCU_ETR1_ATID0,
+ .irq_ctrl_offset = CTCU_ETR1_IRQCTRL,
+ .port_num = 1,
},
};
@@ -62,6 +68,85 @@ static const struct ctcu_config sa8775p_cfgs = {
.num_etr_config = ARRAY_SIZE(sa8775p_etr_cfgs),
};
+void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offset)
+{
+ CS_UNLOCK(drvdata->base);
+ ctcu_writel(drvdata, val, offset);
+ CS_LOCK(drvdata->base);
+}
+
+static ssize_t irq_enabled_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct ctcu_byte_cntr_irq_attribute *irq_attr =
+ container_of(attr, struct ctcu_byte_cntr_irq_attribute, attr);
+ struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ u8 port = irq_attr->port;
+
+ if (!drvdata->byte_cntr_data[port].irq_ctrl_offset)
+ return -EINVAL;
+
+ return sysfs_emit(buf, "%u\n",
+ (unsigned int)drvdata->byte_cntr_data[port].irq_enabled);
+}
+
+static ssize_t irq_enabled_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t size)
+{
+ struct ctcu_byte_cntr_irq_attribute *irq_attr =
+ container_of(attr, struct ctcu_byte_cntr_irq_attribute, attr);
+ struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ u8 port = irq_attr->port;
+ unsigned long val;
+
+ if (kstrtoul(buf, 0, &val))
+ return -EINVAL;
+
+ guard(raw_spinlock_irqsave)(&drvdata->byte_cntr_data[port].spin_lock);
+ if (drvdata->byte_cntr_data[port].reading)
+ return -EBUSY;
+ else if (drvdata->byte_cntr_data[port].irq_ctrl_offset)
+ drvdata->byte_cntr_data[port].irq_enabled = !!val;
+
+ return size;
+}
+
+static umode_t irq_enabled_is_visible(struct kobject *kobj,
+ struct attribute *attr, int n)
+{
+ struct device_attribute *dev_attr =
+ container_of(attr, struct device_attribute, attr);
+ struct ctcu_byte_cntr_irq_attribute *irq_attr =
+ container_of(dev_attr, struct ctcu_byte_cntr_irq_attribute, attr);
+ struct device *dev = kobj_to_dev(kobj);
+ struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ u8 port = irq_attr->port;
+
+ if (drvdata && drvdata->byte_cntr_data[port].irq_ctrl_offset)
+ return attr->mode;
+
+ return 0;
+}
+
+static struct attribute *ctcu_attrs[] = {
+ ctcu_byte_cntr_irq_rw(0),
+ ctcu_byte_cntr_irq_rw(1),
+ NULL,
+};
+
+static struct attribute_group ctcu_attr_grp = {
+ .attrs = ctcu_attrs,
+ .is_visible = irq_enabled_is_visible,
+};
+
+static const struct attribute_group *ctcu_attr_grps[] = {
+ &ctcu_attr_grp,
+ NULL,
+};
+
static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 reg_offset,
u8 bit, bool enable)
{
@@ -140,11 +225,15 @@ static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct coresight
static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode,
struct coresight_path *path)
{
+ ctcu_byte_cntr_start(csdev, path);
+
return ctcu_set_etr_traceid(csdev, path, true);
}
static int ctcu_disable(struct coresight_device *csdev, struct coresight_path *path)
{
+ ctcu_byte_cntr_stop(csdev, path);
+
return ctcu_set_etr_traceid(csdev, path, false);
}
@@ -195,7 +284,10 @@ static int ctcu_probe(struct platform_device *pdev)
for (i = 0; i < cfgs->num_etr_config; i++) {
etr_cfg = &cfgs->etr_cfgs[i];
drvdata->atid_offset[i] = etr_cfg->atid_offset;
+ drvdata->byte_cntr_data[i].irq_ctrl_offset =
+ etr_cfg->irq_ctrl_offset;
}
+ ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config);
}
}
@@ -209,6 +301,7 @@ static int ctcu_probe(struct platform_device *pdev)
desc.dev = dev;
desc.ops = &ctcu_ops;
desc.access = CSDEV_ACCESS_IOMEM(base);
+ desc.groups = ctcu_attr_grps;
raw_spin_lock_init(&drvdata->spin_lock);
drvdata->csdev = coresight_register(&desc);
@@ -244,10 +337,34 @@ static int ctcu_platform_probe(struct platform_device *pdev)
static void ctcu_platform_remove(struct platform_device *pdev)
{
struct ctcu_drvdata *drvdata = platform_get_drvdata(pdev);
+ struct ctcu_byte_cntr *byte_cntr_data;
+ unsigned long flags;
+ int i;
if (WARN_ON(!drvdata))
return;
+ /*
+ * Signal all active byte-cntr readers to exit, then wait for them to
+ * finish before resetting the ops pointer and freeing driver data.
+ * Without this, a reader blocked in wait_event_interruptible_timeout()
+ * would access the freed ctcu_drvdata wait-queue head (use-after-free).
+ */
+ for (i = 0; i < ETR_MAX_NUM; i++) {
+ byte_cntr_data = &drvdata->byte_cntr_data[i];
+ raw_spin_lock_irqsave(&byte_cntr_data->spin_lock, flags);
+ /* Set enable=false for all ports to signal teardown to racing readers */
+ byte_cntr_data->enable = false;
+ if (!byte_cntr_data->reading) {
+ raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags);
+ continue;
+ }
+ raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags);
+ wake_up_all(&byte_cntr_data->wq);
+ wait_event(byte_cntr_data->wq, !byte_cntr_data->reading);
+ }
+
+ tmc_etr_reset_byte_cntr_sysfs_ops();
ctcu_remove(pdev);
pm_runtime_disable(&pdev->dev);
}
diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtracing/coresight/coresight-ctcu.h
index e9594c38dd91..a2ae0a0d91d0 100644
--- a/drivers/hwtracing/coresight/coresight-ctcu.h
+++ b/drivers/hwtracing/coresight/coresight-ctcu.h
@@ -1,23 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2024-2026 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _CORESIGHT_CTCU_H
#define _CORESIGHT_CTCU_H
+
+#include <linux/time.h>
#include "coresight-trace-id.h"
/* Maximum number of supported ETR devices for a single CTCU. */
#define ETR_MAX_NUM 2
+#define BYTE_CNTR_TIMEOUT (3 * HZ)
+#define MAX_IRQ_CNT 20
+
/**
* struct ctcu_etr_config
* @atid_offset: offset to the ATID0 Register.
- * @port_num: in-port number of CTCU device that connected to ETR.
+ * @port_num: in-port number of the CTCU device that connected to ETR.
+ * @irq_ctrl_offset: offset to the BYTECNTRVAL register.
*/
struct ctcu_etr_config {
const u32 atid_offset;
const u32 port_num;
+ const u32 irq_ctrl_offset;
};
struct ctcu_config {
@@ -25,15 +33,68 @@ struct ctcu_config {
int num_etr_config;
};
-struct ctcu_drvdata {
- void __iomem *base;
- struct clk *apb_clk;
- struct device *dev;
- struct coresight_device *csdev;
+/**
+ * struct ctcu_byte_cntr
+ * @enable: indicates that byte_cntr function is enabled or not.
+ * @irq_enabled: indicates that the interruption is enabled.
+ * @reading: indicates that byte_cntr is reading.
+ * @irq: allocated number of the IRQ.
+ * @irq_cnt: IRQ count number of the triggered interruptions.
+ * @wq: waitqueue for reading data from ETR buffer.
+ * @spin_lock: spinlock of the byte_cntr_data.
+ * @irq_ctrl_offset: offset to the BYTECNTVAL Register.
+ * @ctcu_drvdata: drvdata of the CTCU device.
+ * @buf_node: etr_buf_node for reading.
+ */
+struct ctcu_byte_cntr {
+ bool enable;
+ bool irq_enabled;
+ bool reading;
+ int irq;
+ atomic_t irq_cnt;
+ wait_queue_head_t wq;
raw_spinlock_t spin_lock;
- u32 atid_offset[ETR_MAX_NUM];
- /* refcnt for each traceid of each sink */
- u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP];
+ u32 irq_ctrl_offset;
+ struct ctcu_drvdata *ctcu_drvdata;
+ struct etr_buf_node *buf_node;
};
+struct ctcu_drvdata {
+ void __iomem *base;
+ struct clk *apb_clk;
+ struct device *dev;
+ struct coresight_device *csdev;
+ struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM];
+ raw_spinlock_t spin_lock;
+ u32 atid_offset[ETR_MAX_NUM];
+ /* refcnt for each traceid of each sink */
+ u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP];
+};
+
+/**
+ * struct ctcu_byte_cntr_irq_attribute
+ * @attr: The device attribute.
+ * @port: port number.
+ */
+struct ctcu_byte_cntr_irq_attribute {
+ struct device_attribute attr;
+ u8 port;
+};
+
+#define ctcu_byte_cntr_irq_rw(port) \
+ (&((struct ctcu_byte_cntr_irq_attribute[]) { \
+ { \
+ __ATTR(irq_enabled##port, 0644, irq_enabled_show, \
+ irq_enabled_store), \
+ port, \
+ } \
+ })[0].attr.attr)
+
+void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offset);
+
+/* Byte-cntr functions */
+void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path);
+void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path);
+void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int port_num);
+
#endif
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index 4b40b692be4d..6ad09995ba87 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -293,7 +293,8 @@ static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
return -EFAULT;
}
- *ppos += actual;
+ if (!tmc_etr_update_buf_node_pos(drvdata, actual))
+ *ppos += actual;
dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual);
return actual;
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 2b26ce6455a7..e78f8891f11e 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1168,6 +1168,9 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
return rc;
}
+/* Assumes a single CTCU instance per system, as on all current Qualcomm SoCs. */
+static const struct tmc_sysfs_ops *byte_cntr_sysfs_ops;
+
/*
* Return the available trace data in the buffer (starts at etr_buf->offset,
* limited by etr_buf->len) from @pos, with a maximum limit of @len,
@@ -1178,23 +1181,39 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata,
* We are protected here by drvdata->reading != 0, which ensures the
* sysfs_buf stays alive.
*/
-ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
- loff_t pos, size_t len, char **bufpp)
+ssize_t tmc_etr_read_sysfs_buf(struct etr_buf *sysfs_buf, loff_t pos,
+ size_t len, char **bufpp)
{
s64 offset;
ssize_t actual = len;
- struct etr_buf *etr_buf = drvdata->sysfs_buf;
- if (pos + actual > etr_buf->len)
- actual = etr_buf->len - pos;
+ if (pos + actual > sysfs_buf->len)
+ actual = sysfs_buf->len - pos;
if (actual <= 0)
return actual;
/* Compute the offset from which we read the data */
- offset = etr_buf->offset + pos;
- if (offset >= etr_buf->size)
- offset -= etr_buf->size;
- return tmc_etr_buf_get_data(etr_buf, offset, actual, bufpp);
+ offset = sysfs_buf->offset + pos;
+ if (offset >= sysfs_buf->size)
+ offset -= sysfs_buf->size;
+ return tmc_etr_buf_get_data(sysfs_buf, offset, actual, bufpp);
+}
+EXPORT_SYMBOL_GPL(tmc_etr_read_sysfs_buf);
+
+ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
+ loff_t pos, size_t len, char **bufpp)
+{
+ ssize_t ret;
+ const struct tmc_sysfs_ops *byte_cntr_ops = READ_ONCE(byte_cntr_sysfs_ops);
+
+ if (byte_cntr_ops) {
+ ret = byte_cntr_ops->get_trace_data(drvdata, pos, len, bufpp);
+ /* Return the filled buffer */
+ if (ret > 0 || ret == -ENOMEM)
+ return ret;
+ }
+
+ return tmc_etr_read_sysfs_buf(drvdata->sysfs_buf, pos, len, bufpp);
}
static struct etr_buf *
@@ -1248,6 +1267,39 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
}
+static void tmc_etr_reset_sysfs_buf(struct tmc_drvdata *drvdata)
+{
+ u32 sts;
+
+ CS_UNLOCK(drvdata->base);
+ tmc_write_rrp(drvdata, drvdata->sysfs_buf->hwaddr);
+ tmc_write_rwp(drvdata, drvdata->sysfs_buf->hwaddr);
+ sts = readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL;
+ writel_relaxed(sts, drvdata->base + TMC_STS);
+ CS_LOCK(drvdata->base);
+}
+
+/**
+ * tmc_etr_enable_disable_hw - enable/disable the ETR hw.
+ * @drvdata: drvdata of the TMC device.
+ * @enable: indicates enable/disable.
+ */
+void tmc_etr_enable_disable_hw(struct tmc_drvdata *drvdata, bool enable)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&drvdata->spinlock, flags);
+ if (enable) {
+ tmc_etr_reset_sysfs_buf(drvdata);
+ __tmc_etr_enable_hw(drvdata);
+ } else {
+ __tmc_etr_disable_hw(drvdata);
+ }
+
+ raw_spin_unlock_irqrestore(&drvdata->spinlock, flags);
+}
+EXPORT_SYMBOL_GPL(tmc_etr_enable_disable_hw);
+
void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
{
__tmc_etr_disable_hw(drvdata);
@@ -2068,15 +2120,54 @@ int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes)
}
EXPORT_SYMBOL_GPL(tmc_create_etr_buf_list);
+void tmc_etr_set_byte_cntr_sysfs_ops(const struct tmc_sysfs_ops *sysfs_ops)
+{
+ WRITE_ONCE(byte_cntr_sysfs_ops, sysfs_ops);
+}
+EXPORT_SYMBOL_GPL(tmc_etr_set_byte_cntr_sysfs_ops);
+
+void tmc_etr_reset_byte_cntr_sysfs_ops(void)
+{
+ WRITE_ONCE(byte_cntr_sysfs_ops, NULL);
+}
+EXPORT_SYMBOL_GPL(tmc_etr_reset_byte_cntr_sysfs_ops);
+
+bool tmc_etr_update_buf_node_pos(struct tmc_drvdata *drvdata, ssize_t size)
+{
+ struct etr_buf_node *nd, *next;
+
+ if (drvdata->config_type != TMC_CONFIG_TYPE_ETR)
+ return false;
+
+ list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, link) {
+ if (nd && nd->reading) {
+ nd->pos += size;
+ return true;
+ }
+ }
+
+ return false;
+}
+
int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
{
int ret = 0;
unsigned long flags;
+ const struct tmc_sysfs_ops *byte_cntr_ops;
/* config types are set a boot time and never change */
if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETR))
return -EINVAL;
+ byte_cntr_ops = READ_ONCE(byte_cntr_sysfs_ops);
+ if (byte_cntr_ops) {
+ ret = byte_cntr_ops->read_prepare(drvdata);
+ if (!ret || ret == -EBUSY)
+ return ret;
+
+ ret = 0;
+ }
+
raw_spin_lock_irqsave(&drvdata->spinlock, flags);
if (drvdata->reading) {
ret = -EBUSY;
@@ -2108,11 +2199,17 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)
{
unsigned long flags;
struct etr_buf *sysfs_buf = NULL;
+ const struct tmc_sysfs_ops *byte_cntr_ops;
/* config types are set a boot time and never change */
if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETR))
return -EINVAL;
+ byte_cntr_ops = READ_ONCE(byte_cntr_sysfs_ops);
+ if (byte_cntr_ops)
+ if (!byte_cntr_ops->read_unprepare(drvdata))
+ return 0;
+
raw_spin_lock_irqsave(&drvdata->spinlock, flags);
/* RE-enable the TMC if need be */
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index fbb015079872..a15e2f93f16a 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -211,12 +211,15 @@ struct tmc_resrv_buf {
/**
* @sysfs_buf: Allocated sysfs_buf.
* @is_free: Indicates whether the buffer is free to choose.
+ * @reading: Indicates byte_cntr is reading the buffer attached to
+ * the node.
* @pos: Offset to the start of the buffer.
* @link: list_head of the node.
*/
struct etr_buf_node {
struct etr_buf *sysfs_buf;
bool is_free;
+ bool reading;
loff_t pos;
struct list_head link;
};
@@ -480,5 +483,11 @@ struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev,
extern const struct attribute_group coresight_etr_group;
void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata);
int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes);
+void tmc_etr_set_byte_cntr_sysfs_ops(const struct tmc_sysfs_ops *sysfs_ops);
+void tmc_etr_reset_byte_cntr_sysfs_ops(void);
+void tmc_etr_enable_disable_hw(struct tmc_drvdata *drvdata, bool enable);
+bool tmc_etr_update_buf_node_pos(struct tmc_drvdata *drvdata, ssize_t size);
+ssize_t tmc_etr_read_sysfs_buf(struct etr_buf *sysfs_buf, loff_t pos,
+ size_t len, char **bufpp);
#endif
--
2.34.1
^ permalink raw reply related
* [PATCH v19 7/7] arm64: dts: qcom: lemans: add interrupts to CTCU device
From: Jie Gan @ 2026-06-25 10:45 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Alexander Shishkin, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jie Gan, Bjorn Andersson,
Konrad Dybcio, Yuanfang Zhang, Mao Jinlong
Cc: coresight, linux-arm-kernel, linux-kernel, linux-arm-msm,
devicetree, Konrad Dybcio
In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com>
Add interrupts to enable byte-cntr function for TMC ETR devices.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 353a6e6fd3ac..2b4debc39db0 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -3150,6 +3150,9 @@ ctcu@4001000 {
clocks = <&aoss_qmp>;
clock-names = "apb";
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
+
in-ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.34.1
^ permalink raw reply related
* [RFC PATCH 0/3] pinctrl: mediatek: mt8516-mt8167: Convert to Paris driver
From: Luca Leonardo Scorcia @ 2026-06-25 10:46 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Sean Wang, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel
The pinctrl registers of the mt8516 and mt8167 SoCs follow the layout of
the Paris platform, but their pinctrl driver is currently modeled on
the mt65xx legacy driver. As suggested in [1], it is possible to migrate
them to the Paris driver.
In the process it is also possible to completely drop one of the two
drivers as their register layout is identical, they only differ in some
pin functions (mt8167 is basically mt8516 with added display blocks).
The Paris driver allows specifying two base registers, gpio and eint;
this way it's no longer necessary to have a syscfg node in the device
tree, referenced as a phandle in the pinctrl node. This also fixes the
following long standing dtbs_check errors:
mt8167-pumpkin.dtb: syscfg-pctl@10005000 (syscon): compatible: ['syscon']
is too short
mt8516-pumpkin.dtb: syscfg-pctl@10005000 (syscon): compatible: ['syscon']
is too short
The new driver has been checked against the SoC data sheet and adds the
capability to control pin driving strength and R1R0 pullup-pulldown
resistors.
This series is sent as a RFC since the changes could theoretically impact
existing devices. I am pretty sure that no device ever used upstream
drivers though, not even the Pumpkin board that's present in Linux
sources since this board lacks the associated mt6392 PMIC driver that
is required for regulator management. If for compatibility reasons it is
deemed better to keep both drivers in the kernel I would welcome any
suggestion on how to name the new driver, and how to adjust the two
bindings for coexistence.
These changes have been tested on the Xiaomi Mi Smart Clock X04G and on
the Lenovo Smart Clock 2 CD-24502F.
[1] https://lore.kernel.org/linux-mediatek/296b000c-5970-4668-bd42-b99ca78d598f@collabora.com/
Luca Leonardo Scorcia (3):
dt-bindings: pinctrl: mt8516/mt8167: Move compatibles from mt66xx to
mt6795
pinctrl: mediatek: mt8516/mt8167: Migrate driver to pinctrl-paris
platform
arm64: dts: mt8516/mt8167: Update pinctrl nodes for the new paris
driver
.../pinctrl/mediatek,mt65xx-pinctrl.yaml | 2 -
.../pinctrl/mediatek,mt6795-pinctrl.yaml | 5 +-
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 15 +-
arch/arm64/boot/dts/mediatek/mt8516.dtsi | 12 +-
drivers/pinctrl/mediatek/Kconfig | 11 +-
drivers/pinctrl/mediatek/Makefile | 1 -
drivers/pinctrl/mediatek/pinctrl-mt8167.c | 345 --------
drivers/pinctrl/mediatek/pinctrl-mt8516.c | 770 +++++++++++-------
drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h | 562 +++++++------
drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h | 512 ++++++------
10 files changed, 1018 insertions(+), 1217 deletions(-)
delete mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8167.c
base-commit: 4e5dfb7c84012007c3c7061126491bbc92d71bf1
--
2.43.0
^ permalink raw reply
* [RFC PATCH 1/3] dt-bindings: pinctrl: mt8516/mt8167: Move compatibles from mt66xx to mt6795
From: Luca Leonardo Scorcia @ 2026-06-25 10:46 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Sean Wang, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20260625104742.113803-1-l.scorcia@gmail.com>
Pinctrl settings for MediaTek mt8516-mt8167 SoCs use two reg base
addresses, one for GPIO and the other for EINT, as it is common in the
"Paris" pinctrl platform that is described in the MediaTek mt6795 docs.
Move the binding compatible for these two SoCs from mt66xx to the mt6796
one as a prerequisite for migrating the pinctrl driver to the
pinctrl-paris platform.
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
---
.../devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 2 --
.../devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml | 5 ++++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
index 1468c6f87cfa..0cff2a352b1f 100644
--- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
@@ -22,9 +22,7 @@ properties:
- mediatek,mt7623-pinctrl
- mediatek,mt8127-pinctrl
- mediatek,mt8135-pinctrl
- - mediatek,mt8167-pinctrl
- mediatek,mt8173-pinctrl
- - mediatek,mt8516-pinctrl
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml
index 9a937f414cc9..c703de72e1d5 100644
--- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml
@@ -15,7 +15,10 @@ description:
properties:
compatible:
- const: mediatek,mt6795-pinctrl
+ enum:
+ - mediatek,mt6795-pinctrl
+ - mediatek,mt8167-pinctrl
+ - mediatek,mt8516-pinctrl
gpio-controller: true
--
2.43.0
^ permalink raw reply related
* [RFC PATCH 2/3] pinctrl: mediatek: mt8516/mt8167: Migrate driver to pinctrl-paris platform
From: Luca Leonardo Scorcia @ 2026-06-25 10:46 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Sean Wang, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20260625104742.113803-1-l.scorcia@gmail.com>
Migrate the mt8516/mt8167 pinctrl driver to the paris platform driver.
This change lets us correctly describe the two base addresses (GPIO/EINT)
used by the SoCs in their device tree. It also adds support for driving
strength capability and R1R0 pullup-pulldown on pins.
Since the driver for mt8167 pinctrl is identical to the mt8516 one except
for pin definitions there is no need for a separate driver, so drop it and
add a compatible to the other one.
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
---
drivers/pinctrl/mediatek/Kconfig | 11 +-
drivers/pinctrl/mediatek/Makefile | 1 -
drivers/pinctrl/mediatek/pinctrl-mt8167.c | 345 --------
drivers/pinctrl/mediatek/pinctrl-mt8516.c | 770 +++++++++++-------
drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h | 562 +++++++------
drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h | 512 ++++++------
6 files changed, 1006 insertions(+), 1195 deletions(-)
delete mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8167.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 97980cc28b9c..28edd53f12ed 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -214,13 +214,6 @@ config PINCTRL_MT7988
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_MOORE
-config PINCTRL_MT8167
- bool "MediaTek MT8167 pin control"
- depends on OF
- depends on ARM64 || COMPILE_TEST
- default ARM64 && ARCH_MEDIATEK
- select PINCTRL_MTK
-
config PINCTRL_MT8173
bool "MediaTek MT8173 pin control"
depends on OF
@@ -300,11 +293,11 @@ config PINCTRL_MT8365
select PINCTRL_MTK
config PINCTRL_MT8516
- bool "MediaTek MT8516 pin control"
+ bool "MediaTek MT8516/MT8167 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
- select PINCTRL_MTK
+ select PINCTRL_MTK_PARIS
# For PMIC
config PINCTRL_MT6397
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 6dc17b0c23f9..1533a93b14d3 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -30,7 +30,6 @@ obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
-obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c
deleted file mode 100644
index c812d614e9d4..000000000000
--- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c
+++ /dev/null
@@ -1,345 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2020 MediaTek Inc.
- * Author: Min.Guo <min.guo@mediatek.com>
- */
-
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <linux/of.h>
-#include <linux/module.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-
-#include "pinctrl-mtk-common.h"
-#include "pinctrl-mtk-mt8167.h"
-
-static const struct mtk_drv_group_desc mt8167_drv_grp[] = {
- /* 0E4E8SR 4/8/12/16 */
- MTK_DRV_GRP(4, 16, 1, 2, 4),
- /* 0E2E4SR 2/4/6/8 */
- MTK_DRV_GRP(2, 8, 1, 2, 2),
- /* E8E4E2 2/4/6/8/10/12/14/16 */
- MTK_DRV_GRP(2, 16, 0, 2, 2)
-};
-
-static const struct mtk_pin_drv_grp mt8167_pin_drv[] = {
- MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
-
- MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
-
- MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
- MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
- MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
-
- MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
-
- MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
- MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
- MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
-
- MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
-
- MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
- MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
-
- MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
-
- MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
- MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
- MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
-
- MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
- MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
-
- MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
- MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
- MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
- MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
-
- MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
-
- MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
- MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
- MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
-
- MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
- MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
- MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
- MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
-
- MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
- MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
- MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
- MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
-
- MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
-
- MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
- MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
- MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
-
- MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
-
- MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
-
- MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
-
- MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
- MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
- MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
- MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
-
- MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
- MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
- MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
- MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
-
- MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
-
- MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
-
- MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
- MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
- MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
- MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
-
- MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
-
- MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
-
- MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
-
- MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
-
- MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
-};
-
-static const struct mtk_pin_spec_pupd_set_samereg mt8167_spec_pupd[] = {
- MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
-
- MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
-
- MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
-
- MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
-
- MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
-};
-
-static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
- MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
- MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
- MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
- MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
- MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
- MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
- MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
- MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
- MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
- MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
- MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
- MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
- MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
- MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
- MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
- MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
- MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
- MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
- MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
- MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
- MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
- MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
- MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
- MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
- MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
- MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
- MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
- MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
- MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
- MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
- MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
- MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
- MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
- MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
- MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
- MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
- MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
- MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
- MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
- MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
- MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
- MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
- MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
- MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
- MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
-};
-
-static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
- MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
- MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
- MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
- MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
- MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
- MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
- MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
- MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
- MTK_PIN_IES_SMT_SPEC(34, 39, 0xA00, 2),
- MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
- MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
- MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
- MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
- MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
- MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
- MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
- MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
- MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
- MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
- MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
- MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
- MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
- MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
- MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
- MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
- MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
-
- MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
- MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
- MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
- MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
- MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
- MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
- MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
- MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
- MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
- MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
- MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
- MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
- MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
- MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
- MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
- MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
- MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
- MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
- MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
-};
-
-static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
- .pins = mtk_pins_mt8167,
- .npins = ARRAY_SIZE(mtk_pins_mt8167),
- .grp_desc = mt8167_drv_grp,
- .n_grp_cls = ARRAY_SIZE(mt8167_drv_grp),
- .pin_drv_grp = mt8167_pin_drv,
- .n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv),
- .spec_ies = mt8167_ies_set,
- .n_spec_ies = ARRAY_SIZE(mt8167_ies_set),
- .spec_pupd = mt8167_spec_pupd,
- .n_spec_pupd = ARRAY_SIZE(mt8167_spec_pupd),
- .spec_smt = mt8167_smt_set,
- .n_spec_smt = ARRAY_SIZE(mt8167_smt_set),
- .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
- .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
- .dir_offset = 0x0000,
- .pullen_offset = 0x0500,
- .pullsel_offset = 0x0600,
- .dout_offset = 0x0100,
- .din_offset = 0x0200,
- .pinmux_offset = 0x0300,
- .type1_start = 125,
- .type1_end = 125,
- .port_shf = 4,
- .port_mask = 0xf,
- .port_align = 4,
- .mode_mask = 0xf,
- .mode_per_reg = 5,
- .mode_shf = 4,
- .eint_hw = {
- .port_mask = 7,
- .ports = 6,
- .ap_num = 169,
- .db_cnt = 64,
- .db_time = debounce_time_mt6795,
- },
-};
-
-static const struct of_device_id mt8167_pctrl_match[] = {
- { .compatible = "mediatek,mt8167-pinctrl", .data = &mt8167_pinctrl_data },
- {}
-};
-
-MODULE_DEVICE_TABLE(of, mt8167_pctrl_match);
-
-static struct platform_driver mtk_pinctrl_driver = {
- .probe = mtk_pctrl_common_probe,
- .driver = {
- .name = "mediatek-mt8167-pinctrl",
- .of_match_table = mt8167_pctrl_match,
- .pm = pm_sleep_ptr(&mtk_eint_pm_ops),
- },
-};
-
-static int __init mtk_pinctrl_init(void)
-{
- return platform_driver_register(&mtk_pinctrl_driver);
-}
-arch_initcall(mtk_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
index 68d6638e7f4b..e00b5633bc67 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
@@ -1,345 +1,517 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2019 MediaTek Inc.
* Author: Min.Guo <min.guo@mediatek.com>
+ * Author: Luca Leonardo Scorcia <l.scorcia@gmail.com>
*/
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <linux/of.h>
-#include <linux/module.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-
-#include "pinctrl-mtk-common.h"
+#include "pinctrl-mtk-mt8167.h"
#include "pinctrl-mtk-mt8516.h"
+#include "pinctrl-paris.h"
-static const struct mtk_drv_group_desc mt8516_drv_grp[] = {
- /* 0E4E8SR 4/8/12/16 */
- MTK_DRV_GRP(4, 16, 1, 2, 4),
- /* 0E2E4SR 2/4/6/8 */
- MTK_DRV_GRP(2, 8, 1, 2, 2),
- /* E8E4E2 2/4/6/8/10/12/14/16 */
- MTK_DRV_GRP(2, 16, 0, 2, 2)
-};
-
-static const struct mtk_pin_drv_grp mt8516_pin_drv[] = {
- MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
- MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
-
- MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
- MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
-
- MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
- MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
- MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
-
- MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
-
- MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
- MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
- MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
-
- MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
- MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
-
- MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
- MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
+#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 15, 0)
- MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
- MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
+#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, 0)
- MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
- MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
- MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
+#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
+ PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, 1)
- MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
- MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
-
- MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
- MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
- MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
- MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
-
- MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
-
- MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
- MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
- MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
-
- MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
- MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
- MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
- MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
-
- MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
- MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
- MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
- MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
-
- MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
-
- MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
- MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
- MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
+static const struct mtk_pin_field_calc mt8516_pin_dir_range[] = {
+ PIN_FIELD16(0, 124, 0x000, 0x10, 0, 1),
+};
- MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
- MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
+static const struct mtk_pin_field_calc mt8516_pin_do_range[] = {
+ PIN_FIELD16(0, 124, 0x100, 0x10, 0, 1),
+};
- MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
+static const struct mtk_pin_field_calc mt8516_pin_di_range[] = {
+ PIN_FIELD16(0, 124, 0x200, 0x10, 0, 1),
+};
- MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
+static const struct mtk_pin_field_calc mt8516_pin_mode_range[] = {
+ PIN_FIELD15(0, 124, 0x300, 0x10, 0, 3),
+};
- MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
- MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
- MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
- MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
+static const struct mtk_pin_field_calc mt8516_pin_pullen_range[] = {
+ PIN_FIELD16(0, 124, 0x500, 0x10, 0, 1),
+};
- MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
- MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
- MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
- MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
+static const struct mtk_pin_field_calc mt8516_pin_pullsel_range[] = {
+ PIN_FIELD16(0, 124, 0x600, 0x10, 0, 1),
+};
- MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
+static const struct mtk_pin_field_calc mt8516_pin_ies_range[] = {
+ PINS_FIELD16(0, 6, 0x900, 0x10, 2, 1),
+ PINS_FIELD16(7, 10, 0x900, 0x10, 3, 1),
+ PINS_FIELD16(11, 13, 0x900, 0x10, 12, 1),
+ PINS_FIELD16(14, 17, 0x900, 0x10, 13, 1),
+ PINS_FIELD16(18, 20, 0x910, 0x10, 10, 1),
+ PINS_FIELD16(21, 23, 0x900, 0x10, 13, 1),
+ PINS_FIELD16(24, 25, 0x900, 0x10, 12, 1),
+ PINS_FIELD16(26, 30, 0x900, 0x10, 0, 1),
+ PINS_FIELD16(31, 33, 0x900, 0x10, 1, 1),
+ PINS_FIELD16(34, 39, 0x900, 0x10, 2, 1),
+ PIN_FIELD16(40, 40, 0x910, 0x10, 11, 1),
+ PINS_FIELD16(41, 43, 0x900, 0x10, 10, 1),
+ PINS_FIELD16(44, 47, 0x900, 0x10, 11, 1),
+ PINS_FIELD16(48, 51, 0x900, 0x10, 14, 1),
+ PINS_FIELD16(52, 53, 0x910, 0x10, 0, 1),
+ PIN_FIELD16(54, 54, 0x910, 0x10, 2, 1),
+ PINS_FIELD16(55, 57, 0x910, 0x10, 4, 1),
+ PINS_FIELD16(58, 59, 0x900, 0x10, 15, 1),
+ PINS_FIELD16(60, 61, 0x910, 0x10, 1, 1),
+ PINS_FIELD16(62, 65, 0x910, 0x10, 5, 1),
+ PINS_FIELD16(66, 67, 0x910, 0x10, 6, 1),
+ PIN_FIELD16(68, 68, 0x930, 0x10, 2, 1),
+ PIN_FIELD16(69, 69, 0x930, 0x10, 1, 1),
+ PIN_FIELD16(70, 70, 0x930, 0x10, 6, 1),
+ PIN_FIELD16(71, 71, 0x930, 0x10, 5, 1),
+ PIN_FIELD16(72, 72, 0x930, 0x10, 4, 1),
+ PIN_FIELD16(73, 73, 0x930, 0x10, 3, 1),
+ PINS_FIELD16(100, 103, 0x910, 0x10, 7, 1),
+ PIN_FIELD16(104, 104, 0x920, 0x10, 12, 1),
+ PIN_FIELD16(105, 105, 0x920, 0x10, 11, 1),
+ PIN_FIELD16(106, 106, 0x930, 0x10, 0, 1),
+ PIN_FIELD16(107, 107, 0x920, 0x10, 15, 1),
+ PIN_FIELD16(108, 108, 0x920, 0x10, 14, 1),
+ PIN_FIELD16(109, 109, 0x920, 0x10, 13, 1),
+ PIN_FIELD16(110, 110, 0x920, 0x10, 9, 1),
+ PIN_FIELD16(111, 111, 0x920, 0x10, 8, 1),
+ PIN_FIELD16(112, 112, 0x920, 0x10, 7, 1),
+ PIN_FIELD16(113, 113, 0x920, 0x10, 6, 1),
+ PIN_FIELD16(114, 114, 0x920, 0x10, 10, 1),
+ PIN_FIELD16(115, 115, 0x920, 0x10, 1, 1),
+ PIN_FIELD16(116, 116, 0x920, 0x10, 0, 1),
+ PIN_FIELD16(117, 117, 0x920, 0x10, 5, 1),
+ PIN_FIELD16(118, 118, 0x920, 0x10, 4, 1),
+ PIN_FIELD16(119, 119, 0x920, 0x10, 3, 1),
+ PIN_FIELD16(120, 120, 0x920, 0x10, 2, 1),
+ PINS_FIELD16(121, 124, 0x910, 0x10, 9, 1),
+};
- MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
+static const struct mtk_pin_field_calc mt8516_pin_smt_range[] = {
+ PINS_FIELD16(0, 6, 0xa00, 0x10, 2, 1),
+ PINS_FIELD16(7, 10, 0xa00, 0x10, 3, 1),
+ PINS_FIELD16(11, 13, 0xa00, 0x10, 12, 1),
+ PINS_FIELD16(14, 17, 0xa00, 0x10, 13, 1),
+ PINS_FIELD16(18, 20, 0xa10, 0x10, 10, 1),
+ PINS_FIELD16(21, 23, 0xa00, 0x10, 13, 1),
+ PINS_FIELD16(24, 25, 0xa00, 0x10, 12, 1),
+ PINS_FIELD16(26, 30, 0xa00, 0x10, 0, 1),
+ PINS_FIELD16(31, 33, 0xa00, 0x10, 1, 1),
+ PINS_FIELD16(34, 39, 0xa00, 0x10, 2, 1),
+ PIN_FIELD16(40, 40, 0xa10, 0x10, 11, 1),
+ PINS_FIELD16(41, 43, 0xa00, 0x10, 10, 1),
+ PINS_FIELD16(44, 47, 0xa00, 0x10, 11, 1),
+ PINS_FIELD16(48, 51, 0xa00, 0x10, 14, 1),
+ PINS_FIELD16(52, 53, 0xa10, 0x10, 0, 1),
+ PIN_FIELD16(54, 54, 0xa10, 0x10, 2, 1),
+ PINS_FIELD16(55, 57, 0xa10, 0x10, 4, 1),
+ PINS_FIELD16(58, 59, 0xa00, 0x10, 15, 1),
+ PINS_FIELD16(60, 61, 0xa10, 0x10, 1, 1),
+ PINS_FIELD16(62, 65, 0xa10, 0x10, 5, 1),
+ PINS_FIELD16(66, 67, 0xa10, 0x10, 6, 1),
+ PIN_FIELD16(68, 68, 0xa30, 0x10, 2, 1),
+ PIN_FIELD16(69, 69, 0xa30, 0x10, 1, 1),
+ PIN_FIELD16(70, 70, 0xa30, 0x10, 3, 1),
+ PIN_FIELD16(71, 71, 0xa30, 0x10, 4, 1),
+ PIN_FIELD16(72, 72, 0xa30, 0x10, 5, 1),
+ PIN_FIELD16(73, 73, 0xa30, 0x10, 6, 1),
+ PINS_FIELD16(100, 103, 0xa10, 0x10, 7, 1),
+ PIN_FIELD16(104, 104, 0xa20, 0x10, 12, 1),
+ PIN_FIELD16(105, 105, 0xa20, 0x10, 11, 1),
+ PIN_FIELD16(106, 106, 0xa20, 0x10, 13, 1),
+ PIN_FIELD16(107, 107, 0xa20, 0x10, 14, 1),
+ PIN_FIELD16(108, 108, 0xa20, 0x10, 15, 1),
+ PIN_FIELD16(109, 109, 0xa30, 0x10, 0, 1),
+ PIN_FIELD16(110, 110, 0xa20, 0x10, 9, 1),
+ PIN_FIELD16(111, 111, 0xa20, 0x10, 8, 1),
+ PIN_FIELD16(112, 112, 0xa20, 0x10, 7, 1),
+ PIN_FIELD16(113, 113, 0xa20, 0x10, 6, 1),
+ PIN_FIELD16(114, 114, 0xa20, 0x10, 10, 1),
+ PIN_FIELD16(115, 115, 0xa20, 0x10, 1, 1),
+ PIN_FIELD16(116, 116, 0xa20, 0x10, 0, 1),
+ PIN_FIELD16(117, 117, 0xa20, 0x10, 5, 1),
+ PIN_FIELD16(118, 118, 0xa20, 0x10, 4, 1),
+ PIN_FIELD16(119, 119, 0xa20, 0x10, 3, 1),
+ PIN_FIELD16(120, 120, 0xa20, 0x10, 2, 1),
+ PINS_FIELD16(121, 124, 0xa10, 0x10, 9, 1),
+};
- MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
- MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
- MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
- MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
+static const struct mtk_pin_field_calc mt8516_pin_pupd_range[] = {
+ /* EINT */
+ PIN_FIELD16(14, 14, 0xe50, 0x10, 14, 1), /* EINT14 */
+ PIN_FIELD16(15, 15, 0xe60, 0x10, 2, 1), /* EINT15 */
+ PIN_FIELD16(16, 16, 0xe60, 0x10, 6, 1), /* EINT16 */
+ PIN_FIELD16(17, 17, 0xe60, 0x10, 10, 1), /* EINT17 */
+ PIN_FIELD16(21, 21, 0xe60, 0x10, 14, 1), /* EINT21 */
+ PIN_FIELD16(22, 22, 0xe70, 0x10, 2, 1), /* EINT22 */
+ PIN_FIELD16(23, 23, 0xe70, 0x10, 6, 1), /* EINT23 */
+
+ /* KPROW */
+ PIN_FIELD16(40, 40, 0xe80, 0x10, 2, 1), /* KPROW0 */
+ PIN_FIELD16(41, 41, 0xe80, 0x10, 6, 1), /* KPROW1 */
+
+ PIN_FIELD16(42, 42, 0xe90, 0x10, 2, 1), /* KPCOL0 */
+ PIN_FIELD16(43, 43, 0xe90, 0x10, 6, 1), /* KPCOL1 */
+
+ /* MSDC2 */
+ PIN_FIELD16(68, 68, 0xe50, 0x10, 10, 1), /* MSDC2_CMD */
+ PIN_FIELD16(69, 69, 0xe50, 0x10, 6, 1), /* MSDC2_CLK */
+ PIN_FIELD16(70, 70, 0xe40, 0x10, 6, 1), /* MSDC2_DAT0 */
+ PIN_FIELD16(71, 71, 0xe40, 0x10, 10, 1), /* MSDC2_DAT1 */
+ PIN_FIELD16(72, 72, 0xe40, 0x10, 14, 1), /* MSDC2_DAT2 */
+ PIN_FIELD16(73, 73, 0xe50, 0x10, 2, 1), /* MSDC2_DAT3 */
+
+ /* MSDC1 */
+ PIN_FIELD16(104, 104, 0xe40, 0x10, 2, 1), /* MSDC1_CMD */
+ PIN_FIELD16(105, 105, 0xe30, 0x10, 14, 1), /* MSDC1_CLK */
+ PIN_FIELD16(106, 106, 0xe20, 0x10, 14, 1), /* MSDC1_DAT0 */
+ PIN_FIELD16(107, 107, 0xe30, 0x10, 2, 1), /* MSDC1_DAT1 */
+ PIN_FIELD16(108, 108, 0xe30, 0x10, 6, 1), /* MSDC1_DAT2 */
+ PIN_FIELD16(109, 109, 0xe30, 0x10, 10, 1), /* MSDC1_DAT3 */
+
+ /* MSDC0 */
+ PIN_FIELD16(110, 110, 0xe10, 0x10, 14, 1), /* MSDC0_DAT7 */
+ PIN_FIELD16(111, 111, 0xe10, 0x10, 10, 1), /* MSDC0_DAT6 */
+ PIN_FIELD16(112, 112, 0xe10, 0x10, 6, 1), /* MSDC0_DAT5 */
+ PIN_FIELD16(113, 113, 0xe10, 0x10, 2, 1), /* MSDC0_DAT4 */
+ PIN_FIELD16(114, 114, 0xe20, 0x10, 10, 1), /* MSDC0_RSTB */
+ PIN_FIELD16(115, 115, 0xe20, 0x10, 2, 1), /* MSDC0_CMD */
+ PIN_FIELD16(116, 116, 0xe20, 0x10, 6, 1), /* MSDC0_CLK */
+ PIN_FIELD16(117, 117, 0xe00, 0x10, 14, 1), /* MSDC0_DAT3 */
+ PIN_FIELD16(118, 118, 0xe00, 0x10, 10, 1), /* MSDC0_DAT2 */
+ PIN_FIELD16(119, 119, 0xe00, 0x10, 6, 1), /* MSDC0_DAT1 */
+ PIN_FIELD16(120, 120, 0xe00, 0x10, 2, 1), /* MSDC0_DAT0 */
+};
- MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
+static const struct mtk_pin_field_calc mt8516_pin_r0_range[] = {
+ /* EINT */
+ PIN_FIELD16(14, 14, 0xe50, 0x10, 12, 1), /* EINT14 */
+ PIN_FIELD16(15, 15, 0xe60, 0x10, 0, 1), /* EINT15 */
+ PIN_FIELD16(16, 16, 0xe60, 0x10, 4, 1), /* EINT16 */
+ PIN_FIELD16(17, 17, 0xe60, 0x10, 8, 1), /* EINT17 */
+ PIN_FIELD16(21, 21, 0xe60, 0x10, 12, 1), /* EINT21 */
+ PIN_FIELD16(22, 22, 0xe70, 0x10, 0, 1), /* EINT22 */
+ PIN_FIELD16(23, 23, 0xe70, 0x10, 4, 1), /* EINT23 */
+
+ /* KPROW */
+ PIN_FIELD16(40, 40, 0xe80, 0x10, 0, 1), /* KPROW0 */
+ PIN_FIELD16(41, 41, 0xe80, 0x10, 4, 1), /* KPROW1 */
+ PIN_FIELD16(42, 42, 0xe90, 0x10, 0, 1), /* KPCOL0 */
+ PIN_FIELD16(43, 43, 0xe90, 0x10, 4, 1), /* KPCOL1 */
+
+ /* MSDC2 */
+ PIN_FIELD16(68, 68, 0xe50, 0x10, 8, 1), /* MSDC2_CMD */
+ PIN_FIELD16(69, 69, 0xe50, 0x10, 4, 1), /* MSDC2_CLK */
+ PIN_FIELD16(70, 70, 0xe40, 0x10, 4, 1), /* MSDC2_DAT0 */
+ PIN_FIELD16(71, 71, 0xe40, 0x10, 8, 1), /* MSDC2_DAT1 */
+ PIN_FIELD16(72, 72, 0xe40, 0x10, 12, 1), /* MSDC2_DAT2 */
+ PIN_FIELD16(73, 73, 0xe50, 0x10, 0, 1), /* MSDC2_DAT3 */
+
+ /* MSDC1 */
+ PIN_FIELD16(104, 104, 0xe40, 0x10, 0, 1), /* MSDC1_CMD */
+ PIN_FIELD16(105, 105, 0xe30, 0x10, 12, 1), /* MSDC1_CLK */
+ PIN_FIELD16(106, 106, 0xe20, 0x10, 12, 1), /* MSDC1_DAT0 */
+ PIN_FIELD16(107, 107, 0xe30, 0x10, 0, 1), /* MSDC1_DAT1 */
+ PIN_FIELD16(108, 108, 0xe30, 0x10, 4, 1), /* MSDC1_DAT2 */
+ PIN_FIELD16(109, 109, 0xe30, 0x10, 8, 1), /* MSDC1_DAT3 */
+
+ /* MSDC0 */
+ PIN_FIELD16(110, 110, 0xe10, 0x10, 12, 1), /* MSDC0_DAT7 */
+ PIN_FIELD16(111, 111, 0xe10, 0x10, 8, 1), /* MSDC0_DAT6 */
+ PIN_FIELD16(112, 112, 0xe10, 0x10, 4, 1), /* MSDC0_DAT5 */
+ PIN_FIELD16(113, 113, 0xe10, 0x10, 0, 1), /* MSDC0_DAT4 */
+ PIN_FIELD16(114, 114, 0xe20, 0x10, 8, 1), /* MSDC0_RSTB */
+ PIN_FIELD16(115, 115, 0xe20, 0x10, 0, 1), /* MSDC0_CMD */
+ PIN_FIELD16(116, 116, 0xe20, 0x10, 4, 1), /* MSDC0_CLK */
+ PIN_FIELD16(117, 117, 0xe00, 0x10, 12, 1), /* MSDC0_DAT3 */
+ PIN_FIELD16(118, 118, 0xe00, 0x10, 8, 1), /* MSDC0_DAT2 */
+ PIN_FIELD16(119, 119, 0xe00, 0x10, 4, 1), /* MSDC0_DAT1 */
+ PIN_FIELD16(120, 120, 0xe00, 0x10, 0, 1), /* MSDC0_DAT0 */
+};
- MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
+static const struct mtk_pin_field_calc mt8516_pin_r1_range[] = {
+ /* EINT */
+ PIN_FIELD16(14, 14, 0xe50, 0x10, 13, 1), /* EINT14 */
+ PIN_FIELD16(15, 15, 0xe60, 0x10, 1, 1), /* EINT15 */
+ PIN_FIELD16(16, 16, 0xe60, 0x10, 5, 1), /* EINT16 */
+ PIN_FIELD16(17, 17, 0xe60, 0x10, 9, 1), /* EINT17 */
+ PIN_FIELD16(21, 21, 0xe60, 0x10, 13, 1), /* EINT21 */
+ PIN_FIELD16(22, 22, 0xe70, 0x10, 1, 1), /* EINT22 */
+ PIN_FIELD16(23, 23, 0xe70, 0x10, 5, 1), /* EINT23 */
+
+ /* KPROW */
+ PIN_FIELD16(40, 40, 0xe80, 0x10, 1, 1), /* KPROW0 */
+ PIN_FIELD16(41, 41, 0xe80, 0x10, 5, 1), /* KPROW1 */
+ PIN_FIELD16(42, 42, 0xe90, 0x10, 1, 1), /* KPCOL0 */
+ PIN_FIELD16(43, 43, 0xe90, 0x10, 5, 1), /* KPCOL1 */
+
+ /* MSDC2 */
+ PIN_FIELD16(68, 68, 0xe50, 0x10, 9, 1), /* MSDC2_CMD */
+ PIN_FIELD16(69, 69, 0xe50, 0x10, 5, 1), /* MSDC2_CLK */
+ PIN_FIELD16(70, 70, 0xe40, 0x10, 5, 1), /* MSDC2_DAT0 */
+ PIN_FIELD16(71, 71, 0xe40, 0x10, 9, 1), /* MSDC2_DAT1 */
+ PIN_FIELD16(72, 72, 0xe40, 0x10, 13, 1), /* MSDC2_DAT2 */
+ PIN_FIELD16(73, 73, 0xe50, 0x10, 1, 1), /* MSDC2_DAT3 */
+
+ /* MSDC1 */
+ PIN_FIELD16(104, 104, 0xe40, 0x10, 1, 1), /* MSDC1_CMD */
+ PIN_FIELD16(105, 105, 0xe30, 0x10, 13, 1), /* MSDC1_CLK */
+ PIN_FIELD16(106, 106, 0xe20, 0x10, 13, 1), /* MSDC1_DAT0 */
+ PIN_FIELD16(107, 107, 0xe30, 0x10, 1, 1), /* MSDC1_DAT1 */
+ PIN_FIELD16(108, 108, 0xe30, 0x10, 5, 1), /* MSDC1_DAT2 */
+ PIN_FIELD16(109, 109, 0xe30, 0x10, 9, 1), /* MSDC1_DAT3 */
+
+ /* MSDC0 */
+ PIN_FIELD16(110, 110, 0xe10, 0x10, 13, 1), /* MSDC0_DAT7 */
+ PIN_FIELD16(111, 111, 0xe10, 0x10, 9, 1), /* MSDC0_DAT6 */
+ PIN_FIELD16(112, 112, 0xe10, 0x10, 5, 1), /* MSDC0_DAT5 */
+ PIN_FIELD16(113, 113, 0xe10, 0x10, 1, 1), /* MSDC0_DAT4 */
+ PIN_FIELD16(114, 114, 0xe20, 0x10, 9, 1), /* MSDC0_RSTB */
+ PIN_FIELD16(115, 115, 0xe20, 0x10, 1, 1), /* MSDC0_CMD */
+ PIN_FIELD16(116, 116, 0xe20, 0x10, 5, 1), /* MSDC0_CLK */
+ PIN_FIELD16(117, 117, 0xe00, 0x10, 13, 1), /* MSDC0_DAT3 */
+ PIN_FIELD16(118, 118, 0xe00, 0x10, 9, 1), /* MSDC0_DAT2 */
+ PIN_FIELD16(119, 119, 0xe00, 0x10, 5, 1), /* MSDC0_DAT1 */
+ PIN_FIELD16(120, 120, 0xe00, 0x10, 1, 1), /* MSDC0_DAT0 */
+};
- MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
+static const struct mtk_pin_field_calc mt8516_pin_drv_range[] = {
+ PINS_FIELD16(0, 4, 0xd00, 0x10, 0, 2),
+ PINS_FIELD16(5, 10, 0xd00, 0x10, 4, 2),
+ PINS_FIELD16(11, 13, 0xd00, 0x10, 8, 2),
+ PINS_FIELD16(14, 17, 0xd00, 0x10, 12, 2),
+ PINS_FIELD16(18, 20, 0xd10, 0x10, 0, 2),
+ PINS_FIELD16(21, 23, 0xd00, 0x10, 12, 2),
+ PINS_FIELD16(24, 25, 0xd00, 0x10, 8, 2),
+ PINS_FIELD16(26, 30, 0xd10, 0x10, 4, 2),
+ PINS_FIELD16(31, 33, 0xd10, 0x10, 8, 2),
+ PINS_FIELD16(34, 35, 0xd10, 0x10, 12, 2),
+ PINS_FIELD16(36, 39, 0xd20, 0x10, 0, 2),
+ PIN_FIELD16(40, 40, 0xd20, 0x10, 4, 2),
+ PINS_FIELD16(41, 43, 0xd20, 0x10, 8, 2),
+ PINS_FIELD16(44, 47, 0xd20, 0x10, 12, 2),
+ PINS_FIELD16(48, 51, 0xd30, 0x10, 12, 2),
+
+ PIN_FIELD16(54, 54, 0xd30, 0x10, 8, 2),
+ PINS_FIELD16(55, 57, 0xd30, 0x10, 0, 2),
+
+ PINS_FIELD16(62, 67, 0xd40, 0x10, 8, 2),
+ PIN_FIELD16(68, 68, 0xd40, 0x10, 12, 2),
+ PIN_FIELD16(69, 69, 0xd50, 0x10, 0, 2),
+ PINS_FIELD16(70, 73, 0xd50, 0x10, 4, 2),
+
+ PINS_FIELD16(100, 103, 0xd50, 0x10, 8, 2),
+ PIN_FIELD16(104, 104, 0xd50, 0x10, 12, 2),
+ PIN_FIELD16(105, 105, 0xd60, 0x10, 0, 2),
+ PINS_FIELD16(106, 109, 0xd60, 0x10, 4, 2),
+ PINS_FIELD16(110, 113, 0xd70, 0x10, 0, 2),
+ PIN_FIELD16(114, 114, 0xd70, 0x10, 4, 2),
+ PIN_FIELD16(115, 115, 0xd60, 0x10, 12, 2),
+ PIN_FIELD16(116, 116, 0xd60, 0x10, 8, 2),
+ PINS_FIELD16(117, 120, 0xd70, 0x10, 0, 2),
+};
- MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
+static const struct mtk_pin_field_calc mt8516_pin_sr_range[] = {
+ PINS_FIELD16(0, 4, 0xd00, 0x10, 3, 1),
+ PINS_FIELD16(5, 10, 0xd00, 0x10, 7, 1),
+ PINS_FIELD16(11, 13, 0xd00, 0x10, 11, 1),
+ PINS_FIELD16(14, 17, 0xd00, 0x10, 15, 1),
+ PINS_FIELD16(18, 20, 0xd10, 0x10, 3, 1),
+ PINS_FIELD16(21, 23, 0xd00, 0x10, 15, 1),
+ PINS_FIELD16(24, 25, 0xd00, 0x10, 11, 1),
+ PINS_FIELD16(26, 30, 0xd10, 0x10, 7, 1),
+ PINS_FIELD16(31, 33, 0xd10, 0x10, 11, 1),
+ PINS_FIELD16(34, 35, 0xd10, 0x10, 15, 1),
+ PINS_FIELD16(36, 39, 0xd20, 0x10, 3, 1),
+ PIN_FIELD16(40, 40, 0xd20, 0x10, 7, 1),
+ PINS_FIELD16(41, 43, 0xd20, 0x10, 11, 1),
+ PINS_FIELD16(44, 47, 0xd20, 0x10, 15, 1),
+ PINS_FIELD16(48, 51, 0xd30, 0x10, 15, 1),
+
+ PIN_FIELD16(54, 54, 0xd30, 0x10, 11, 1),
+ PINS_FIELD16(55, 57, 0xd30, 0x10, 3, 1),
+
+ PINS_FIELD16(62, 67, 0xd40, 0x10, 11, 1),
+ PIN_FIELD16(68, 68, 0xd40, 0x10, 15, 1),
+ PIN_FIELD16(69, 69, 0xd50, 0x10, 3, 1),
+ PINS_FIELD16(70, 73, 0xd50, 0x10, 7, 1),
+
+ PINS_FIELD16(100, 103, 0xd50, 0x10, 11, 1),
+ PIN_FIELD16(104, 104, 0xd50, 0x10, 15, 1),
+ PIN_FIELD16(105, 105, 0xd60, 0x10, 3, 1),
+ PINS_FIELD16(106, 109, 0xd60, 0x10, 7, 1),
+ PINS_FIELD16(110, 113, 0xd70, 0x10, 3, 1),
+ PIN_FIELD16(114, 114, 0xd70, 0x10, 7, 1),
+ PIN_FIELD16(115, 115, 0xd60, 0x10, 15, 1),
+ PIN_FIELD16(116, 116, 0xd60, 0x10, 11, 1),
+ PINS_FIELD16(117, 120, 0xd70, 0x10, 3, 1),
+};
- MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
- MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
+static const struct mtk_pin_reg_calc mt8516_reg_cals[PINCTRL_PIN_REG_MAX] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8516_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8516_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8516_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8516_pin_do_range),
+ [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt8516_pin_sr_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8516_pin_smt_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8516_pin_drv_range),
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8516_pin_pupd_range),
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8516_pin_r0_range),
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8516_pin_r1_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8516_pin_ies_range),
+ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8516_pin_pullen_range),
+ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8516_pin_pullsel_range),
};
-static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = {
- MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
-
- MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
-
- MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
-
- MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
-
- MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
- MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
- MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
- MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
- MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
+static const struct mtk_eint_hw mt8516_eint_hw = {
+ .port_mask = 7,
+ .ports = 6,
+ .ap_num = 169,
+ .db_cnt = 64,
+ .db_time = debounce_time_mt6795,
};
-static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
- MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
- MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
- MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
- MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
- MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
- MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
- MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
- MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
- MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
- MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
- MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
- MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
- MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
- MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
- MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
- MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
- MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
- MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
- MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
- MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
- MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
- MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
- MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
- MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
- MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
- MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
- MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
- MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
- MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
- MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
- MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
- MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
- MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
- MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
- MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
- MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
- MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
- MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
- MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
- MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
- MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
- MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
- MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
- MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
- MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
+static const unsigned int mt8516_pull_type[] = {
+ MTK_PULL_PULLSEL_TYPE,/*0*/ MTK_PULL_PULLSEL_TYPE,/*1*/
+ MTK_PULL_PULLSEL_TYPE,/*2*/ MTK_PULL_PULLSEL_TYPE,/*3*/
+ MTK_PULL_PULLSEL_TYPE,/*4*/ MTK_PULL_PULLSEL_TYPE,/*5*/
+ MTK_PULL_PULLSEL_TYPE,/*6*/ MTK_PULL_PULLSEL_TYPE,/*7*/
+ MTK_PULL_PULLSEL_TYPE,/*8*/ MTK_PULL_PULLSEL_TYPE,/*9*/
+ MTK_PULL_PULLSEL_TYPE,/*10*/ MTK_PULL_PULLSEL_TYPE,/*11*/
+ MTK_PULL_PULLSEL_TYPE,/*12*/ MTK_PULL_PULLSEL_TYPE,/*13*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
+ MTK_PULL_PULLSEL_TYPE,/*18*/ MTK_PULL_PULLSEL_TYPE,/*19*/
+ MTK_PULL_PULLSEL_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
+ MTK_PULL_PULLSEL_TYPE,/*24*/ MTK_PULL_PULLSEL_TYPE,/*25*/
+ MTK_PULL_PULLSEL_TYPE,/*26*/ MTK_PULL_PULLSEL_TYPE,/*27*/
+ MTK_PULL_PULLSEL_TYPE,/*28*/ MTK_PULL_PULLSEL_TYPE,/*29*/
+ MTK_PULL_PULLSEL_TYPE,/*30*/ MTK_PULL_PULLSEL_TYPE,/*31*/
+ MTK_PULL_PULLSEL_TYPE,/*32*/ MTK_PULL_PULLSEL_TYPE,/*33*/
+ MTK_PULL_PULLSEL_TYPE,/*34*/ MTK_PULL_PULLSEL_TYPE,/*35*/
+ MTK_PULL_PULLSEL_TYPE,/*36*/ MTK_PULL_PULLSEL_TYPE,/*37*/
+ MTK_PULL_PULLSEL_TYPE,/*38*/ MTK_PULL_PULLSEL_TYPE,/*39*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
+ MTK_PULL_PULLSEL_TYPE,/*44*/ MTK_PULL_PULLSEL_TYPE,/*45*/
+ MTK_PULL_PULLSEL_TYPE,/*46*/ MTK_PULL_PULLSEL_TYPE,/*47*/
+ MTK_PULL_PULLSEL_TYPE,/*48*/ MTK_PULL_PULLSEL_TYPE,/*49*/
+ MTK_PULL_PULLSEL_TYPE,/*50*/ MTK_PULL_PULLSEL_TYPE,/*51*/
+ MTK_PULL_PULLSEL_TYPE,/*52*/ MTK_PULL_PULLSEL_TYPE,/*53*/
+ MTK_PULL_PULLSEL_TYPE,/*54*/ MTK_PULL_PULLSEL_TYPE,/*55*/
+ MTK_PULL_PULLSEL_TYPE,/*56*/ MTK_PULL_PULLSEL_TYPE,/*57*/
+ MTK_PULL_PULLSEL_TYPE,/*58*/ MTK_PULL_PULLSEL_TYPE,/*59*/
+ MTK_PULL_PULLSEL_TYPE,/*60*/ MTK_PULL_PULLSEL_TYPE,/*61*/
+ MTK_PULL_PULLSEL_TYPE,/*62*/ MTK_PULL_PULLSEL_TYPE,/*63*/
+ MTK_PULL_PULLSEL_TYPE,/*64*/ MTK_PULL_PULLSEL_TYPE,/*65*/
+ MTK_PULL_PULLSEL_TYPE,/*66*/ MTK_PULL_PULLSEL_TYPE,/*67*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PUPD_R1R0_TYPE,/*71*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/
+ MTK_PULL_PULLSEL_TYPE,/*74*/ MTK_PULL_PULLSEL_TYPE,/*75*/
+ MTK_PULL_PULLSEL_TYPE,/*76*/ MTK_PULL_PULLSEL_TYPE,/*77*/
+ MTK_PULL_PULLSEL_TYPE,/*78*/ MTK_PULL_PULLSEL_TYPE,/*79*/
+ MTK_PULL_PULLSEL_TYPE,/*80*/ MTK_PULL_PULLSEL_TYPE,/*81*/
+ MTK_PULL_PULLSEL_TYPE,/*82*/ MTK_PULL_PULLSEL_TYPE,/*83*/
+ MTK_PULL_PULLSEL_TYPE,/*84*/ MTK_PULL_PULLSEL_TYPE,/*85*/
+ MTK_PULL_PULLSEL_TYPE,/*86*/ MTK_PULL_PULLSEL_TYPE,/*87*/
+ MTK_PULL_PULLSEL_TYPE,/*88*/ MTK_PULL_PULLSEL_TYPE,/*89*/
+ MTK_PULL_PULLSEL_TYPE,/*90*/ MTK_PULL_PULLSEL_TYPE,/*91*/
+ MTK_PULL_PULLSEL_TYPE,/*92*/ MTK_PULL_PULLSEL_TYPE,/*93*/
+ MTK_PULL_PULLSEL_TYPE,/*94*/ MTK_PULL_PULLSEL_TYPE,/*95*/
+ MTK_PULL_PULLSEL_TYPE,/*96*/ MTK_PULL_PULLSEL_TYPE,/*97*/
+ MTK_PULL_PULLSEL_TYPE,/*98*/ MTK_PULL_PULLSEL_TYPE,/*99*/
+ MTK_PULL_PULLSEL_TYPE,/*100*/ MTK_PULL_PULLSEL_TYPE,/*101*/
+ MTK_PULL_PULLSEL_TYPE,/*102*/ MTK_PULL_PULLSEL_TYPE,/*103*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*104*/ MTK_PULL_PUPD_R1R0_TYPE,/*105*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*106*/ MTK_PULL_PUPD_R1R0_TYPE,/*107*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*108*/ MTK_PULL_PUPD_R1R0_TYPE,/*109*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*110*/ MTK_PULL_PUPD_R1R0_TYPE,/*111*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*112*/ MTK_PULL_PUPD_R1R0_TYPE,/*113*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*114*/ MTK_PULL_PUPD_R1R0_TYPE,/*115*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*116*/ MTK_PULL_PUPD_R1R0_TYPE,/*117*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*118*/ MTK_PULL_PUPD_R1R0_TYPE,/*119*/
+ MTK_PULL_PUPD_R1R0_TYPE,/*120*/ MTK_PULL_PULLSEL_TYPE,/*121*/
+ MTK_PULL_PULLSEL_TYPE,/*122*/ MTK_PULL_PULLSEL_TYPE,/*123*/
+ MTK_PULL_PULLSEL_TYPE,/*124*/
};
-static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
- MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
- MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
- MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
- MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
- MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
- MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
- MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
- MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
- MTK_PIN_IES_SMT_SPEC(34, 39, 0xA00, 2),
- MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
- MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
- MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
- MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
- MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
- MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
- MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
- MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
- MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
- MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
- MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
- MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
- MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
- MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
- MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
- MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
- MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
-
- MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
- MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
- MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
- MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
- MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
- MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
- MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
- MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
- MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
- MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
- MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
- MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
- MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
- MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
- MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
- MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
- MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
- MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
- MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
+static const struct mtk_pin_soc mt8167_pinctrl_data = {
+ .reg_cal = mt8516_reg_cals,
+ .pins = mtk_pins_mt8167,
+ .npins = ARRAY_SIZE(mtk_pins_mt8167),
+ .ngrps = ARRAY_SIZE(mtk_pins_mt8167),
+ .nfuncs = 8,
+ .eint_hw = &mt8516_eint_hw,
+ .gpio_m = 0,
+ .ies_present = true,
+ .base_names = mtk_default_register_base_names,
+ .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
+ .pull_type = mt8516_pull_type,
+ .bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
+ .bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
+ .bias_set = mtk_pinconf_bias_set_rev1,
+ .bias_get = mtk_pinconf_bias_get_rev1,
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+ .adv_pull_get = mtk_pinconf_adv_pull_get,
+ .adv_pull_set = mtk_pinconf_adv_pull_set,
};
-static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
+static const struct mtk_pin_soc mt8516_pinctrl_data = {
+ .reg_cal = mt8516_reg_cals,
.pins = mtk_pins_mt8516,
.npins = ARRAY_SIZE(mtk_pins_mt8516),
- .grp_desc = mt8516_drv_grp,
- .n_grp_cls = ARRAY_SIZE(mt8516_drv_grp),
- .pin_drv_grp = mt8516_pin_drv,
- .n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv),
- .spec_ies = mt8516_ies_set,
- .n_spec_ies = ARRAY_SIZE(mt8516_ies_set),
- .spec_pupd = mt8516_spec_pupd,
- .n_spec_pupd = ARRAY_SIZE(mt8516_spec_pupd),
- .spec_smt = mt8516_smt_set,
- .n_spec_smt = ARRAY_SIZE(mt8516_smt_set),
- .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
- .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
- .dir_offset = 0x0000,
- .pullen_offset = 0x0500,
- .pullsel_offset = 0x0600,
- .dout_offset = 0x0100,
- .din_offset = 0x0200,
- .pinmux_offset = 0x0300,
- .type1_start = 125,
- .type1_end = 125,
- .port_shf = 4,
- .port_mask = 0xf,
- .port_align = 4,
- .mode_mask = 0xf,
- .mode_per_reg = 5,
- .mode_shf = 4,
- .eint_hw = {
- .port_mask = 7,
- .ports = 6,
- .ap_num = 169,
- .db_cnt = 64,
- .db_time = debounce_time_mt6795,
- },
+ .ngrps = ARRAY_SIZE(mtk_pins_mt8516),
+ .nfuncs = 8,
+ .eint_hw = &mt8516_eint_hw,
+ .gpio_m = 0,
+ .ies_present = true,
+ .base_names = mtk_default_register_base_names,
+ .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
+ .pull_type = mt8516_pull_type,
+ .bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
+ .bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
+ .bias_set = mtk_pinconf_bias_set_rev1,
+ .bias_get = mtk_pinconf_bias_get_rev1,
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+ .adv_pull_get = mtk_pinconf_adv_pull_get,
+ .adv_pull_set = mtk_pinconf_adv_pull_set,
};
-static const struct of_device_id mt8516_pctrl_match[] = {
+static const struct of_device_id mt8516_pinctrl_of_match[] = {
+ { .compatible = "mediatek,mt8167-pinctrl", .data = &mt8167_pinctrl_data },
{ .compatible = "mediatek,mt8516-pinctrl", .data = &mt8516_pinctrl_data },
{}
};
+MODULE_DEVICE_TABLE(of, mt8516_pinctrl_of_match);
-MODULE_DEVICE_TABLE(of, mt8516_pctrl_match);
-
-static struct platform_driver mtk_pinctrl_driver = {
- .probe = mtk_pctrl_common_probe,
+static struct platform_driver mt8516_pinctrl_driver = {
.driver = {
.name = "mediatek-mt8516-pinctrl",
- .of_match_table = mt8516_pctrl_match,
- .pm = pm_sleep_ptr(&mtk_eint_pm_ops),
+ .of_match_table = mt8516_pinctrl_of_match,
+ .pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops),
},
+ .probe = mtk_paris_pinctrl_probe,
};
-static int __init mtk_pinctrl_init(void)
+static int __init mt8516_pinctrl_init(void)
{
- return platform_driver_register(&mtk_pinctrl_driver);
+ return platform_driver_register(&mt8516_pinctrl_driver);
}
-arch_initcall(mtk_pinctrl_init);
+arch_initcall(mt8516_pinctrl_init);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek MT8516/MT8167 Pinctrl Driver");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h
index 225c41fc9b75..d0c603838644 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h
@@ -1,18 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2020 MediaTek Inc.
- */
#ifndef __PINCTRL_MTK_MT8167_H
#define __PINCTRL_MTK_MT8167_H
-#include <linux/pinctrl/pinctrl.h>
-#include "pinctrl-mtk-common.h"
+#include "pinctrl-paris.h"
-static const struct mtk_desc_pin mtk_pins_mt8167[] = {
+static const struct mtk_pin_desc mtk_pins_mt8167[] = {
MTK_PIN(
- PINCTRL_PIN(0, "EINT0"),
- NULL, "mt8167",
+ 0, "EINT0",
MTK_EINT_FUNCTION(0, 0),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO0"),
MTK_FUNCTION(1, "PWM_B"),
MTK_FUNCTION(2, "DPI_CK"),
@@ -22,9 +18,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[6]")
),
MTK_PIN(
- PINCTRL_PIN(1, "EINT1"),
- NULL, "mt8167",
+ 1, "EINT1",
MTK_EINT_FUNCTION(0, 1),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO1"),
MTK_FUNCTION(1, "PWM_C"),
MTK_FUNCTION(2, "DPI_D12"),
@@ -35,9 +31,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[7]")
),
MTK_PIN(
- PINCTRL_PIN(2, "EINT2"),
- NULL, "mt8167",
+ 2, "EINT2",
MTK_EINT_FUNCTION(0, 2),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO2"),
MTK_FUNCTION(1, "CLKM0"),
MTK_FUNCTION(2, "DPI_D13"),
@@ -48,9 +44,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[8]")
),
MTK_PIN(
- PINCTRL_PIN(3, "EINT3"),
- NULL, "mt8167",
+ 3, "EINT3",
MTK_EINT_FUNCTION(0, 3),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO3"),
MTK_FUNCTION(1, "CLKM1"),
MTK_FUNCTION(2, "DPI_D14"),
@@ -61,9 +57,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[9]")
),
MTK_PIN(
- PINCTRL_PIN(4, "EINT4"),
- NULL, "mt8167",
+ 4, "EINT4",
MTK_EINT_FUNCTION(0, 4),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO4"),
MTK_FUNCTION(1, "CLKM2"),
MTK_FUNCTION(2, "DPI_D15"),
@@ -74,9 +70,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[10]")
),
MTK_PIN(
- PINCTRL_PIN(5, "EINT5"),
- NULL, "mt8167",
+ 5, "EINT5",
MTK_EINT_FUNCTION(0, 5),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO5"),
MTK_FUNCTION(1, "UCTS2"),
MTK_FUNCTION(2, "DPI_D16"),
@@ -87,9 +83,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[11]")
),
MTK_PIN(
- PINCTRL_PIN(6, "EINT6"),
- NULL, "mt8167",
+ 6, "EINT6",
MTK_EINT_FUNCTION(0, 6),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO6"),
MTK_FUNCTION(1, "URTS2"),
MTK_FUNCTION(2, "DPI_D17"),
@@ -100,9 +96,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[12]")
),
MTK_PIN(
- PINCTRL_PIN(7, "EINT7"),
- NULL, "mt8167",
+ 7, "EINT7",
MTK_EINT_FUNCTION(0, 7),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO7"),
MTK_FUNCTION(1, "SQIRST"),
MTK_FUNCTION(2, "DPI_D6"),
@@ -113,9 +109,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[13]")
),
MTK_PIN(
- PINCTRL_PIN(8, "EINT8"),
- NULL, "mt8167",
+ 8, "EINT8",
MTK_EINT_FUNCTION(0, 8),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO8"),
MTK_FUNCTION(1, "SQICK"),
MTK_FUNCTION(2, "CLKM3"),
@@ -126,9 +122,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[14]")
),
MTK_PIN(
- PINCTRL_PIN(9, "EINT9"),
- NULL, "mt8167",
+ 9, "EINT9",
MTK_EINT_FUNCTION(0, 9),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO9"),
MTK_FUNCTION(1, "CLKM4"),
MTK_FUNCTION(2, "SDA2_0"),
@@ -139,9 +135,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[15]")
),
MTK_PIN(
- PINCTRL_PIN(10, "EINT10"),
- NULL, "mt8167",
+ 10, "EINT10",
MTK_EINT_FUNCTION(0, 10),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO10"),
MTK_FUNCTION(1, "CLKM5"),
MTK_FUNCTION(2, "SCL2_0"),
@@ -152,9 +148,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[16]")
),
MTK_PIN(
- PINCTRL_PIN(11, "EINT11"),
- NULL, "mt8167",
+ 11, "EINT11",
MTK_EINT_FUNCTION(0, 11),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO11"),
MTK_FUNCTION(1, "CLKM4"),
MTK_FUNCTION(2, "PWM_C"),
@@ -165,9 +161,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[17]")
),
MTK_PIN(
- PINCTRL_PIN(12, "EINT12"),
- NULL, "mt8167",
+ 12, "EINT12",
MTK_EINT_FUNCTION(0, 12),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO12"),
MTK_FUNCTION(1, "CLKM5"),
MTK_FUNCTION(2, "PWM_A"),
@@ -178,9 +174,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[18]")
),
MTK_PIN(
- PINCTRL_PIN(13, "EINT13"),
- NULL, "mt8167",
+ 13, "EINT13",
MTK_EINT_FUNCTION(0, 13),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO13"),
MTK_FUNCTION(3, "TSF_IN"),
MTK_FUNCTION(4, "ANT_SEL5"),
@@ -189,9 +185,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[19]")
),
MTK_PIN(
- PINCTRL_PIN(14, "EINT14"),
- NULL, "mt8167",
+ 14, "EINT14",
MTK_EINT_FUNCTION(0, 14),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO14"),
MTK_FUNCTION(2, "I2S_8CH_DO1"),
MTK_FUNCTION(3, "TDM_RX_MCK"),
@@ -201,9 +197,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[8]")
),
MTK_PIN(
- PINCTRL_PIN(15, "EINT15"),
- NULL, "mt8167",
+ 15, "EINT15",
MTK_EINT_FUNCTION(0, 15),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO15"),
MTK_FUNCTION(2, "I2S_8CH_LRCK"),
MTK_FUNCTION(3, "TDM_RX_BCK"),
@@ -213,9 +209,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[9]")
),
MTK_PIN(
- PINCTRL_PIN(16, "EINT16"),
- NULL, "mt8167",
+ 16, "EINT16",
MTK_EINT_FUNCTION(0, 16),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO16"),
MTK_FUNCTION(2, "I2S_8CH_BCK"),
MTK_FUNCTION(3, "TDM_RX_LRCK"),
@@ -225,9 +221,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[10]")
),
MTK_PIN(
- PINCTRL_PIN(17, "EINT17"),
- NULL, "mt8167",
+ 17, "EINT17",
MTK_EINT_FUNCTION(0, 17),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO17"),
MTK_FUNCTION(2, "I2S_8CH_MCK"),
MTK_FUNCTION(3, "TDM_RX_DI"),
@@ -237,9 +233,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[11]")
),
MTK_PIN(
- PINCTRL_PIN(18, "EINT18"),
- NULL, "mt8167",
+ 18, "EINT18",
MTK_EINT_FUNCTION(0, 18),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO18"),
MTK_FUNCTION(2, "USB_DRVVBUS"),
MTK_FUNCTION(3, "I2S3_LRCK"),
@@ -249,9 +245,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[20]")
),
MTK_PIN(
- PINCTRL_PIN(19, "EINT19"),
- NULL, "mt8167",
+ 19, "EINT19",
MTK_EINT_FUNCTION(0, 19),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO19"),
MTK_FUNCTION(1, "UCTS1"),
MTK_FUNCTION(2, "IDDIG"),
@@ -262,9 +258,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[21]")
),
MTK_PIN(
- PINCTRL_PIN(20, "EINT20"),
- NULL, "mt8167",
+ 20, "EINT20",
MTK_EINT_FUNCTION(0, 20),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO20"),
MTK_FUNCTION(1, "URTS1"),
MTK_FUNCTION(3, "I2S3_DO"),
@@ -274,9 +270,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[22]")
),
MTK_PIN(
- PINCTRL_PIN(21, "EINT21"),
- NULL, "mt8167",
+ 21, "EINT21",
MTK_EINT_FUNCTION(0, 21),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO21"),
MTK_FUNCTION(1, "NRNB"),
MTK_FUNCTION(2, "ANT_SEL0"),
@@ -284,9 +280,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[31]")
),
MTK_PIN(
- PINCTRL_PIN(22, "EINT22"),
- NULL, "mt8167",
+ 22, "EINT22",
MTK_EINT_FUNCTION(0, 22),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO22"),
MTK_FUNCTION(2, "I2S_8CH_DO2"),
MTK_FUNCTION(3, "TSF_IN"),
@@ -296,9 +292,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[12]")
),
MTK_PIN(
- PINCTRL_PIN(23, "EINT23"),
- NULL, "mt8167",
+ 23, "EINT23",
MTK_EINT_FUNCTION(0, 23),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO23"),
MTK_FUNCTION(2, "I2S_8CH_DO3"),
MTK_FUNCTION(3, "CLKM0"),
@@ -308,9 +304,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[13]")
),
MTK_PIN(
- PINCTRL_PIN(24, "EINT24"),
- NULL, "mt8167",
+ 24, "EINT24",
MTK_EINT_FUNCTION(0, 24),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO24"),
MTK_FUNCTION(1, "DPI_D20"),
MTK_FUNCTION(2, "DPI_DE"),
@@ -321,9 +317,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[0]")
),
MTK_PIN(
- PINCTRL_PIN(25, "EINT25"),
- NULL, "mt8167",
+ 25, "EINT25",
MTK_EINT_FUNCTION(0, 25),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO25"),
MTK_FUNCTION(1, "DPI_D19"),
MTK_FUNCTION(2, "DPI_VSYNC"),
@@ -334,25 +330,25 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[1]")
),
MTK_PIN(
- PINCTRL_PIN(26, "PWRAP_SPI0_MI"),
- NULL, "mt8167",
+ 26, "PWRAP_SPI0_MI",
MTK_EINT_FUNCTION(0, 26),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO26"),
MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
MTK_FUNCTION(2, "PWRAP_SPI0_MI")
),
MTK_PIN(
- PINCTRL_PIN(27, "PWRAP_SPI0_MO"),
- NULL, "mt8167",
+ 27, "PWRAP_SPI0_MO",
MTK_EINT_FUNCTION(0, 27),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO27"),
MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
MTK_FUNCTION(2, "PWRAP_SPI0_MO")
),
MTK_PIN(
- PINCTRL_PIN(28, "PWRAP_INT"),
- NULL, "mt8167",
+ 28, "PWRAP_INT",
MTK_EINT_FUNCTION(0, 28),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO28"),
MTK_FUNCTION(1, "I2S0_MCK"),
MTK_FUNCTION(4, "I2S_8CH_MCK"),
@@ -360,44 +356,44 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(6, "I2S3_MCK")
),
MTK_PIN(
- PINCTRL_PIN(29, "PWRAP_SPI0_CK"),
- NULL, "mt8167",
+ 29, "PWRAP_SPI0_CK",
MTK_EINT_FUNCTION(0, 29),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO29"),
MTK_FUNCTION(1, "PWRAP_SPI0_CK")
),
MTK_PIN(
- PINCTRL_PIN(30, "PWRAP_SPI0_CSN"),
- NULL, "mt8167",
+ 30, "PWRAP_SPI0_CSN",
MTK_EINT_FUNCTION(0, 30),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO30"),
MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
),
MTK_PIN(
- PINCTRL_PIN(31, "RTC32K_CK"),
- NULL, "mt8167",
+ 31, "RTC32K_CK",
MTK_EINT_FUNCTION(0, 31),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO31"),
MTK_FUNCTION(1, "RTC32K_CK")
),
MTK_PIN(
- PINCTRL_PIN(32, "WATCHDOG"),
- NULL, "mt8167",
+ 32, "WATCHDOG",
MTK_EINT_FUNCTION(0, 32),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO32"),
MTK_FUNCTION(1, "WATCHDOG")
),
MTK_PIN(
- PINCTRL_PIN(33, "SRCLKENA"),
- NULL, "mt8167",
+ 33, "SRCLKENA",
MTK_EINT_FUNCTION(0, 33),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO33"),
MTK_FUNCTION(1, "SRCLKENA0")
),
MTK_PIN(
- PINCTRL_PIN(34, "URXD2"),
- NULL, "mt8167",
+ 34, "URXD2",
MTK_EINT_FUNCTION(0, 34),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO34"),
MTK_FUNCTION(1, "URXD2"),
MTK_FUNCTION(2, "DPI_D5"),
@@ -407,9 +403,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[0]")
),
MTK_PIN(
- PINCTRL_PIN(35, "UTXD2"),
- NULL, "mt8167",
+ 35, "UTXD2",
MTK_EINT_FUNCTION(0, 35),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO35"),
MTK_FUNCTION(1, "UTXD2"),
MTK_FUNCTION(2, "DPI_HSYNC"),
@@ -420,9 +416,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[1]")
),
MTK_PIN(
- PINCTRL_PIN(36, "MRG_CLK"),
- NULL, "mt8167",
+ 36, "MRG_CLK",
MTK_EINT_FUNCTION(0, 36),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO36"),
MTK_FUNCTION(1, "MRG_CLK"),
MTK_FUNCTION(2, "DPI_D4"),
@@ -433,9 +429,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[2]")
),
MTK_PIN(
- PINCTRL_PIN(37, "MRG_SYNC"),
- NULL, "mt8167",
+ 37, "MRG_SYNC",
MTK_EINT_FUNCTION(0, 37),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO37"),
MTK_FUNCTION(1, "MRG_SYNC"),
MTK_FUNCTION(2, "DPI_D3"),
@@ -446,9 +442,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[3]")
),
MTK_PIN(
- PINCTRL_PIN(38, "MRG_DI"),
- NULL, "mt8167",
+ 38, "MRG_DI",
MTK_EINT_FUNCTION(0, 38),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO38"),
MTK_FUNCTION(1, "MRG_DI"),
MTK_FUNCTION(2, "DPI_D1"),
@@ -459,9 +455,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[4]")
),
MTK_PIN(
- PINCTRL_PIN(39, "MRG_DO"),
- NULL, "mt8167",
+ 39, "MRG_DO",
MTK_EINT_FUNCTION(0, 39),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO39"),
MTK_FUNCTION(1, "MRG_DO"),
MTK_FUNCTION(2, "DPI_D2"),
@@ -472,18 +468,18 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[5]")
),
MTK_PIN(
- PINCTRL_PIN(40, "KPROW0"),
- NULL, "mt8167",
+ 40, "KPROW0",
MTK_EINT_FUNCTION(0, 40),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO40"),
MTK_FUNCTION(1, "KPROW0"),
MTK_FUNCTION(4, "IMG_TEST_CK"),
MTK_FUNCTION(7, "DBG_MON_B[4]")
),
MTK_PIN(
- PINCTRL_PIN(41, "KPROW1"),
- NULL, "mt8167",
+ 41, "KPROW1",
MTK_EINT_FUNCTION(0, 41),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO41"),
MTK_FUNCTION(1, "KPROW1"),
MTK_FUNCTION(2, "IDDIG"),
@@ -492,17 +488,17 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[5]")
),
MTK_PIN(
- PINCTRL_PIN(42, "KPCOL0"),
- NULL, "mt8167",
+ 42, "KPCOL0",
MTK_EINT_FUNCTION(0, 42),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO42"),
MTK_FUNCTION(1, "KPCOL0"),
MTK_FUNCTION(7, "DBG_MON_B[6]")
),
MTK_PIN(
- PINCTRL_PIN(43, "KPCOL1"),
- NULL, "mt8167",
+ 43, "KPCOL1",
MTK_EINT_FUNCTION(0, 43),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO43"),
MTK_FUNCTION(1, "KPCOL1"),
MTK_FUNCTION(2, "USB_DRVVBUS"),
@@ -513,9 +509,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[7]")
),
MTK_PIN(
- PINCTRL_PIN(44, "JTMS"),
- NULL, "mt8167",
+ 44, "JTMS",
MTK_EINT_FUNCTION(0, 44),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO44"),
MTK_FUNCTION(1, "JTMS"),
MTK_FUNCTION(2, "CONN_MCU_TMS"),
@@ -525,9 +521,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(6, "UDI_TMS_XI")
),
MTK_PIN(
- PINCTRL_PIN(45, "JTCK"),
- NULL, "mt8167",
+ 45, "JTCK",
MTK_EINT_FUNCTION(0, 45),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO45"),
MTK_FUNCTION(1, "JTCK"),
MTK_FUNCTION(2, "CONN_MCU_TCK"),
@@ -537,9 +533,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(6, "UDI_TCK_XI")
),
MTK_PIN(
- PINCTRL_PIN(46, "JTDI"),
- NULL, "mt8167",
+ 46, "JTDI",
MTK_EINT_FUNCTION(0, 46),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO46"),
MTK_FUNCTION(1, "JTDI"),
MTK_FUNCTION(2, "CONN_MCU_TDI"),
@@ -548,9 +544,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(6, "UDI_TDI_XI")
),
MTK_PIN(
- PINCTRL_PIN(47, "JTDO"),
- NULL, "mt8167",
+ 47, "JTDO",
MTK_EINT_FUNCTION(0, 47),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO47"),
MTK_FUNCTION(1, "JTDO"),
MTK_FUNCTION(2, "CONN_MCU_TDO"),
@@ -559,9 +555,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(6, "UDI_TDO")
),
MTK_PIN(
- PINCTRL_PIN(48, "SPI_CS"),
- NULL, "mt8167",
+ 48, "SPI_CS",
MTK_EINT_FUNCTION(0, 48),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO48"),
MTK_FUNCTION(1, "SPI_CSB"),
MTK_FUNCTION(3, "I2S0_DI"),
@@ -569,9 +565,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[23]")
),
MTK_PIN(
- PINCTRL_PIN(49, "SPI_CK"),
- NULL, "mt8167",
+ 49, "SPI_CK",
MTK_EINT_FUNCTION(0, 49),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO49"),
MTK_FUNCTION(1, "SPI_CLK"),
MTK_FUNCTION(3, "I2S0_LRCK"),
@@ -579,9 +575,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[24]")
),
MTK_PIN(
- PINCTRL_PIN(50, "SPI_MI"),
- NULL, "mt8167",
+ 50, "SPI_MI",
MTK_EINT_FUNCTION(0, 50),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO50"),
MTK_FUNCTION(1, "SPI_MI"),
MTK_FUNCTION(2, "SPI_MO"),
@@ -590,9 +586,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[25]")
),
MTK_PIN(
- PINCTRL_PIN(51, "SPI_MO"),
- NULL, "mt8167",
+ 51, "SPI_MO",
MTK_EINT_FUNCTION(0, 51),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO51"),
MTK_FUNCTION(1, "SPI_MO"),
MTK_FUNCTION(2, "SPI_MI"),
@@ -601,32 +597,32 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[26]")
),
MTK_PIN(
- PINCTRL_PIN(52, "SDA1"),
- NULL, "mt8167",
+ 52, "SDA1",
MTK_EINT_FUNCTION(0, 52),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO52"),
MTK_FUNCTION(1, "SDA1_0")
),
MTK_PIN(
- PINCTRL_PIN(53, "SCL1"),
- NULL, "mt8167",
+ 53, "SCL1",
MTK_EINT_FUNCTION(0, 53),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO53"),
MTK_FUNCTION(1, "SCL1_0")
),
MTK_PIN(
- PINCTRL_PIN(54, "DISP_PWM"),
- NULL, "mt8167",
+ 54, "DISP_PWM",
MTK_EINT_FUNCTION(0, 54),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO54"),
MTK_FUNCTION(1, "DISP_PWM"),
MTK_FUNCTION(2, "PWM_B"),
MTK_FUNCTION(7, "DBG_MON_B[2]")
),
MTK_PIN(
- PINCTRL_PIN(55, "I2S_DATA_IN"),
- NULL, "mt8167",
+ 55, "I2S_DATA_IN",
MTK_EINT_FUNCTION(0, 55),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO55"),
MTK_FUNCTION(1, "I2S0_DI"),
MTK_FUNCTION(2, "UCTS0"),
@@ -637,9 +633,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[28]")
),
MTK_PIN(
- PINCTRL_PIN(56, "I2S_LRCK"),
- NULL, "mt8167",
+ 56, "I2S_LRCK",
MTK_EINT_FUNCTION(0, 56),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO56"),
MTK_FUNCTION(1, "I2S0_LRCK"),
MTK_FUNCTION(3, "I2S3_LRCK"),
@@ -649,9 +645,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[29]")
),
MTK_PIN(
- PINCTRL_PIN(57, "I2S_BCK"),
- NULL, "mt8167",
+ 57, "I2S_BCK",
MTK_EINT_FUNCTION(0, 57),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO57"),
MTK_FUNCTION(1, "I2S0_BCK"),
MTK_FUNCTION(2, "URTS0"),
@@ -662,91 +658,91 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_A[30]")
),
MTK_PIN(
- PINCTRL_PIN(58, "SDA0"),
- NULL, "mt8167",
+ 58, "SDA0",
MTK_EINT_FUNCTION(0, 58),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO58"),
MTK_FUNCTION(1, "SDA0_0")
),
MTK_PIN(
- PINCTRL_PIN(59, "SCL0"),
- NULL, "mt8167",
+ 59, "SCL0",
MTK_EINT_FUNCTION(0, 59),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO59"),
MTK_FUNCTION(1, "SCL0_0")
),
MTK_PIN(
- PINCTRL_PIN(60, "SDA2"),
- NULL, "mt8167",
+ 60, "SDA2",
MTK_EINT_FUNCTION(0, 60),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO60"),
MTK_FUNCTION(1, "SDA2_0"),
MTK_FUNCTION(2, "PWM_B")
),
MTK_PIN(
- PINCTRL_PIN(61, "SCL2"),
- NULL, "mt8167",
+ 61, "SCL2",
MTK_EINT_FUNCTION(0, 61),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO61"),
MTK_FUNCTION(1, "SCL2_0"),
MTK_FUNCTION(2, "PWM_C")
),
MTK_PIN(
- PINCTRL_PIN(62, "URXD0"),
- NULL, "mt8167",
+ 62, "URXD0",
MTK_EINT_FUNCTION(0, 62),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO62"),
MTK_FUNCTION(1, "URXD0"),
MTK_FUNCTION(2, "UTXD0")
),
MTK_PIN(
- PINCTRL_PIN(63, "UTXD0"),
- NULL, "mt8167",
+ 63, "UTXD0",
MTK_EINT_FUNCTION(0, 63),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO63"),
MTK_FUNCTION(1, "UTXD0"),
MTK_FUNCTION(2, "URXD0")
),
MTK_PIN(
- PINCTRL_PIN(64, "URXD1"),
- NULL, "mt8167",
+ 64, "URXD1",
MTK_EINT_FUNCTION(0, 64),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO64"),
MTK_FUNCTION(1, "URXD1"),
MTK_FUNCTION(2, "UTXD1"),
MTK_FUNCTION(7, "DBG_MON_A[27]")
),
MTK_PIN(
- PINCTRL_PIN(65, "UTXD1"),
- NULL, "mt8167",
+ 65, "UTXD1",
MTK_EINT_FUNCTION(0, 65),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO65"),
MTK_FUNCTION(1, "UTXD1"),
MTK_FUNCTION(2, "URXD1"),
MTK_FUNCTION(7, "DBG_MON_A[31]")
),
MTK_PIN(
- PINCTRL_PIN(66, "LCM_RST"),
- NULL, "mt8167",
+ 66, "LCM_RST",
MTK_EINT_FUNCTION(0, 66),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO66"),
MTK_FUNCTION(1, "LCM_RST"),
MTK_FUNCTION(3, "I2S0_MCK"),
MTK_FUNCTION(7, "DBG_MON_B[3]")
),
MTK_PIN(
- PINCTRL_PIN(67, "DSI_TE"),
- NULL, "mt8167",
+ 67, "DSI_TE",
MTK_EINT_FUNCTION(0, 67),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO67"),
MTK_FUNCTION(1, "DSI_TE"),
MTK_FUNCTION(3, "I2S_8CH_MCK"),
MTK_FUNCTION(7, "DBG_MON_B[14]")
),
MTK_PIN(
- PINCTRL_PIN(68, "MSDC2_CMD"),
- NULL, "mt8167",
+ 68, "MSDC2_CMD",
MTK_EINT_FUNCTION(0, 68),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO68"),
MTK_FUNCTION(1, "MSDC2_CMD"),
MTK_FUNCTION(2, "I2S_8CH_DO4"),
@@ -756,9 +752,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[15]")
),
MTK_PIN(
- PINCTRL_PIN(69, "MSDC2_CLK"),
- NULL, "mt8167",
+ 69, "MSDC2_CLK",
MTK_EINT_FUNCTION(0, 69),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO69"),
MTK_FUNCTION(1, "MSDC2_CLK"),
MTK_FUNCTION(2, "I2S_8CH_DO3"),
@@ -769,9 +765,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[16]")
),
MTK_PIN(
- PINCTRL_PIN(70, "MSDC2_DAT0"),
- NULL, "mt8167",
+ 70, "MSDC2_DAT0",
MTK_EINT_FUNCTION(0, 70),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO70"),
MTK_FUNCTION(1, "MSDC2_DAT0"),
MTK_FUNCTION(2, "I2S_8CH_DO2"),
@@ -781,9 +777,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[17]")
),
MTK_PIN(
- PINCTRL_PIN(71, "MSDC2_DAT1"),
- NULL, "mt8167",
+ 71, "MSDC2_DAT1",
MTK_EINT_FUNCTION(0, 71),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO71"),
MTK_FUNCTION(1, "MSDC2_DAT1"),
MTK_FUNCTION(2, "I2S_8CH_DO1"),
@@ -794,9 +790,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[18]")
),
MTK_PIN(
- PINCTRL_PIN(72, "MSDC2_DAT2"),
- NULL, "mt8167",
+ 72, "MSDC2_DAT2",
MTK_EINT_FUNCTION(0, 72),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO72"),
MTK_FUNCTION(1, "MSDC2_DAT2"),
MTK_FUNCTION(2, "I2S_8CH_LRCK"),
@@ -807,9 +803,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[19]")
),
MTK_PIN(
- PINCTRL_PIN(73, "MSDC2_DAT3"),
- NULL, "mt8167",
+ 73, "MSDC2_DAT3",
MTK_EINT_FUNCTION(0, 73),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO73"),
MTK_FUNCTION(1, "MSDC2_DAT3"),
MTK_FUNCTION(2, "I2S_8CH_BCK"),
@@ -820,203 +816,203 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[20]")
),
MTK_PIN(
- PINCTRL_PIN(74, "TDN3"),
- NULL, "mt8167",
+ 74, "TDN3",
MTK_EINT_FUNCTION(0, 74),
- MTK_FUNCTION(0, "GPI74"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO74"),
MTK_FUNCTION(1, "TDN3")
),
MTK_PIN(
- PINCTRL_PIN(75, "TDP3"),
- NULL, "mt8167",
+ 75, "TDP3",
MTK_EINT_FUNCTION(0, 75),
- MTK_FUNCTION(0, "GPI75"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO75"),
MTK_FUNCTION(1, "TDP3")
),
MTK_PIN(
- PINCTRL_PIN(76, "TDN2"),
- NULL, "mt8167",
+ 76, "TDN2",
MTK_EINT_FUNCTION(0, 76),
- MTK_FUNCTION(0, "GPI76"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO76"),
MTK_FUNCTION(1, "TDN2")
),
MTK_PIN(
- PINCTRL_PIN(77, "TDP2"),
- NULL, "mt8167",
+ 77, "TDP2",
MTK_EINT_FUNCTION(0, 77),
- MTK_FUNCTION(0, "GPI77"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO77"),
MTK_FUNCTION(1, "TDP2")
),
MTK_PIN(
- PINCTRL_PIN(78, "TCN"),
- NULL, "mt8167",
+ 78, "TCN",
MTK_EINT_FUNCTION(0, 78),
- MTK_FUNCTION(0, "GPI78"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO78"),
MTK_FUNCTION(1, "TCN")
),
MTK_PIN(
- PINCTRL_PIN(79, "TCP"),
- NULL, "mt8167",
+ 79, "TCP",
MTK_EINT_FUNCTION(0, 79),
- MTK_FUNCTION(0, "GPI79"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO79"),
MTK_FUNCTION(1, "TCP")
),
MTK_PIN(
- PINCTRL_PIN(80, "TDN1"),
- NULL, "mt8167",
+ 80, "TDN1",
MTK_EINT_FUNCTION(0, 80),
- MTK_FUNCTION(0, "GPI80"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO80"),
MTK_FUNCTION(1, "TDN1")
),
MTK_PIN(
- PINCTRL_PIN(81, "TDP1"),
- NULL, "mt8167",
+ 81, "TDP1",
MTK_EINT_FUNCTION(0, 81),
- MTK_FUNCTION(0, "GPI81"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO81"),
MTK_FUNCTION(1, "TDP1")
),
MTK_PIN(
- PINCTRL_PIN(82, "TDN0"),
- NULL, "mt8167",
+ 82, "TDN0",
MTK_EINT_FUNCTION(0, 82),
- MTK_FUNCTION(0, "GPI82"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO82"),
MTK_FUNCTION(1, "TDN0")
),
MTK_PIN(
- PINCTRL_PIN(83, "TDP0"),
- NULL, "mt8167",
+ 83, "TDP0",
MTK_EINT_FUNCTION(0, 83),
- MTK_FUNCTION(0, "GPI83"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO83"),
MTK_FUNCTION(1, "TDP0")
),
MTK_PIN(
- PINCTRL_PIN(84, "RDN0"),
- NULL, "mt8167",
+ 84, "RDN0",
MTK_EINT_FUNCTION(0, 84),
- MTK_FUNCTION(0, "GPI84"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO84"),
MTK_FUNCTION(1, "RDN0")
),
MTK_PIN(
- PINCTRL_PIN(85, "RDP0"),
- NULL, "mt8167",
+ 85, "RDP0",
MTK_EINT_FUNCTION(0, 85),
- MTK_FUNCTION(0, "GPI85"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO85"),
MTK_FUNCTION(1, "RDP0")
),
MTK_PIN(
- PINCTRL_PIN(86, "RDN1"),
- NULL, "mt8167",
+ 86, "RDN1",
MTK_EINT_FUNCTION(0, 86),
- MTK_FUNCTION(0, "GPI86"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO86"),
MTK_FUNCTION(1, "RDN1")
),
MTK_PIN(
- PINCTRL_PIN(87, "RDP1"),
- NULL, "mt8167",
+ 87, "RDP1",
MTK_EINT_FUNCTION(0, 87),
- MTK_FUNCTION(0, "GPI87"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO87"),
MTK_FUNCTION(1, "RDP1")
),
MTK_PIN(
- PINCTRL_PIN(88, "RCN"),
- NULL, "mt8167",
+ 88, "RCN",
MTK_EINT_FUNCTION(0, 88),
- MTK_FUNCTION(0, "GPI88"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO88"),
MTK_FUNCTION(1, "RCN")
),
MTK_PIN(
- PINCTRL_PIN(89, "RCP"),
- NULL, "mt8167",
+ 89, "RCP",
MTK_EINT_FUNCTION(0, 89),
- MTK_FUNCTION(0, "GPI89"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO89"),
MTK_FUNCTION(1, "RCP")
),
MTK_PIN(
- PINCTRL_PIN(90, "RDN2"),
- NULL, "mt8167",
+ 90, "RDN2",
MTK_EINT_FUNCTION(0, 90),
- MTK_FUNCTION(0, "GPI90"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO90"),
MTK_FUNCTION(1, "RDN2"),
MTK_FUNCTION(2, "CMDAT8")
),
MTK_PIN(
- PINCTRL_PIN(91, "RDP2"),
- NULL, "mt8167",
+ 91, "RDP2",
MTK_EINT_FUNCTION(0, 91),
- MTK_FUNCTION(0, "GPI91"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO91"),
MTK_FUNCTION(1, "RDP2"),
MTK_FUNCTION(2, "CMDAT9")
),
MTK_PIN(
- PINCTRL_PIN(92, "RDN3"),
- NULL, "mt8167",
+ 92, "RDN3",
MTK_EINT_FUNCTION(0, 92),
- MTK_FUNCTION(0, "GPI92"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO92"),
MTK_FUNCTION(1, "RDN3"),
MTK_FUNCTION(2, "CMDAT4")
),
MTK_PIN(
- PINCTRL_PIN(93, "RDP3"),
- NULL, "mt8167",
+ 93, "RDP3",
MTK_EINT_FUNCTION(0, 93),
- MTK_FUNCTION(0, "GPI93"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO93"),
MTK_FUNCTION(1, "RDP3"),
MTK_FUNCTION(2, "CMDAT5")
),
MTK_PIN(
- PINCTRL_PIN(94, "RCN_A"),
- NULL, "mt8167",
+ 94, "RCN_A",
MTK_EINT_FUNCTION(0, 94),
- MTK_FUNCTION(0, "GPI94"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO94"),
MTK_FUNCTION(1, "RCN_A"),
MTK_FUNCTION(2, "CMDAT6")
),
MTK_PIN(
- PINCTRL_PIN(95, "RCP_A"),
- NULL, "mt8167",
+ 95, "RCP_A",
MTK_EINT_FUNCTION(0, 95),
- MTK_FUNCTION(0, "GPI95"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO95"),
MTK_FUNCTION(1, "RCP_A"),
MTK_FUNCTION(2, "CMDAT7")
),
MTK_PIN(
- PINCTRL_PIN(96, "RDN1_A"),
- NULL, "mt8167",
+ 96, "RDN1_A",
MTK_EINT_FUNCTION(0, 96),
- MTK_FUNCTION(0, "GPI96"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO96"),
MTK_FUNCTION(1, "RDN1_A"),
MTK_FUNCTION(2, "CMDAT2"),
MTK_FUNCTION(3, "CMCSD2")
),
MTK_PIN(
- PINCTRL_PIN(97, "RDP1_A"),
- NULL, "mt8167",
+ 97, "RDP1_A",
MTK_EINT_FUNCTION(0, 97),
- MTK_FUNCTION(0, "GPI97"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO97"),
MTK_FUNCTION(1, "RDP1_A"),
MTK_FUNCTION(2, "CMDAT3"),
MTK_FUNCTION(3, "CMCSD3")
),
MTK_PIN(
- PINCTRL_PIN(98, "RDN0_A"),
- NULL, "mt8167",
+ 98, "RDN0_A",
MTK_EINT_FUNCTION(0, 98),
- MTK_FUNCTION(0, "GPI98"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO98"),
MTK_FUNCTION(1, "RDN0_A"),
MTK_FUNCTION(2, "CMHSYNC")
),
MTK_PIN(
- PINCTRL_PIN(99, "RDP0_A"),
- NULL, "mt8167",
+ 99, "RDP0_A",
MTK_EINT_FUNCTION(0, 99),
- MTK_FUNCTION(0, "GPI99"),
+ DRV_GRP0, // N/A
+ MTK_FUNCTION(0, "GPIO99"),
MTK_FUNCTION(1, "RDP0_A"),
MTK_FUNCTION(2, "CMVSYNC")
),
MTK_PIN(
- PINCTRL_PIN(100, "CMDAT0"),
- NULL, "mt8167",
+ 100, "CMDAT0",
MTK_EINT_FUNCTION(0, 100),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO100"),
MTK_FUNCTION(1, "CMDAT0"),
MTK_FUNCTION(2, "CMCSD0"),
@@ -1025,9 +1021,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[21]")
),
MTK_PIN(
- PINCTRL_PIN(101, "CMDAT1"),
- NULL, "mt8167",
+ 101, "CMDAT1",
MTK_EINT_FUNCTION(0, 101),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO101"),
MTK_FUNCTION(1, "CMDAT1"),
MTK_FUNCTION(2, "CMCSD1"),
@@ -1037,9 +1033,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[22]")
),
MTK_PIN(
- PINCTRL_PIN(102, "CMMCLK"),
- NULL, "mt8167",
+ 102, "CMMCLK",
MTK_EINT_FUNCTION(0, 102),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO102"),
MTK_FUNCTION(1, "CMMCLK"),
MTK_FUNCTION(3, "ANT_SEL4"),
@@ -1047,29 +1043,29 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[23]")
),
MTK_PIN(
- PINCTRL_PIN(103, "CMPCLK"),
- NULL, "mt8167",
+ 103, "CMPCLK",
MTK_EINT_FUNCTION(0, 103),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO103"),
MTK_FUNCTION(1, "CMPCLK"),
MTK_FUNCTION(2, "CMCSK"),
MTK_FUNCTION(3, "ANT_SEL5"),
- MTK_FUNCTION(5, " TDM_RX_DI"),
+ MTK_FUNCTION(5, "TDM_RX_DI"),
MTK_FUNCTION(7, "DBG_MON_B[24]")
),
MTK_PIN(
- PINCTRL_PIN(104, "MSDC1_CMD"),
- NULL, "mt8167",
+ 104, "MSDC1_CMD",
MTK_EINT_FUNCTION(0, 104),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO104"),
MTK_FUNCTION(1, "MSDC1_CMD"),
MTK_FUNCTION(4, "SQICS"),
MTK_FUNCTION(7, "DBG_MON_B[25]")
),
MTK_PIN(
- PINCTRL_PIN(105, "MSDC1_CLK"),
- NULL, "mt8167",
+ 105, "MSDC1_CLK",
MTK_EINT_FUNCTION(0, 105),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO105"),
MTK_FUNCTION(1, "MSDC1_CLK"),
MTK_FUNCTION(2, "UDI_NTRST_XI"),
@@ -1079,9 +1075,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[26]")
),
MTK_PIN(
- PINCTRL_PIN(106, "MSDC1_DAT0"),
- NULL, "mt8167",
+ 106, "MSDC1_DAT0",
MTK_EINT_FUNCTION(0, 106),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO106"),
MTK_FUNCTION(1, "MSDC1_DAT0"),
MTK_FUNCTION(2, "UDI_TMS_XI"),
@@ -1091,9 +1087,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[27]")
),
MTK_PIN(
- PINCTRL_PIN(107, "MSDC1_DAT1"),
- NULL, "mt8167",
+ 107, "MSDC1_DAT1",
MTK_EINT_FUNCTION(0, 107),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO107"),
MTK_FUNCTION(1, "MSDC1_DAT1"),
MTK_FUNCTION(2, "UDI_TCK_XI"),
@@ -1103,9 +1099,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[28]")
),
MTK_PIN(
- PINCTRL_PIN(108, "MSDC1_DAT2"),
- NULL, "mt8167",
+ 108, "MSDC1_DAT2",
MTK_EINT_FUNCTION(0, 108),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO108"),
MTK_FUNCTION(1, "MSDC1_DAT2"),
MTK_FUNCTION(2, "UDI_TDI_XI"),
@@ -1115,9 +1111,9 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[29]")
),
MTK_PIN(
- PINCTRL_PIN(109, "MSDC1_DAT3"),
- NULL, "mt8167",
+ 109, "MSDC1_DAT3",
MTK_EINT_FUNCTION(0, 109),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO109"),
MTK_FUNCTION(1, "MSDC1_DAT3"),
MTK_FUNCTION(2, "UDI_TDO"),
@@ -1127,119 +1123,119 @@ static const struct mtk_desc_pin mtk_pins_mt8167[] = {
MTK_FUNCTION(7, "DBG_MON_B[30]")
),
MTK_PIN(
- PINCTRL_PIN(110, "MSDC0_DAT7"),
- NULL, "mt8167",
+ 110, "MSDC0_DAT7",
MTK_EINT_FUNCTION(0, 110),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO110"),
MTK_FUNCTION(1, "MSDC0_DAT7"),
MTK_FUNCTION(4, "NLD7")
),
MTK_PIN(
- PINCTRL_PIN(111, "MSDC0_DAT6"),
- NULL, "mt8167",
+ 111, "MSDC0_DAT6",
MTK_EINT_FUNCTION(0, 111),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO111"),
MTK_FUNCTION(1, "MSDC0_DAT6"),
MTK_FUNCTION(4, "NLD6")
),
MTK_PIN(
- PINCTRL_PIN(112, "MSDC0_DAT5"),
- NULL, "mt8167",
+ 112, "MSDC0_DAT5",
MTK_EINT_FUNCTION(0, 112),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO112"),
MTK_FUNCTION(1, "MSDC0_DAT5"),
MTK_FUNCTION(4, "NLD4")
),
MTK_PIN(
- PINCTRL_PIN(113, "MSDC0_DAT4"),
- NULL, "mt8167",
+ 113, "MSDC0_DAT4",
MTK_EINT_FUNCTION(0, 113),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO113"),
MTK_FUNCTION(1, "MSDC0_DAT4"),
MTK_FUNCTION(4, "NLD3")
),
MTK_PIN(
- PINCTRL_PIN(114, "MSDC0_RSTB"),
- NULL, "mt8167",
+ 114, "MSDC0_RSTB",
MTK_EINT_FUNCTION(0, 114),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO114"),
MTK_FUNCTION(1, "MSDC0_RSTB"),
MTK_FUNCTION(4, "NLD0")
),
MTK_PIN(
- PINCTRL_PIN(115, "MSDC0_CMD"),
- NULL, "mt8167",
+ 115, "MSDC0_CMD",
MTK_EINT_FUNCTION(0, 115),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO115"),
MTK_FUNCTION(1, "MSDC0_CMD"),
MTK_FUNCTION(4, "NALE")
),
MTK_PIN(
- PINCTRL_PIN(116, "MSDC0_CLK"),
- NULL, "mt8167",
+ 116, "MSDC0_CLK",
MTK_EINT_FUNCTION(0, 116),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO116"),
MTK_FUNCTION(1, "MSDC0_CLK"),
MTK_FUNCTION(4, "NWEB")
),
MTK_PIN(
- PINCTRL_PIN(117, "MSDC0_DAT3"),
- NULL, "mt8167",
+ 117, "MSDC0_DAT3",
MTK_EINT_FUNCTION(0, 117),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO117"),
MTK_FUNCTION(1, "MSDC0_DAT3"),
MTK_FUNCTION(4, "NLD1")
),
MTK_PIN(
- PINCTRL_PIN(118, "MSDC0_DAT2"),
- NULL, "mt8167",
+ 118, "MSDC0_DAT2",
MTK_EINT_FUNCTION(0, 118),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO118"),
MTK_FUNCTION(1, "MSDC0_DAT2"),
MTK_FUNCTION(4, "NLD5")
),
MTK_PIN(
- PINCTRL_PIN(119, "MSDC0_DAT1"),
- NULL, "mt8167",
+ 119, "MSDC0_DAT1",
MTK_EINT_FUNCTION(0, 119),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO119"),
MTK_FUNCTION(1, "MSDC0_DAT1"),
MTK_FUNCTION(4, "NLD8")
),
MTK_PIN(
- PINCTRL_PIN(120, "MSDC0_DAT0"),
- NULL, "mt8167",
+ 120, "MSDC0_DAT0",
MTK_EINT_FUNCTION(0, 120),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO120"),
MTK_FUNCTION(1, "MSDC0_DAT0"),
MTK_FUNCTION(4, "WATCHDOG"),
MTK_FUNCTION(5, "NLD2")
),
MTK_PIN(
- PINCTRL_PIN(121, "CEC"),
- NULL, "mt8167",
+ 121, "CEC",
MTK_EINT_FUNCTION(0, 121),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO121"),
MTK_FUNCTION(1, "CEC")
),
MTK_PIN(
- PINCTRL_PIN(122, "HTPLG"),
- NULL, "mt8167",
+ 122, "HTPLG",
MTK_EINT_FUNCTION(0, 122),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO122"),
MTK_FUNCTION(1, "HTPLG")
),
MTK_PIN(
- PINCTRL_PIN(123, "HDMISCK"),
- NULL, "mt8167",
+ 123, "HDMISCK",
MTK_EINT_FUNCTION(0, 123),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO123"),
MTK_FUNCTION(1, "HDMISCK")
),
MTK_PIN(
- PINCTRL_PIN(124, "HDMISD"),
- NULL, "mt8167",
+ 124, "HDMISD",
MTK_EINT_FUNCTION(0, 124),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO124"),
MTK_FUNCTION(1, "HDMISD")
),
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
index f7a4c6e4a026..fc4f8401b3c6 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8516.h
@@ -1,18 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (C) 2019 MediaTek Inc.
- */
#ifndef __PINCTRL_MTK_MT8516_H
#define __PINCTRL_MTK_MT8516_H
-#include <linux/pinctrl/pinctrl.h>
-#include "pinctrl-mtk-common.h"
+#include "pinctrl-paris.h"
-static const struct mtk_desc_pin mtk_pins_mt8516[] = {
+static const struct mtk_pin_desc mtk_pins_mt8516[] = {
MTK_PIN(
- PINCTRL_PIN(0, "EINT0"),
- NULL, "mt8516",
+ 0, "EINT0",
MTK_EINT_FUNCTION(0, 0),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO0"),
MTK_FUNCTION(1, "PWM_B"),
MTK_FUNCTION(3, "I2S2_BCK"),
@@ -21,9 +17,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[6]")
),
MTK_PIN(
- PINCTRL_PIN(1, "EINT1"),
- NULL, "mt8516",
+ 1, "EINT1",
MTK_EINT_FUNCTION(0, 1),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO1"),
MTK_FUNCTION(1, "PWM_C"),
MTK_FUNCTION(3, "I2S2_DI"),
@@ -33,9 +29,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[7]")
),
MTK_PIN(
- PINCTRL_PIN(2, "EINT2"),
- NULL, "mt8516",
+ 2, "EINT2",
MTK_EINT_FUNCTION(0, 2),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO2"),
MTK_FUNCTION(1, "CLKM0"),
MTK_FUNCTION(3, "I2S2_LRCK"),
@@ -45,9 +41,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[8]")
),
MTK_PIN(
- PINCTRL_PIN(3, "EINT3"),
- NULL, "mt8516",
+ 3, "EINT3",
MTK_EINT_FUNCTION(0, 3),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO3"),
MTK_FUNCTION(1, "CLKM1"),
MTK_FUNCTION(3, "SPI_MI"),
@@ -57,9 +53,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[9]")
),
MTK_PIN(
- PINCTRL_PIN(4, "EINT4"),
- NULL, "mt8516",
+ 4, "EINT4",
MTK_EINT_FUNCTION(0, 4),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO4"),
MTK_FUNCTION(1, "CLKM2"),
MTK_FUNCTION(3, "SPI_MO"),
@@ -69,9 +65,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[10]")
),
MTK_PIN(
- PINCTRL_PIN(5, "EINT5"),
- NULL, "mt8516",
+ 5, "EINT5",
MTK_EINT_FUNCTION(0, 5),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO5"),
MTK_FUNCTION(1, "UCTS2"),
MTK_FUNCTION(3, "SPI_CSB"),
@@ -81,9 +77,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[11]")
),
MTK_PIN(
- PINCTRL_PIN(6, "EINT6"),
- NULL, "mt8516",
+ 6, "EINT6",
MTK_EINT_FUNCTION(0, 6),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO6"),
MTK_FUNCTION(1, "URTS2"),
MTK_FUNCTION(3, "SPI_CLK"),
@@ -92,9 +88,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[12]")
),
MTK_PIN(
- PINCTRL_PIN(7, "EINT7"),
- NULL, "mt8516",
+ 7, "EINT7",
MTK_EINT_FUNCTION(0, 7),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO7"),
MTK_FUNCTION(1, "SQIRST"),
MTK_FUNCTION(3, "SDA1_0"),
@@ -104,9 +100,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[13]")
),
MTK_PIN(
- PINCTRL_PIN(8, "EINT8"),
- NULL, "mt8516",
+ 8, "EINT8",
MTK_EINT_FUNCTION(0, 8),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO8"),
MTK_FUNCTION(1, "SQICK"),
MTK_FUNCTION(2, "CLKM3"),
@@ -116,9 +112,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[14]")
),
MTK_PIN(
- PINCTRL_PIN(9, "EINT9"),
- NULL, "mt8516",
+ 9, "EINT9",
MTK_EINT_FUNCTION(0, 9),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO9"),
MTK_FUNCTION(1, "CLKM4"),
MTK_FUNCTION(2, "SDA2_0"),
@@ -128,9 +124,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[15]")
),
MTK_PIN(
- PINCTRL_PIN(10, "EINT10"),
- NULL, "mt8516",
+ 10, "EINT10",
MTK_EINT_FUNCTION(0, 10),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO10"),
MTK_FUNCTION(1, "CLKM5"),
MTK_FUNCTION(2, "SCL2_0"),
@@ -140,9 +136,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[16]")
),
MTK_PIN(
- PINCTRL_PIN(11, "EINT11"),
- NULL, "mt8516",
+ 11, "EINT11",
MTK_EINT_FUNCTION(0, 11),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO11"),
MTK_FUNCTION(1, "CLKM4"),
MTK_FUNCTION(2, "PWM_C"),
@@ -152,9 +148,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[17]")
),
MTK_PIN(
- PINCTRL_PIN(12, "EINT12"),
- NULL, "mt8516",
+ 12, "EINT12",
MTK_EINT_FUNCTION(0, 12),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO12"),
MTK_FUNCTION(1, "CLKM5"),
MTK_FUNCTION(2, "PWM_A"),
@@ -164,9 +160,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[18]")
),
MTK_PIN(
- PINCTRL_PIN(13, "EINT13"),
- NULL, "mt8516",
+ 13, "EINT13",
MTK_EINT_FUNCTION(0, 13),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO13"),
MTK_FUNCTION(3, "TSF_IN"),
MTK_FUNCTION(4, "ANT_SEL5"),
@@ -174,9 +170,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[19]")
),
MTK_PIN(
- PINCTRL_PIN(14, "EINT14"),
- NULL, "mt8516",
+ 14, "EINT14",
MTK_EINT_FUNCTION(0, 14),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO14"),
MTK_FUNCTION(2, "I2S_8CH_DO1"),
MTK_FUNCTION(3, "TDM_RX_MCK"),
@@ -186,9 +182,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[8]")
),
MTK_PIN(
- PINCTRL_PIN(15, "EINT15"),
- NULL, "mt8516",
+ 15, "EINT15",
MTK_EINT_FUNCTION(0, 15),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO15"),
MTK_FUNCTION(2, "I2S_8CH_LRCK"),
MTK_FUNCTION(3, "TDM_RX_BCK"),
@@ -198,9 +194,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[9]")
),
MTK_PIN(
- PINCTRL_PIN(16, "EINT16"),
- NULL, "mt8516",
+ 16, "EINT16",
MTK_EINT_FUNCTION(0, 16),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO16"),
MTK_FUNCTION(2, "I2S_8CH_BCK"),
MTK_FUNCTION(3, "TDM_RX_LRCK"),
@@ -210,9 +206,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[10]")
),
MTK_PIN(
- PINCTRL_PIN(17, "EINT17"),
- NULL, "mt8516",
+ 17, "EINT17",
MTK_EINT_FUNCTION(0, 17),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO17"),
MTK_FUNCTION(2, "I2S_8CH_MCK"),
MTK_FUNCTION(3, "TDM_RX_DI"),
@@ -222,9 +218,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[11]")
),
MTK_PIN(
- PINCTRL_PIN(18, "EINT18"),
- NULL, "mt8516",
+ 18, "EINT18",
MTK_EINT_FUNCTION(0, 18),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO18"),
MTK_FUNCTION(2, "USB_DRVVBUS"),
MTK_FUNCTION(3, "I2S3_LRCK"),
@@ -234,9 +230,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[20]")
),
MTK_PIN(
- PINCTRL_PIN(19, "EINT19"),
- NULL, "mt8516",
+ 19, "EINT19",
MTK_EINT_FUNCTION(0, 19),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO19"),
MTK_FUNCTION(1, "UCTS1"),
MTK_FUNCTION(2, "IDDIG"),
@@ -247,9 +243,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[21]")
),
MTK_PIN(
- PINCTRL_PIN(20, "EINT20"),
- NULL, "mt8516",
+ 20, "EINT20",
MTK_EINT_FUNCTION(0, 20),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO20"),
MTK_FUNCTION(1, "URTS1"),
MTK_FUNCTION(3, "I2S3_DO"),
@@ -259,9 +255,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[22]")
),
MTK_PIN(
- PINCTRL_PIN(21, "EINT21"),
- NULL, "mt8516",
+ 21, "EINT21",
MTK_EINT_FUNCTION(0, 21),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO21"),
MTK_FUNCTION(1, "NRNB"),
MTK_FUNCTION(2, "ANT_SEL0"),
@@ -269,9 +265,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[31]")
),
MTK_PIN(
- PINCTRL_PIN(22, "EINT22"),
- NULL, "mt8516",
+ 22, "EINT22",
MTK_EINT_FUNCTION(0, 22),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO22"),
MTK_FUNCTION(2, "I2S_8CH_DO2"),
MTK_FUNCTION(3, "TSF_IN"),
@@ -281,9 +277,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[12]")
),
MTK_PIN(
- PINCTRL_PIN(23, "EINT23"),
- NULL, "mt8516",
+ 23, "EINT23",
MTK_EINT_FUNCTION(0, 23),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO23"),
MTK_FUNCTION(2, "I2S_8CH_DO3"),
MTK_FUNCTION(3, "CLKM0"),
@@ -293,9 +289,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[13]")
),
MTK_PIN(
- PINCTRL_PIN(24, "EINT24"),
- NULL, "mt8516",
+ 24, "EINT24",
MTK_EINT_FUNCTION(0, 24),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO24"),
MTK_FUNCTION(3, "ANT_SEL1"),
MTK_FUNCTION(4, "UCTS2"),
@@ -304,9 +300,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[0]")
),
MTK_PIN(
- PINCTRL_PIN(25, "EINT25"),
- NULL, "mt8516",
+ 25, "EINT25",
MTK_EINT_FUNCTION(0, 25),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO25"),
MTK_FUNCTION(3, "ANT_SEL0"),
MTK_FUNCTION(4, "URTS2"),
@@ -315,25 +311,25 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[1]")
),
MTK_PIN(
- PINCTRL_PIN(26, "PWRAP_SPI0_MI"),
- NULL, "mt8516",
+ 26, "PWRAP_SPI0_MI",
MTK_EINT_FUNCTION(0, 26),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO26"),
MTK_FUNCTION(1, "PWRAP_SPI0_MO"),
MTK_FUNCTION(2, "PWRAP_SPI0_MI")
),
MTK_PIN(
- PINCTRL_PIN(27, "PWRAP_SPI0_MO"),
- NULL, "mt8516",
+ 27, "PWRAP_SPI0_MO",
MTK_EINT_FUNCTION(0, 27),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO27"),
MTK_FUNCTION(1, "PWRAP_SPI0_MI"),
MTK_FUNCTION(2, "PWRAP_SPI0_MO")
),
MTK_PIN(
- PINCTRL_PIN(28, "PWRAP_INT"),
- NULL, "mt8516",
+ 28, "PWRAP_INT",
MTK_EINT_FUNCTION(0, 28),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO28"),
MTK_FUNCTION(1, "I2S0_MCK"),
MTK_FUNCTION(4, "I2S_8CH_MCK"),
@@ -341,44 +337,44 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(6, "I2S3_MCK")
),
MTK_PIN(
- PINCTRL_PIN(29, "PWRAP_SPI0_CK"),
- NULL, "mt8516",
+ 29, "PWRAP_SPI0_CK",
MTK_EINT_FUNCTION(0, 29),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO29"),
MTK_FUNCTION(1, "PWRAP_SPI0_CK")
),
MTK_PIN(
- PINCTRL_PIN(30, "PWRAP_SPI0_CSN"),
- NULL, "mt8516",
+ 30, "PWRAP_SPI0_CSN",
MTK_EINT_FUNCTION(0, 30),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO30"),
MTK_FUNCTION(1, "PWRAP_SPI0_CSN")
),
MTK_PIN(
- PINCTRL_PIN(31, "RTC32K_CK"),
- NULL, "mt8516",
+ 31, "RTC32K_CK",
MTK_EINT_FUNCTION(0, 31),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO31"),
MTK_FUNCTION(1, "RTC32K_CK")
),
MTK_PIN(
- PINCTRL_PIN(32, "WATCHDOG"),
- NULL, "mt8516",
+ 32, "WATCHDOG",
MTK_EINT_FUNCTION(0, 32),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO32"),
MTK_FUNCTION(1, "WATCHDOG")
),
MTK_PIN(
- PINCTRL_PIN(33, "SRCLKENA"),
- NULL, "mt8516",
+ 33, "SRCLKENA",
MTK_EINT_FUNCTION(0, 33),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO33"),
MTK_FUNCTION(1, "SRCLKENA0")
),
MTK_PIN(
- PINCTRL_PIN(34, "URXD2"),
- NULL, "mt8516",
+ 34, "URXD2",
MTK_EINT_FUNCTION(0, 34),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO34"),
MTK_FUNCTION(1, "URXD2"),
MTK_FUNCTION(3, "UTXD2"),
@@ -387,9 +383,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[0]")
),
MTK_PIN(
- PINCTRL_PIN(35, "UTXD2"),
- NULL, "mt8516",
+ 35, "UTXD2",
MTK_EINT_FUNCTION(0, 35),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO35"),
MTK_FUNCTION(1, "UTXD2"),
MTK_FUNCTION(3, "URXD2"),
@@ -398,9 +394,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[1]")
),
MTK_PIN(
- PINCTRL_PIN(36, "MRG_CLK"),
- NULL, "mt8516",
+ 36, "MRG_CLK",
MTK_EINT_FUNCTION(0, 36),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO36"),
MTK_FUNCTION(1, "MRG_CLK"),
MTK_FUNCTION(3, "I2S0_BCK"),
@@ -410,9 +406,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[2]")
),
MTK_PIN(
- PINCTRL_PIN(37, "MRG_SYNC"),
- NULL, "mt8516",
+ 37, "MRG_SYNC",
MTK_EINT_FUNCTION(0, 37),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO37"),
MTK_FUNCTION(1, "MRG_SYNC"),
MTK_FUNCTION(3, "I2S0_LRCK"),
@@ -422,9 +418,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[3]")
),
MTK_PIN(
- PINCTRL_PIN(38, "MRG_DI"),
- NULL, "mt8516",
+ 38, "MRG_DI",
MTK_EINT_FUNCTION(0, 38),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO38"),
MTK_FUNCTION(1, "MRG_DI"),
MTK_FUNCTION(3, "I2S0_DI"),
@@ -434,9 +430,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[4]")
),
MTK_PIN(
- PINCTRL_PIN(39, "MRG_DO"),
- NULL, "mt8516",
+ 39, "MRG_DO",
MTK_EINT_FUNCTION(0, 39),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO39"),
MTK_FUNCTION(1, "MRG_DO"),
MTK_FUNCTION(3, "I2S0_MCK"),
@@ -446,17 +442,17 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[5]")
),
MTK_PIN(
- PINCTRL_PIN(40, "KPROW0"),
- NULL, "mt8516",
+ 40, "KPROW0",
MTK_EINT_FUNCTION(0, 40),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO40"),
MTK_FUNCTION(1, "KPROW0"),
MTK_FUNCTION(7, "DBG_MON_B[4]")
),
MTK_PIN(
- PINCTRL_PIN(41, "KPROW1"),
- NULL, "mt8516",
+ 41, "KPROW1",
MTK_EINT_FUNCTION(0, 41),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO41"),
MTK_FUNCTION(1, "KPROW1"),
MTK_FUNCTION(2, "IDDIG"),
@@ -464,17 +460,17 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[5]")
),
MTK_PIN(
- PINCTRL_PIN(42, "KPCOL0"),
- NULL, "mt8516",
+ 42, "KPCOL0",
MTK_EINT_FUNCTION(0, 42),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO42"),
MTK_FUNCTION(1, "KPCOL0"),
MTK_FUNCTION(7, "DBG_MON_B[6]")
),
MTK_PIN(
- PINCTRL_PIN(43, "KPCOL1"),
- NULL, "mt8516",
+ 43, "KPCOL1",
MTK_EINT_FUNCTION(0, 43),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO43"),
MTK_FUNCTION(1, "KPCOL1"),
MTK_FUNCTION(2, "USB_DRVVBUS"),
@@ -483,43 +479,43 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[7]")
),
MTK_PIN(
- PINCTRL_PIN(44, "JTMS"),
- NULL, "mt8516",
+ 44, "JTMS",
MTK_EINT_FUNCTION(0, 44),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO44"),
MTK_FUNCTION(1, "JTMS"),
MTK_FUNCTION(2, "CONN_MCU_TMS"),
MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC")
),
MTK_PIN(
- PINCTRL_PIN(45, "JTCK"),
- NULL, "mt8516",
+ 45, "JTCK",
MTK_EINT_FUNCTION(0, 45),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO45"),
MTK_FUNCTION(1, "JTCK"),
MTK_FUNCTION(2, "CONN_MCU_TCK"),
MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC")
),
MTK_PIN(
- PINCTRL_PIN(46, "JTDI"),
- NULL, "mt8516",
+ 46, "JTDI",
MTK_EINT_FUNCTION(0, 46),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO46"),
MTK_FUNCTION(1, "JTDI"),
MTK_FUNCTION(2, "CONN_MCU_TDI")
),
MTK_PIN(
- PINCTRL_PIN(47, "JTDO"),
- NULL, "mt8516",
+ 47, "JTDO",
MTK_EINT_FUNCTION(0, 47),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO47"),
MTK_FUNCTION(1, "JTDO"),
MTK_FUNCTION(2, "CONN_MCU_TDO")
),
MTK_PIN(
- PINCTRL_PIN(48, "SPI_CS"),
- NULL, "mt8516",
+ 48, "SPI_CS",
MTK_EINT_FUNCTION(0, 48),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO48"),
MTK_FUNCTION(1, "SPI_CSB"),
MTK_FUNCTION(3, "I2S0_DI"),
@@ -527,9 +523,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[23]")
),
MTK_PIN(
- PINCTRL_PIN(49, "SPI_CK"),
- NULL, "mt8516",
+ 49, "SPI_CK",
MTK_EINT_FUNCTION(0, 49),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO49"),
MTK_FUNCTION(1, "SPI_CLK"),
MTK_FUNCTION(3, "I2S0_LRCK"),
@@ -537,9 +533,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[24]")
),
MTK_PIN(
- PINCTRL_PIN(50, "SPI_MI"),
- NULL, "mt8516",
+ 50, "SPI_MI",
MTK_EINT_FUNCTION(0, 50),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO50"),
MTK_FUNCTION(1, "SPI_MI"),
MTK_FUNCTION(2, "SPI_MO"),
@@ -548,9 +544,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[25]")
),
MTK_PIN(
- PINCTRL_PIN(51, "SPI_MO"),
- NULL, "mt8516",
+ 51, "SPI_MO",
MTK_EINT_FUNCTION(0, 51),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO51"),
MTK_FUNCTION(1, "SPI_MO"),
MTK_FUNCTION(2, "SPI_MI"),
@@ -559,31 +555,31 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[26]")
),
MTK_PIN(
- PINCTRL_PIN(52, "SDA1"),
- NULL, "mt8516",
+ 52, "SDA1",
MTK_EINT_FUNCTION(0, 52),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO52"),
MTK_FUNCTION(1, "SDA1_0")
),
MTK_PIN(
- PINCTRL_PIN(53, "SCL1"),
- NULL, "mt8516",
+ 53, "SCL1",
MTK_EINT_FUNCTION(0, 53),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO53"),
MTK_FUNCTION(1, "SCL1_0")
),
MTK_PIN(
- PINCTRL_PIN(54, "GPIO54"),
- NULL, "mt8516",
+ 54, "GPIO54",
MTK_EINT_FUNCTION(0, 54),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO54"),
MTK_FUNCTION(2, "PWM_B"),
MTK_FUNCTION(7, "DBG_MON_B[2]")
),
MTK_PIN(
- PINCTRL_PIN(55, "I2S_DATA_IN"),
- NULL, "mt8516",
+ 55, "I2S_DATA_IN",
MTK_EINT_FUNCTION(0, 55),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO55"),
MTK_FUNCTION(1, "I2S0_DI"),
MTK_FUNCTION(2, "UCTS0"),
@@ -594,9 +590,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[28]")
),
MTK_PIN(
- PINCTRL_PIN(56, "I2S_LRCK"),
- NULL, "mt8516",
+ 56, "I2S_LRCK",
MTK_EINT_FUNCTION(0, 56),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO56"),
MTK_FUNCTION(1, "I2S0_LRCK"),
MTK_FUNCTION(3, "I2S3_LRCK"),
@@ -606,9 +602,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[29]")
),
MTK_PIN(
- PINCTRL_PIN(57, "I2S_BCK"),
- NULL, "mt8516",
+ 57, "I2S_BCK",
MTK_EINT_FUNCTION(0, 57),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO57"),
MTK_FUNCTION(1, "I2S0_BCK"),
MTK_FUNCTION(2, "URTS0"),
@@ -619,90 +615,90 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_A[30]")
),
MTK_PIN(
- PINCTRL_PIN(58, "SDA0"),
- NULL, "mt8516",
+ 58, "SDA0",
MTK_EINT_FUNCTION(0, 58),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO58"),
MTK_FUNCTION(1, "SDA0_0")
),
MTK_PIN(
- PINCTRL_PIN(59, "SCL0"),
- NULL, "mt8516",
+ 59, "SCL0",
MTK_EINT_FUNCTION(0, 59),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO59"),
MTK_FUNCTION(1, "SCL0_0")
),
MTK_PIN(
- PINCTRL_PIN(60, "SDA2"),
- NULL, "mt8516",
+ 60, "SDA2",
MTK_EINT_FUNCTION(0, 60),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO60"),
MTK_FUNCTION(1, "SDA2_0"),
MTK_FUNCTION(2, "PWM_B")
),
MTK_PIN(
- PINCTRL_PIN(61, "SCL2"),
- NULL, "mt8516",
+ 61, "SCL2",
MTK_EINT_FUNCTION(0, 61),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO61"),
MTK_FUNCTION(1, "SCL2_0"),
MTK_FUNCTION(2, "PWM_C")
),
MTK_PIN(
- PINCTRL_PIN(62, "URXD0"),
- NULL, "mt8516",
+ 62, "URXD0",
MTK_EINT_FUNCTION(0, 62),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO62"),
MTK_FUNCTION(1, "URXD0"),
MTK_FUNCTION(2, "UTXD0")
),
MTK_PIN(
- PINCTRL_PIN(63, "UTXD0"),
- NULL, "mt8516",
+ 63, "UTXD0",
MTK_EINT_FUNCTION(0, 63),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO63"),
MTK_FUNCTION(1, "UTXD0"),
MTK_FUNCTION(2, "URXD0")
),
MTK_PIN(
- PINCTRL_PIN(64, "URXD1"),
- NULL, "mt8516",
+ 64, "URXD1",
MTK_EINT_FUNCTION(0, 64),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO64"),
MTK_FUNCTION(1, "URXD1"),
MTK_FUNCTION(2, "UTXD1"),
MTK_FUNCTION(7, "DBG_MON_A[27]")
),
MTK_PIN(
- PINCTRL_PIN(65, "UTXD1"),
- NULL, "mt8516",
+ 65, "UTXD1",
MTK_EINT_FUNCTION(0, 65),
+ DRV_GRP0,
MTK_FUNCTION(0, "GPIO65"),
MTK_FUNCTION(1, "UTXD1"),
MTK_FUNCTION(2, "URXD1"),
MTK_FUNCTION(7, "DBG_MON_A[31]")
),
MTK_PIN(
- PINCTRL_PIN(66, "LCM_RST"),
- NULL, "mt8516",
+ 66, "LCM_RST",
MTK_EINT_FUNCTION(0, 66),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO66"),
MTK_FUNCTION(1, "LCM_RST"),
MTK_FUNCTION(3, "I2S0_MCK"),
MTK_FUNCTION(7, "DBG_MON_B[3]")
),
MTK_PIN(
- PINCTRL_PIN(67, "GPIO67"),
- NULL, "mt8516",
+ 67, "GPIO67",
MTK_EINT_FUNCTION(0, 67),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO67"),
MTK_FUNCTION(3, "I2S_8CH_MCK"),
MTK_FUNCTION(7, "DBG_MON_B[14]")
),
MTK_PIN(
- PINCTRL_PIN(68, "MSDC2_CMD"),
- NULL, "mt8516",
+ 68, "MSDC2_CMD",
MTK_EINT_FUNCTION(0, 68),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO68"),
MTK_FUNCTION(1, "MSDC2_CMD"),
MTK_FUNCTION(2, "I2S_8CH_DO4"),
@@ -712,9 +708,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[15]")
),
MTK_PIN(
- PINCTRL_PIN(69, "MSDC2_CLK"),
- NULL, "mt8516",
+ 69, "MSDC2_CLK",
MTK_EINT_FUNCTION(0, 69),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO69"),
MTK_FUNCTION(1, "MSDC2_CLK"),
MTK_FUNCTION(2, "I2S_8CH_DO3"),
@@ -724,9 +720,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[16]")
),
MTK_PIN(
- PINCTRL_PIN(70, "MSDC2_DAT0"),
- NULL, "mt8516",
+ 70, "MSDC2_DAT0",
MTK_EINT_FUNCTION(0, 70),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO70"),
MTK_FUNCTION(1, "MSDC2_DAT0"),
MTK_FUNCTION(2, "I2S_8CH_DO2"),
@@ -735,9 +731,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[17]")
),
MTK_PIN(
- PINCTRL_PIN(71, "MSDC2_DAT1"),
- NULL, "mt8516",
+ 71, "MSDC2_DAT1",
MTK_EINT_FUNCTION(0, 71),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO71"),
MTK_FUNCTION(1, "MSDC2_DAT1"),
MTK_FUNCTION(2, "I2S_8CH_DO1"),
@@ -748,9 +744,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[18]")
),
MTK_PIN(
- PINCTRL_PIN(72, "MSDC2_DAT2"),
- NULL, "mt8516",
+ 72, "MSDC2_DAT2",
MTK_EINT_FUNCTION(0, 72),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO72"),
MTK_FUNCTION(1, "MSDC2_DAT2"),
MTK_FUNCTION(2, "I2S_8CH_LRCK"),
@@ -760,9 +756,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[19]")
),
MTK_PIN(
- PINCTRL_PIN(73, "MSDC2_DAT3"),
- NULL, "mt8516",
+ 73, "MSDC2_DAT3",
MTK_EINT_FUNCTION(0, 73),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO73"),
MTK_FUNCTION(1, "MSDC2_DAT3"),
MTK_FUNCTION(2, "I2S_8CH_BCK"),
@@ -773,203 +769,203 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[20]")
),
MTK_PIN(
- PINCTRL_PIN(74, "TDN3"),
- NULL, "mt8516",
+ 74, "TDN3",
MTK_EINT_FUNCTION(0, 74),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO74"),
MTK_FUNCTION(1, "TDN3")
),
MTK_PIN(
- PINCTRL_PIN(75, "TDP3"),
- NULL, "mt8516",
+ 75, "TDP3",
MTK_EINT_FUNCTION(0, 75),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO75"),
MTK_FUNCTION(1, "TDP3")
),
MTK_PIN(
- PINCTRL_PIN(76, "TDN2"),
- NULL, "mt8516",
+ 76, "TDN2",
MTK_EINT_FUNCTION(0, 76),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO76"),
MTK_FUNCTION(1, "TDN2")
),
MTK_PIN(
- PINCTRL_PIN(77, "TDP2"),
- NULL, "mt8516",
+ 77, "TDP2",
MTK_EINT_FUNCTION(0, 77),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO77"),
MTK_FUNCTION(1, "TDP2")
),
MTK_PIN(
- PINCTRL_PIN(78, "TCN"),
- NULL, "mt8516",
+ 78, "TCN",
MTK_EINT_FUNCTION(0, 78),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO78"),
MTK_FUNCTION(1, "TCN")
),
MTK_PIN(
- PINCTRL_PIN(79, "TCP"),
- NULL, "mt8516",
+ 79, "TCP",
MTK_EINT_FUNCTION(0, 79),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO79"),
MTK_FUNCTION(1, "TCP")
),
MTK_PIN(
- PINCTRL_PIN(80, "TDN1"),
- NULL, "mt8516",
+ 80, "TDN1",
MTK_EINT_FUNCTION(0, 80),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO80"),
MTK_FUNCTION(1, "TDN1")
),
MTK_PIN(
- PINCTRL_PIN(81, "TDP1"),
- NULL, "mt8516",
+ 81, "TDP1",
MTK_EINT_FUNCTION(0, 81),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO81"),
MTK_FUNCTION(1, "TDP1")
),
MTK_PIN(
- PINCTRL_PIN(82, "TDN0"),
- NULL, "mt8516",
+ 82, "TDN0",
MTK_EINT_FUNCTION(0, 82),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO82"),
MTK_FUNCTION(1, "TDN0")
),
MTK_PIN(
- PINCTRL_PIN(83, "TDP0"),
- NULL, "mt8516",
+ 83, "TDP0",
MTK_EINT_FUNCTION(0, 83),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO83"),
MTK_FUNCTION(1, "TDP0")
),
MTK_PIN(
- PINCTRL_PIN(84, "RDN0"),
- NULL, "mt8516",
+ 84, "RDN0",
MTK_EINT_FUNCTION(0, 84),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO84"),
MTK_FUNCTION(1, "RDN0")
),
MTK_PIN(
- PINCTRL_PIN(85, "RDP0"),
- NULL, "mt8516",
+ 85, "RDP0",
MTK_EINT_FUNCTION(0, 85),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO85"),
MTK_FUNCTION(1, "RDP0")
),
MTK_PIN(
- PINCTRL_PIN(86, "RDN1"),
- NULL, "mt8516",
+ 86, "RDN1",
MTK_EINT_FUNCTION(0, 86),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO86"),
MTK_FUNCTION(1, "RDN1")
),
MTK_PIN(
- PINCTRL_PIN(87, "RDP1"),
- NULL, "mt8516",
+ 87, "RDP1",
MTK_EINT_FUNCTION(0, 87),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO87"),
MTK_FUNCTION(1, "RDP1")
),
MTK_PIN(
- PINCTRL_PIN(88, "RCN"),
- NULL, "mt8516",
+ 88, "RCN",
MTK_EINT_FUNCTION(0, 88),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO88"),
MTK_FUNCTION(1, "RCN")
),
MTK_PIN(
- PINCTRL_PIN(89, "RCP"),
- NULL, "mt8516",
+ 89, "RCP",
MTK_EINT_FUNCTION(0, 89),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO89"),
MTK_FUNCTION(1, "RCP")
),
MTK_PIN(
- PINCTRL_PIN(90, "RDN2"),
- NULL, "mt8516",
+ 90, "RDN2",
MTK_EINT_FUNCTION(0, 90),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO90"),
MTK_FUNCTION(1, "RDN2"),
MTK_FUNCTION(2, "CMDAT8")
),
MTK_PIN(
- PINCTRL_PIN(91, "RDP2"),
- NULL, "mt8516",
+ 91, "RDP2",
MTK_EINT_FUNCTION(0, 91),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO91"),
MTK_FUNCTION(1, "RDP2"),
MTK_FUNCTION(2, "CMDAT9")
),
MTK_PIN(
- PINCTRL_PIN(92, "RDN3"),
- NULL, "mt8516",
+ 92, "RDN3",
MTK_EINT_FUNCTION(0, 92),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO92"),
MTK_FUNCTION(1, "RDN3"),
MTK_FUNCTION(2, "CMDAT4")
),
MTK_PIN(
- PINCTRL_PIN(93, "RDP3"),
- NULL, "mt8516",
+ 93, "RDP3",
MTK_EINT_FUNCTION(0, 93),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO93"),
MTK_FUNCTION(1, "RDP3"),
MTK_FUNCTION(2, "CMDAT5")
),
MTK_PIN(
- PINCTRL_PIN(94, "RCN_A"),
- NULL, "mt8516",
+ 94, "RCN_A",
MTK_EINT_FUNCTION(0, 94),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO94"),
MTK_FUNCTION(1, "RCN_A"),
MTK_FUNCTION(2, "CMDAT6")
),
MTK_PIN(
- PINCTRL_PIN(95, "RCP_A"),
- NULL, "mt8516",
+ 95, "RCP_A",
MTK_EINT_FUNCTION(0, 95),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO95"),
MTK_FUNCTION(1, "RCP_A"),
MTK_FUNCTION(2, "CMDAT7")
),
MTK_PIN(
- PINCTRL_PIN(96, "RDN1_A"),
- NULL, "mt8516",
+ 96, "RDN1_A",
MTK_EINT_FUNCTION(0, 96),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO96"),
MTK_FUNCTION(1, "RDN1_A"),
MTK_FUNCTION(2, "CMDAT2"),
MTK_FUNCTION(3, "CMCSD2")
),
MTK_PIN(
- PINCTRL_PIN(97, "RDP1_A"),
- NULL, "mt8516",
+ 97, "RDP1_A",
MTK_EINT_FUNCTION(0, 97),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO97"),
MTK_FUNCTION(1, "RDP1_A"),
MTK_FUNCTION(2, "CMDAT3"),
MTK_FUNCTION(3, "CMCSD3")
),
MTK_PIN(
- PINCTRL_PIN(98, "RDN0_A"),
- NULL, "mt8516",
+ 98, "RDN0_A",
MTK_EINT_FUNCTION(0, 98),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO98"),
MTK_FUNCTION(1, "RDN0_A"),
MTK_FUNCTION(2, "CMHSYNC")
),
MTK_PIN(
- PINCTRL_PIN(99, "RDP0_A"),
- NULL, "mt8516",
+ 99, "RDP0_A",
MTK_EINT_FUNCTION(0, 99),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO99"),
MTK_FUNCTION(1, "RDP0_A"),
MTK_FUNCTION(2, "CMVSYNC")
),
MTK_PIN(
- PINCTRL_PIN(100, "CMDAT0"),
- NULL, "mt8516",
+ 100, "CMDAT0",
MTK_EINT_FUNCTION(0, 100),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO100"),
MTK_FUNCTION(1, "CMDAT0"),
MTK_FUNCTION(2, "CMCSD0"),
@@ -978,9 +974,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[21]")
),
MTK_PIN(
- PINCTRL_PIN(101, "CMDAT1"),
- NULL, "mt8516",
+ 101, "CMDAT1",
MTK_EINT_FUNCTION(0, 101),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO101"),
MTK_FUNCTION(1, "CMDAT1"),
MTK_FUNCTION(2, "CMCSD1"),
@@ -990,9 +986,9 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[22]")
),
MTK_PIN(
- PINCTRL_PIN(102, "CMMCLK"),
- NULL, "mt8516",
+ 102, "CMMCLK",
MTK_EINT_FUNCTION(0, 102),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO102"),
MTK_FUNCTION(1, "CMMCLK"),
MTK_FUNCTION(3, "ANT_SEL4"),
@@ -1000,181 +996,181 @@ static const struct mtk_desc_pin mtk_pins_mt8516[] = {
MTK_FUNCTION(7, "DBG_MON_B[23]")
),
MTK_PIN(
- PINCTRL_PIN(103, "CMPCLK"),
- NULL, "mt8516",
+ 103, "CMPCLK",
MTK_EINT_FUNCTION(0, 103),
+ DRV_GRP2,
MTK_FUNCTION(0, "GPIO103"),
MTK_FUNCTION(1, "CMPCLK"),
MTK_FUNCTION(2, "CMCSK"),
MTK_FUNCTION(3, "ANT_SEL5"),
- MTK_FUNCTION(5, " TDM_RX_DI"),
+ MTK_FUNCTION(5, "TDM_RX_DI"),
MTK_FUNCTION(7, "DBG_MON_B[24]")
),
MTK_PIN(
- PINCTRL_PIN(104, "MSDC1_CMD"),
- NULL, "mt8516",
+ 104, "MSDC1_CMD",
MTK_EINT_FUNCTION(0, 104),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO104"),
MTK_FUNCTION(1, "MSDC1_CMD"),
MTK_FUNCTION(4, "SQICS"),
MTK_FUNCTION(7, "DBG_MON_B[25]")
),
MTK_PIN(
- PINCTRL_PIN(105, "MSDC1_CLK"),
- NULL, "mt8516",
+ 105, "MSDC1_CLK",
MTK_EINT_FUNCTION(0, 105),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO105"),
MTK_FUNCTION(1, "MSDC1_CLK"),
MTK_FUNCTION(4, "SQISO"),
MTK_FUNCTION(7, "DBG_MON_B[26]")
),
MTK_PIN(
- PINCTRL_PIN(106, "MSDC1_DAT0"),
- NULL, "mt8516",
+ 106, "MSDC1_DAT0",
MTK_EINT_FUNCTION(0, 106),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO106"),
MTK_FUNCTION(1, "MSDC1_DAT0"),
MTK_FUNCTION(4, "SQISI"),
MTK_FUNCTION(7, "DBG_MON_B[27]")
),
MTK_PIN(
- PINCTRL_PIN(107, "MSDC1_DAT1"),
- NULL, "mt8516",
+ 107, "MSDC1_DAT1",
MTK_EINT_FUNCTION(0, 107),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO107"),
MTK_FUNCTION(1, "MSDC1_DAT1"),
MTK_FUNCTION(4, "SQIWP"),
MTK_FUNCTION(7, "DBG_MON_B[28]")
),
MTK_PIN(
- PINCTRL_PIN(108, "MSDC1_DAT2"),
- NULL, "mt8516",
+ 108, "MSDC1_DAT2",
MTK_EINT_FUNCTION(0, 108),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO108"),
MTK_FUNCTION(1, "MSDC1_DAT2"),
MTK_FUNCTION(4, "SQIRST"),
MTK_FUNCTION(7, "DBG_MON_B[29]")
),
MTK_PIN(
- PINCTRL_PIN(109, "MSDC1_DAT3"),
- NULL, "mt8516",
+ 109, "MSDC1_DAT3",
MTK_EINT_FUNCTION(0, 109),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO109"),
MTK_FUNCTION(1, "MSDC1_DAT3"),
- MTK_FUNCTION(4, "SQICK"), /* WIP */
+ MTK_FUNCTION(4, "SQICK"),
MTK_FUNCTION(7, "DBG_MON_B[30]")
),
MTK_PIN(
- PINCTRL_PIN(110, "MSDC0_DAT7"),
- NULL, "mt8516",
+ 110, "MSDC0_DAT7",
MTK_EINT_FUNCTION(0, 110),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO110"),
MTK_FUNCTION(1, "MSDC0_DAT7"),
MTK_FUNCTION(4, "NLD7")
),
MTK_PIN(
- PINCTRL_PIN(111, "MSDC0_DAT6"),
- NULL, "mt8516",
+ 111, "MSDC0_DAT6",
MTK_EINT_FUNCTION(0, 111),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO111"),
MTK_FUNCTION(1, "MSDC0_DAT6"),
MTK_FUNCTION(4, "NLD6")
),
MTK_PIN(
- PINCTRL_PIN(112, "MSDC0_DAT5"),
- NULL, "mt8516",
+ 112, "MSDC0_DAT5",
MTK_EINT_FUNCTION(0, 112),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO112"),
MTK_FUNCTION(1, "MSDC0_DAT5"),
MTK_FUNCTION(4, "NLD4")
),
MTK_PIN(
- PINCTRL_PIN(113, "MSDC0_DAT4"),
- NULL, "mt8516",
+ 113, "MSDC0_DAT4",
MTK_EINT_FUNCTION(0, 113),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO113"),
MTK_FUNCTION(1, "MSDC0_DAT4"),
MTK_FUNCTION(4, "NLD3")
),
MTK_PIN(
- PINCTRL_PIN(114, "MSDC0_RSTB"),
- NULL, "mt8516",
+ 114, "MSDC0_RSTB",
MTK_EINT_FUNCTION(0, 114),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO114"),
MTK_FUNCTION(1, "MSDC0_RSTB"),
MTK_FUNCTION(4, "NLD0")
),
MTK_PIN(
- PINCTRL_PIN(115, "MSDC0_CMD"),
- NULL, "mt8516",
+ 115, "MSDC0_CMD",
MTK_EINT_FUNCTION(0, 115),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO115"),
MTK_FUNCTION(1, "MSDC0_CMD"),
MTK_FUNCTION(4, "NALE")
),
MTK_PIN(
- PINCTRL_PIN(116, "MSDC0_CLK"),
- NULL, "mt8516",
+ 116, "MSDC0_CLK",
MTK_EINT_FUNCTION(0, 116),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO116"),
MTK_FUNCTION(1, "MSDC0_CLK"),
MTK_FUNCTION(4, "NWEB")
),
MTK_PIN(
- PINCTRL_PIN(117, "MSDC0_DAT3"),
- NULL, "mt8516",
+ 117, "MSDC0_DAT3",
MTK_EINT_FUNCTION(0, 117),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO117"),
MTK_FUNCTION(1, "MSDC0_DAT3"),
MTK_FUNCTION(4, "NLD1")
),
MTK_PIN(
- PINCTRL_PIN(118, "MSDC0_DAT2"),
- NULL, "mt8516",
+ 118, "MSDC0_DAT2",
MTK_EINT_FUNCTION(0, 118),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO118"),
MTK_FUNCTION(1, "MSDC0_DAT2"),
MTK_FUNCTION(4, "NLD5")
),
MTK_PIN(
- PINCTRL_PIN(119, "MSDC0_DAT1"),
- NULL, "mt8516",
+ 119, "MSDC0_DAT1",
MTK_EINT_FUNCTION(0, 119),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO119"),
MTK_FUNCTION(1, "MSDC0_DAT1"),
MTK_FUNCTION(4, "NLD8")
),
MTK_PIN(
- PINCTRL_PIN(120, "MSDC0_DAT0"),
- NULL, "mt8516",
+ 120, "MSDC0_DAT0",
MTK_EINT_FUNCTION(0, 120),
+ DRV_GRP4,
MTK_FUNCTION(0, "GPIO120"),
MTK_FUNCTION(1, "MSDC0_DAT0"),
MTK_FUNCTION(4, "WATCHDOG"),
MTK_FUNCTION(5, "NLD2")
),
MTK_PIN(
- PINCTRL_PIN(121, "GPIO121"),
- NULL, "mt8516",
+ 121, "GPIO121",
MTK_EINT_FUNCTION(0, 121),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO121")
),
MTK_PIN(
- PINCTRL_PIN(122, "GPIO122"),
- NULL, "mt8516",
+ 122, "GPIO122",
MTK_EINT_FUNCTION(0, 122),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO122")
),
MTK_PIN(
- PINCTRL_PIN(123, "GPIO123"),
- NULL, "mt8516",
+ 123, "GPIO123",
MTK_EINT_FUNCTION(0, 123),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO123")
),
MTK_PIN(
- PINCTRL_PIN(124, "GPIO124"),
- NULL, "mt8516",
+ 124, "GPIO124",
MTK_EINT_FUNCTION(0, 124),
+ DRV_GRP0, // N/A
MTK_FUNCTION(0, "GPIO124")
),
};
--
2.43.0
^ permalink raw reply related
* [RFC PATCH 3/3] arm64: dts: mt8516/mt8167: Update pinctrl nodes for the new paris driver
From: Luca Leonardo Scorcia @ 2026-06-25 10:46 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Sean Wang, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20260625104742.113803-1-l.scorcia@gmail.com>
Update the MediaTek mt8516-mt8167 SoCs descriptions to respect the
constraints of the Paris pinctrl driver.
In those SoCs the pinctrl has base address 0x10005000 for gpio settings
while 0x1000b000 is used for eint configuration.
This change also drops the no longer required syscfg_pctl syscon node
that was used before to access the gpio regmap, fixing the following
dtbs_check errors:
mt8167-pumpkin.dtb: syscfg-pctl@10005000 (syscon): compatible: ['syscon']
is too short
mt8516-pumpkin.dtb: syscfg-pctl@10005000 (syscon): compatible: ['syscon']
is too short
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 15 ++++-----------
arch/arm64/boot/dts/mediatek/mt8516.dtsi | 12 ++++--------
2 files changed, 8 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 27cf32d7ae35..65da6c0538b1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -95,17 +95,6 @@ power-domain@MT8167_POWER_DOMAIN_CONN {
};
};
- pio: pinctrl@1000b000 {
- compatible = "mediatek,mt8167-pinctrl";
- reg = <0 0x1000b000 0 0x1000>;
- mediatek,pctl-regmap = <&syscfg_pctl>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
- };
-
apmixedsys: apmixedsys@10018000 {
compatible = "mediatek,mt8167-apmixedsys", "syscon";
reg = <0 0x10018000 0 0x710>;
@@ -178,3 +167,7 @@ larb2: larb@16010000 {
};
};
};
+
+&pio {
+ compatible = "mediatek,mt8167-pinctrl";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
index b5e753759465..63f36df4d1b4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
@@ -231,17 +231,13 @@ keypad: keypad@10002000 {
status = "disabled";
};
- syscfg_pctl: syscfg-pctl@10005000 {
- compatible = "syscon";
- reg = <0 0x10005000 0 0x1000>;
- };
-
- pio: pinctrl@1000b000 {
+ pio: pinctrl@10005000 {
compatible = "mediatek,mt8516-pinctrl";
- reg = <0 0x1000b000 0 0x1000>;
- mediatek,pctl-regmap = <&syscfg_pctl>;
+ reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
+ reg-names = "base", "eint";
gpio-controller;
#gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 124>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v5 2/3] pwm: add Andes PWM driver support
From: Ben Zong-You Xie @ 2026-06-25 10:32 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-pwm,
devicetree, linux-kernel
In-Reply-To: <ahajkcejv71TwV5f@monoceros>
Hi Uwe,
On Wed, May 27, 2026 at 10:55:32AM +0200, Uwe Kleine-König wrote:
> From: Uwe Kleine-König <ukleinek@kernel.org>
>
> Hello Ben,
>
> On Mon, Mar 30, 2026 at 03:45:44PM +0800, Ben Zong-You Xie via B4 Relay wrote:
> > From: Ben Zong-You Xie <ben717@andestech.com>
> >
> > Add a driver for the PWM controller found in Andes AE350 platforms and
> > QiLai SoCs.
> >
> > The Andes PWM controller features:
> > - 4 independent channels.
> > - Dual clock source support (APB clock and external clock) to provide
> > a flexible range of frequencies.
> > - Support for normal and inversed polarity.
> >
> > The driver implements the .apply() and .get_state() callbacks. Since the
> > clock source of each channel can be selected by programming the
> > register, clock selection logic is implemented to prioritize the
> > external clock to maximize the supported period range, falling back to
> > the APB clock for higher frequency requirements.
> >
> > Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> > ---
> > drivers/pwm/Kconfig | 10 ++
> > drivers/pwm/Makefile | 1 +
> > drivers/pwm/pwm-andes.c | 306 ++++++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 317 insertions(+)
> >
> > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> > index 6f3147518376..b82f2c857ada 100644
> > --- a/drivers/pwm/Kconfig
> > +++ b/drivers/pwm/Kconfig
> > @@ -73,6 +73,16 @@ config PWM_AIROHA
> > To compile this driver as a module, choose M here: the module
> > will be called pwm-airoha.
> >
> > +config PWM_ANDES
> > + tristate "Andes PWM support"
> > + depends on ARCH_ANDES || COMPILE_TEST
> > + help
> > + Generic PWM framework driver for Andes platform, such as QiLai SoC
> > + and AE350 platform.
> > +
> > + To compile this driver as a module, choose M here: the module
> > + will be called pwm-andes.
> > +
> > config PWM_APPLE
> > tristate "Apple SoC PWM support"
> > depends on ARCH_APPLE || COMPILE_TEST
> > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> > index 0dc0d2b69025..858f225289cc 100644
> > --- a/drivers/pwm/Makefile
> > +++ b/drivers/pwm/Makefile
> > @@ -3,6 +3,7 @@ obj-$(CONFIG_PWM) += core.o
> > obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
> > obj-$(CONFIG_PWM_ADP5585) += pwm-adp5585.o
> > obj-$(CONFIG_PWM_AIROHA) += pwm-airoha.o
> > +obj-$(CONFIG_PWM_ANDES) += pwm-andes.o
> > obj-$(CONFIG_PWM_APPLE) += pwm-apple.o
> > obj-$(CONFIG_PWM_ARGON_FAN_HAT) += pwm-argon-fan-hat.o
> > obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
> > diff --git a/drivers/pwm/pwm-andes.c b/drivers/pwm/pwm-andes.c
> > new file mode 100644
> > index 000000000000..835c8db55987
> > --- /dev/null
> > +++ b/drivers/pwm/pwm-andes.c
> > @@ -0,0 +1,306 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Driver for Andes PWM, used in Andes AE350 platform and QiLai SoC
> > + *
> > + * Copyright (C) 2026 Andes Technology Corporation.
> > + *
> > + * Limitations:
> > + * - When disabling a channel, the current period will not be completed, and the
> > + * output will be constant zero.
>
> You could use that to simulate a 0% relative duty cycle instead of
> erroring out.
>
> Just to be sure: A disabled channel emits zero independant of
> ANDES_PWM_CH_CTRL_PARK being set or not?!
>
No, a disabled channel does not always emit zero. Its output is held at
the "park level" selected by the ANDES_PWM_CH_CTRL_PARK field: the
output is driven LOW when the bit is 0 and HIGH when it is 1. So the
"constant zero" wording was wrong; I have corrected the limitation
comment in v6. And yes, as you suggested, v6 uses exactly this to
emulate the duty-cycle extremes instead of erroring out: a 0% relative
duty cycle parks the channel low (PARK=0) and a 100% relative duty cycle
parks it high (PARK=1).
> > + * - The current period will be completed first if reconfiguring.
> > + * - Further, if the reconfiguration changes the clock source, the output will
> > + * not be the old one nor the new one. And the output will be the new one
> > + * until writing to the reload register.
> > + * - The hardware can neither do a 0% nor a 100% relative duty cycle.
> > + */
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/clk.h>
> > +#include <linux/err.h>
> > +#include <linux/math64.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pwm.h>
> > +#include <linux/regmap.h>
> > +#include <linux/time.h>
> > +#include <linux/types.h>
> > +
> > +#define ANDES_PWM_CH_ENABLE 0x1C
> > +#define ANDES_PWM_CH_ENABLE_PWM(ch) BIT(3 + (4 * (ch)))
> > +
> > +#define ANDES_PWM_CH_CTRL(ch) (0x20 + (0x10 * (ch)))
> > +#define ANDES_PWM_CH_CTRL_MODE_PWM BIT(2)
> > +#define ANDES_PWM_CH_CTRL_CLK BIT(3)
> > +#define ANDES_PWM_CH_CTRL_PARK BIT(4)
> > +#define ANDES_PWM_CH_CTRL_MASK GENMASK(4, 0)
> > +
> > +#define ANDES_PWM_CH_RELOAD(ch) (0x24 + (0x10 * (ch)))
> > +#define ANDES_PWM_CH_RELOAD_HIGH GENMASK(31, 16)
> > +#define ANDES_PWM_CH_RELOAD_LOW GENMASK(15, 0)
> > +
> > +#define ANDES_PWM_CH_COUNTER(ch) (0x28 + (0x10 * (ch)))
> > +
> > +#define ANDES_PWM_CH_MAX 4
> > +#define ANDES_PWM_CYCLE_MIN 1
> > +#define ANDES_PWM_CYCLE_MAX 0x10000
> > +
> > +struct andes_pwm {
> > + struct regmap *regmap;
> > + struct clk *pclk;
> > + struct clk *extclk;
> > + unsigned int pclk_rate;
> > + unsigned int extclk_rate;
> > +};
> > +
> > +static const struct regmap_config andes_pwm_regmap_config = {
> > + .name = "andes_pwm",
> > + .reg_bits = 32,
> > + .reg_stride = 4,
> > + .val_bits = 32,
> > + .pad_bits = 0,
> > + .max_register = ANDES_PWM_CH_COUNTER(ANDES_PWM_CH_MAX - 1),
> > + .cache_type = REGCACHE_NONE,
> > +};
> > +
> > +static inline struct andes_pwm *to_andes_pwm(struct pwm_chip *chip)
>
> If you rename this to andes_pwm_from_chip this function has the driver's
> function name prefix, too.
>
Renamed in v6.
> > +{
> > + return pwmchip_get_drvdata(chip);
> > +}
> > +
> > +static int andes_pwm_enable(struct pwm_chip *chip, unsigned int channel,
> > + bool enable)
> > +{
> > + struct andes_pwm *ap = to_andes_pwm(chip);
> > +
> > + return regmap_assign_bits(ap->regmap, ANDES_PWM_CH_ENABLE,
> > + ANDES_PWM_CH_ENABLE_PWM(channel), enable);
> > +}
> > +
> > +static int andes_pwm_config(struct pwm_chip *chip, unsigned int channel,
> > + const struct pwm_state *state)
> > +{
> > + struct andes_pwm *ap = to_andes_pwm(chip);
> > + unsigned int clk_rate = ap->extclk_rate;
> > + unsigned int try = 2;
> > + u64 high_ns = state->duty_cycle;
> > + u64 low_ns = state->period - high_ns;
>
> This results in rounding errors. Consider:
>
> clk_rate = 500000000
> state->duty_cycle = 17
> state->period = 32
>
> then you configure
>
> high_cycles = 8
> low_cycles = 7
>
> which corresponds to a period = 30 ns, while you can do 32 ns. So you
> have to convert state->period to ticks and do the subtraction in the
> tick domain.
>
Fixed in v6.
> > + unsigned int ctrl = ANDES_PWM_CH_CTRL_MODE_PWM;
> > + u64 high_cycles;
> > + u64 low_cycles;
> > + u32 reload;
> > +
> > + /*
> > + * Reload register for PWM mode:
> > + *
> > + * 31 : 16 15 : 0
> > + * PWM16_Hi | PWM16_Lo
> > + *
> > + * The high duration is (PWM16_Hi + 1) cycles and the low duration is
> > + * (PWM16_Lo + 1) cycles. For a duty cycle of 10 cycles and a total
> > + * period of 30 cycles in normal polarity, PWM16_Hi is set to
> > + * 9 (10 - 1) and PWM16_Lo to 19 (30 - 10 - 1). Also, PWM16_Hi is set to
> > + * 19 and PWM16_Lo is set to 9 in inversed polarity.
> > + *
> > + * Because the register stores "cycles - 1", the valid range for
> > + * each phase is 1 to 65536 (0x10000) cycles. This implies the hardware
> > + * cannot achieve a true 0% or 100% duty cycle.
> > + *
> > + * The controller supports two clock sources: the APB clock and an
> > + * external clock. The driver first attempts to use the external clock
> > + * to widest possible range of supported periods. If the requests
> > + * exceeds the valid range of the register, it falls back to the APB
> > + * clock. The request is rejected if the timing cannot be met by either
> > + * source.
> > + */
> > + if (state->polarity == PWM_POLARITY_INVERSED)
> > + swap(high_ns, low_ns);
> > +
> > + while (try) {
> > + high_cycles = mul_u64_u64_div_u64(clk_rate, high_ns,
> > + NSEC_PER_SEC);
> > + low_cycles = mul_u64_u64_div_u64(clk_rate, low_ns,
> > + NSEC_PER_SEC);
> > + if (high_cycles > ANDES_PWM_CYCLE_MAX)
> > + high_cycles = ANDES_PWM_CYCLE_MAX;
> > +
> > + if (low_cycles > ANDES_PWM_CYCLE_MAX)
> > + low_cycles = ANDES_PWM_CYCLE_MAX;
> > +
> > + if (high_cycles >= ANDES_PWM_CYCLE_MIN &&
> > + low_cycles >= ANDES_PWM_CYCLE_MIN)
> > + break;
> > +
> > + try--;
> > + clk_rate = ap->pclk_rate;
> > + }
>
> This loop implements:
>
> if extclk_rate is too high:
> if pclk is too high:
> error out
> else:
> use pclk
> else:
> use extclk
>
> This might be surprising for a user because the emitted period depends
> on the requested duty_cycle.
>
Agreed, that was wrong. In v6 both the clock source and the period are
derived from the requested period alone:
- The driver computes the period in external-clock ticks and uses the
external clock unless that resolves fewer than two ticks (i.e. the period
is too short for it), in which case it uses the APB clock. So the clock
choice depends only on state->period.
- The period is then rounded down to the largest value that stays
representable for every duty split -- at most
ANDES_PWM_CYCLE_MAX + ANDES_PWM_CYCLE_MIN ticks, so both phases always fit
the 16-bit reload fields. The requested duty cycle is split within that
fixed period afterwards.
So changing only the duty cycle no longer moves the emitted period, and an
out-of-range period or duty is now rounded down instead of rejected.
> > +
> > + /*
> > + * try == 0 : no clock is valid
> > + * try == 1 : use APB clock
> > + * try == 2 : use external clock
> > + */
> > + if (!try)
> > + return -EINVAL;
> > +
> > + /*
> > + * If changing the clock source here, the output will not be the old one
> > + * nor the new one. And the output will be the new one until writing to
> > + * the reload register.
>
> And the output will be the new one *after* writing to the reload register?
>
Correct, "until" was a typo for "after". When the clock source changes,
it settles to the new waveform only "after"" the reload register is
written. Fixed in v6.
> > + */
> > + ctrl |= (try == 1) ? ANDES_PWM_CH_CTRL_CLK : 0;
> > + ctrl |= (state->polarity == PWM_POLARITY_INVERSED) ?
> > + ANDES_PWM_CH_CTRL_PARK : 0;
> > + regmap_update_bits(ap->regmap, ANDES_PWM_CH_CTRL(channel),
> > + ANDES_PWM_CH_CTRL_MASK, ctrl);
> > + reload = FIELD_PREP(ANDES_PWM_CH_RELOAD_HIGH, high_cycles - 1) |
> > + FIELD_PREP(ANDES_PWM_CH_RELOAD_LOW, low_cycles - 1);
> > +
> > + return regmap_write(ap->regmap, ANDES_PWM_CH_RELOAD(channel), reload);
> > +}
> > +
> > +static int andes_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> > + const struct pwm_state *state)
> > +{
> > + unsigned int channel = pwm->hwpwm;
> > + int ret;
> > +
> > + if (!state->enabled) {
> > + if (pwm->state.enabled)
> > + andes_pwm_enable(chip, channel, false);
> > +
> > + return 0;
> > + }
> > +
> > + ret = andes_pwm_config(chip, channel, state);
> > + if (ret)
> > + return ret;
> > +
> > + return andes_pwm_enable(chip, channel, true);
> > +}
> > +
> > +static int andes_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
> > + struct pwm_state *state)
> > +{
> > + struct andes_pwm *ap = to_andes_pwm(chip);
> > + unsigned int channel = pwm->hwpwm;
> > + unsigned int ctrl;
> > + unsigned int clk_rate;
> > + unsigned int reload;
> > + u64 high_cycles;
> > + u64 low_cycles;
> > +
> > + regmap_read(ap->regmap, ANDES_PWM_CH_CTRL(channel), &ctrl);
> > + clk_rate = FIELD_GET(ANDES_PWM_CH_CTRL_CLK, ctrl) ? ap->pclk_rate
> > + : ap->extclk_rate;
> > + state->enabled = regmap_test_bits(ap->regmap, ANDES_PWM_CH_ENABLE,
> > + ANDES_PWM_CH_ENABLE_PWM(channel));
> > + state->polarity = regmap_test_bits(ap->regmap,
> > + ANDES_PWM_CH_CTRL(channel),
> > + ANDES_PWM_CH_CTRL_PARK);
>
> This can be simplified to use FIELD_GET(..., ctrl);
>
Done in v6.
> > + regmap_read(ap->regmap, ANDES_PWM_CH_RELOAD(channel), &reload);
> > + high_cycles = FIELD_GET(ANDES_PWM_CH_RELOAD_HIGH, reload) + 1;
> > + low_cycles = FIELD_GET(ANDES_PWM_CH_RELOAD_LOW, reload) + 1;
> > +
> > + /*
> > + * high_cycles and low_cycles are both 16 bits, and NSEC_PER_SEC is 30
> > + * bits. Thus, the multiplication is safe from overflow
>
> Missing . at the end.
>
Fixed in v6.
> > + */
> > + if (state->polarity == PWM_POLARITY_NORMAL) {
> > + state->duty_cycle = DIV_ROUND_UP_ULL(high_cycles * NSEC_PER_SEC,
> > + clk_rate);
> > + state->period = state->duty_cycle +
> > + DIV_ROUND_UP_ULL(low_cycles * NSEC_PER_SEC,
> > + clk_rate);
> > + } else {
> > + state->duty_cycle = DIV_ROUND_UP_ULL(low_cycles * NSEC_PER_SEC,
> > + clk_rate);
> > + state->period = state->duty_cycle +
> > + DIV_ROUND_UP_ULL(high_cycles * NSEC_PER_SEC,
> > + clk_rate);
>
> Here is a rounding error. You need
>
> state->period = DIV_ROUND_UP_ULL((low_cycles + high_cycles) * NSEC_PER_SEC, clk_rate);
>
> (for both polarities, so it can be moved out of the if).
>
> To see the difference, consider clk_rate = 2 * NSEC_PER_SEC,
> high_cycles = 15 and low_cycles = 15.
>
Fixed in v6.
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static const struct pwm_ops andes_pwm_ops = {
> > + .apply = andes_pwm_apply,
> > + .get_state = andes_pwm_get_state,
> > +};
> > +
> > +static int andes_pwm_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct pwm_chip *chip;
> > + struct andes_pwm *ap;
> > + void __iomem *reg_base;
> > + int ret;
> > +
> > + chip = devm_pwmchip_alloc(dev, ANDES_PWM_CH_MAX, sizeof(*ap));
> > + if (IS_ERR(chip))
> > + return PTR_ERR(chip);
> > +
> > + ap = to_andes_pwm(chip);
> > + reg_base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(reg_base))
> > + return dev_err_probe(dev, PTR_ERR(reg_base),
> > + "failed to map I/O space\n");
> > +
> > + ap->pclk = devm_clk_get_enabled(dev, "pclk");
> > + if (IS_ERR(ap->pclk))
> > + return dev_err_probe(dev, PTR_ERR(ap->pclk),
> > + "failed to get APB clock\n");
> > +
> > + ap->extclk = devm_clk_get_optional_enabled(dev, "extclk");
> > + if (IS_ERR(ap->extclk))
> > + return dev_err_probe(dev, PTR_ERR(ap->extclk),
> > + "failed to get external clock\n");
> > +
> > + /*
> > + * If the clock rate is greater than 10^9, there may be an overflow when
> > + * calculating the cycles in andes_pwm_config()
> > + */
> > + ap->pclk_rate = clk_get_rate(ap->pclk);
> > + if (ap->pclk_rate > NSEC_PER_SEC)
> > + ap->pclk = NULL;
>
> This is not enough to prevent that pclk is used.
>
Right -- the clock selection keys off the rate, not the pointer, so nulling
ap->pclk left the out-of-range pclk_rate in place and the clock could still
be picked. v6 caps the rate itself to 0 instead:
ap->pclk_rate = pclk_rate > NSEC_PER_SEC ? 0 : pclk_rate;
ap->extclk_rate = extclk_rate > NSEC_PER_SEC ? 0 : extclk_rate;
A 0 rate resolves to zero ticks in .apply(), so that source is never selected.
> > + ap->extclk_rate = ap->extclk ? clk_get_rate(ap->extclk) : 0;
> > + if (ap->extclk_rate > NSEC_PER_SEC)
> > + ap->extclk = NULL;
> > +
> > + if (!ap->pclk && !ap->extclk)
> > + return dev_err_probe(dev, -EINVAL, "clocks are out of range\n");
>
> If you mention the clk rates in the error message, the problem to fix
> becomes easier to identify.
>
Done in v6.
> > + ap->regmap = devm_regmap_init_mmio(dev, reg_base,
> > + &andes_pwm_regmap_config);
> > + if (IS_ERR(ap->regmap)) {
> > + return dev_err_probe(dev, PTR_ERR(ap->regmap),
> > + "failed to initialize regmap\n");
> > + }
>
> Don't use { ... } for single statements. Please start error messages
> with a capital letter.
>
Done in v6.
> > +
> > + chip->ops = &andes_pwm_ops;
> > + ret = devm_pwmchip_add(dev, chip);
> > + if (ret)
> > + return dev_err_probe(dev, ret, "failed to add pwm chip\n");
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id andes_pwm_of_match[] = {
> > + { .compatible = "andestech,ae350-pwm" },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, andes_pwm_of_match);
> > +
> > +static struct platform_driver andes_pwm_driver = {
> > + .driver = {
> > + .name = "andes_pwm",
> > + .of_match_table = andes_pwm_of_match,
> > + },
> > + .probe = andes_pwm_probe,
> > +};
> > +module_platform_driver(andes_pwm_driver);
> > +
> > +MODULE_AUTHOR("Ben Zong-You Xie <ben717@andestech.com>");
> > +MODULE_DESCRIPTION("Andes PWM driver");
> > +MODULE_LICENSE("GPL");
>
> Best regards
> Uwe
Thanks,
Ben
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