* Re: [PATCH v3 2/2] hwmon: (pmbus/vt7505) Add driver for Analog Devices MAX16545/MAX16550 and Volterra VT7505
From: Guenter Roeck @ 2026-07-24 17:53 UTC (permalink / raw)
To: Pradhan, Sanman, linux-hwmon@vger.kernel.org
Cc: robh@kernel.org, krzk+dt@kernel.org, krzk@kernel.org,
conor+dt@kernel.org, corbet@lwn.net, skhan@linuxfoundation.org,
devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, Sanman Pradhan, Debjit Ghosh,
Jawahar Balaji Thirumalaisamy, Santhanakrishnan Balraj, Brian Mak
In-Reply-To: <20260724164919.247162-3-sanman.pradhan@hpe.com>
Hi,
On 7/24/26 09:50, Pradhan, Sanman wrote:
> From: Georgi Vlaev <gvlaev@juniper.net>
>
> Add a PMBus driver for the Analog Devices MAX16545 and MAX16550, and the
> Volterra VT7505 controllers. The driver reports input/output voltage,
> input/output current, input power and temperature over PMBus. All values
> use the direct data format. Peak input voltage, output voltage, output
> current, input power and temperature readings are exposed and can be
> reset.
>
> The reported current and power depend on the external current-report
> resistor connected to the ILOAD pin, which can be provided through the
> "adi,rload-ohms" device tree property.
>
> On the MAX16550 and VT7505, the severe-OCP deglitch time can optionally
> be configured with the "adi,ocp-severe-filter-us" device tree property.
> When omitted, the existing hardware setting is left unchanged.
>
> Signed-off-by: Georgi Vlaev <gvlaev@juniper.net>
> Co-developed-by: Dhruva Devineni <ddevineni@juniper.net>
> Signed-off-by: Dhruva Devineni <ddevineni@juniper.net>
> Co-developed-by: Debjit Ghosh <dghosh@juniper.net>
> Signed-off-by: Debjit Ghosh <dghosh@juniper.net>
> Co-developed-by: JawaharBalaji Thirumalaisamy <jawaharb@juniper.net>
> Signed-off-by: JawaharBalaji Thirumalaisamy <jawaharb@juniper.net>
> Co-developed-by: Avadhut Naik <avadhutn@juniper.net>
> Signed-off-by: Avadhut Naik <avadhutn@juniper.net>
> Co-developed-by: Santhanakrishnan Balraj <sbalraj@juniper.net>
> Signed-off-by: Santhanakrishnan Balraj <sbalraj@juniper.net>
> Co-developed-by: Brian Mak <makb@juniper.net>
> Signed-off-by: Brian Mak <makb@juniper.net>
> Signed-off-by: Sanman Pradhan <psanman@juniper.net>
> ---
I get delivery errors for the following addresses.
ddevineni@juniper.net
gvlaev@juniper.net
avadhutn@juniper.net
meaning they are quite obviously _not_ involved in the patch approval path.
Please drop those addresses. Also, per Documentation/process/submitting-patches.rst:
Any further SoBs (Signed-off-by:'s) following the author's SoB are from
people handling and transporting the patch, but were not involved in its
development. SoB chains should reflect the **real** route a patch took
as it was propagated to the maintainers and ultimately to Linus, with
the first SoB entry signalling primary authorship of a single author.
Does the above SoB sequence really reflect the approval patch for this
patch ?
Thanks,
Guenter
^ permalink raw reply
* Re: [PATCH v18 2/2] platform: Add initial synology microp driver
From: Markus Probst @ 2026-07-24 17:35 UTC (permalink / raw)
To: sashiko-reviews; +Cc: conor+dt, devicetree, robh, ojeda, linux-leds, lee
In-Reply-To: <20260724172159.C43981F000E9@smtp.kernel.org>
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On Fri, 2026-07-24 at 17:21 +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
> - [High] The dynamically formatted `name` CString for the alert LED is dropped immediately after initialization, leaving a dangling pointer in the LED subsystem.
> - [High] The serdev device is never opened, causing subsequent LED operations to hang the kernel worker thread indefinitely.
> - [High] The `blink_set` callback sleeps by acquiring a Mutex and waiting for synchronous serial I/O, but it is called from an RCU read-side critical section.
> - [High] Incorrect struct field declaration order causes `power_name` to be freed before the `power` LED device is unregistered.
> - [Medium] Hardware blinking is not disabled when setting a solid brightness level, preventing the LED from turning on solidly.
> - [Medium] The driver lacks a device-level lock to serialize commands sent to the microcontroller over the shared serdev bus, allowing concurrent LED updates to interleave.
> --
>
> --- Patch [2]: [PATCH v18 2/2] platform: Add initial synology microp driver ---
> commit 7eb4c67aa911615ee8b6562c3f14a129d9b90280
> Author: Markus Probst <markus.probst@posteo.de>
>
> platform: Add initial synology microp driver
>
> Add a initial synology microp driver, written in Rust.
> The driver targets a microcontroller found in Synology NAS devices. It
> currently only supports controlling of the power led, status led, alert
> led and usb led. Other components such as fan control or handling
> on-device buttons will be added once the required rust abstractions are
> there.
>
> > diff --git a/drivers/platform/synology_microp/command.rs b/drivers/platform/synology_microp/command.rs
> > new file mode 100644
> > index 0000000000000..490719490391c
> > --- /dev/null
> > +++ b/drivers/platform/synology_microp/command.rs
> > @@ -0,0 +1,54 @@
> [ ... ]
> > +impl Command {
> > + pub(crate) fn write(self, dev: &serdev::Device<Bound>) -> Result {
> > + dev.write_all(
>
> [Severity: Medium]
> Since multiple LEDs can be updated concurrently, does this write_all() call
> need a device-level lock to prevent interleaving commands on the shared serdev
> bus?
>
> > + match self {
> [ ... ]
> > + },
> > + 0,
> > + )?;
> > + dev.wait_until_sent(0);
>
> [Severity: High]
> Could this code cause a BUG by sleeping in an atomic context?
>
> When the LED core invokes blink_set() (for instance, via a timer trigger),
> it holds an rwlock and executes in an RCU read-side critical section. The
> wait_until_sent() call performs a sleeping wait, which could cause a panic
> or instability when called from that atomic context.
BLOCKING = true is set in every LedOps implementation. Therefore
sleeping is allowed.
>
> Additionally, could this block indefinitely if dev.open() hasn't been called?
This function does not exist. The serdev rust abstraction opens it
automatically before probe.
Also if it isn't open, it would cause a null pointer dereference
instead of blocking indefinitely.
>
> > + Ok(())
> > + }
> > +}
> > diff --git a/drivers/platform/synology_microp/led.rs b/drivers/platform/synology_microp/led.rs
> > new file mode 100644
> > index 0000000000000..01cad98616fdf
> > --- /dev/null
> > +++ b/drivers/platform/synology_microp/led.rs
> > @@ -0,0 +1,304 @@
> [ ... ]
> > +#[pin_data]
> > +pub(crate) struct Data<'bound> {
> > + #[pin]
> > + status: led::MultiColorDevice<'bound, StatusLedHandler>,
> > + power_name: CString,
> > + #[pin]
> > + power: led::Device<'bound, LedHandler>,
>
> [Severity: High]
> Does this struct field declaration order cause a use-after-free during
> device unbinding?
>
> In Rust, struct fields are dropped in the order they are declared. Because
> power_name is declared before power, the CString buffer for the name is freed
> first. The kernel would be left with a dangling pointer in led_cdev->name while
> the power LED device is still registered and active, which could lead to memory
> corruption if read concurrently before unregistration completes.
`power_name` only needs to outlive the initialization. It is copied by
the led subsystem on register.
>
> > + alert: Option<Pin<KBox<led::Device<'bound, LedHandler>>>>,
> > + usb_copy: Option<Pin<KBox<led::Device<'bound, LedHandler>>>>,
> > + esata: Option<Pin<KBox<led::Device<'bound, LedHandler>>>>,
> > +}
> > +
> > +impl<'bound> Data<'bound> {
> > + pub(super) fn register<'a>(
> > + dev: &'bound serdev::Device<Bound>,
> > + model: &'a Model,
> > + ) -> impl PinInit<Self, Error> + 'a
> > + where
> > + 'bound: 'a,
> > + {
> > + pin_init_scope(move || {
> > + Ok(try_pin_init!(Self {
> [ ... ]
> > + alert: {
> > + if let Some(color) = model.led_alert {
> > + let name = CString::try_from_fmt(fmt!(
> > + "synology:{}:alarm",
> > + color.as_c_str().to_str()?
> > + ))?;
> > + Some(KBox::pin_init(
> > + led::DeviceBuilder::new().color(color).name(&name).build(
>
> [Severity: High]
> Is the dynamically formatted name CString dropped immediately after this
> initialization block?
Yes.
>
> The local CString variable is passed as a reference to the builder but is
> dropped at the end of the `if let` block. The LED classdev will retain a
> dangling pointer to its freed buffer, leading to a use-after-free when the LED
> subsystem accesses the name.
No, it will not retain a pointer. It copies the string in the
initialization.
>
> > + dev,
> > + try_pin_init!(LedHandler {
> > + blink <- new_mutex!(false),
> > + command: Command::AlertLed,
> > + }),
> > + ),
> > + GFP_KERNEL,
> > + )?)
> > + } else {
> > + None
> > + }
> > + },
> [ ... ]
> > + fn brightness_set<'bound>(
> > + &self,
> > + dev: &'bound Self::Bus,
> > + _classdev: &led::Device<'bound, Self>,
> > + brightness: u32,
> > + ) -> Result<()> {
> > + let mut blink = self.blink.lock();
> > + (self.command)(if brightness == 0 {
> > + *blink = false;
> > + State::Off
> > + } else if *blink {
> > + State::Blink
> > + } else {
> > + State::On
> > + })
>
> [Severity: Medium]
> If the LED is currently blinking, does this logic prevent it from turning on
> solidly?
>
> When a solid brightness is requested and the blink state is true, the state
> remains State::Blink. The blink state needs to be reset so the hardware can
> stop blinking and remain solidly on.
Led Subsystem documentation explicitly says
- "passing LED_OFF stops blinking"
- "passing LED_OFF stops hardware blinking"
- "To turn off blinking, use the API function led_brightness_set() with
brightness value LED_OFF, which should stop any software timers that
may have been required for blinking."
It is intended to continue blinking if a non-0 brightness is set.
See https://docs.kernel.org/leds/leds-class.html
>
> > + .write(dev)?;
> > +
> > + Ok(())
> > + }
> > +
> > + fn blink_set<'bound>(
> > + &self,
> > + dev: &'bound Self::Bus,
> > + _classdev: &led::Device<'bound, Self>,
> > + delay_on: &mut usize,
> > + delay_off: &mut usize,
> > + ) -> Result<()> {
> > + let mut blink = self.blink.lock();
>
> [Severity: High]
> Is it safe to acquire this sleeping Mutex here?
>
> Since the blink_set() callback can be called from an RCU read-side critical
> section by the LED core, acquiring a Mutex here could lead to a kernel panic.
BLOCKING = true is set in every LedOps implementation. Therefore
sleeping is allowed.
>
> > +
> > + (self.command)(if *delay_on == 0 && *delay_off != 0 {
> [ ... ]
> > + fn brightness_set<'bound>(
> > + &self,
> > + dev: &'bound Self::Bus,
> > + classdev: &led::MultiColorDevice<'bound, Self>,
> > + brightness: u32,
> > + ) -> Result<()> {
> > + let mut blink = self.blink.lock();
> > + if brightness == 0 {
> > + *blink = false;
> > + }
> > +
> > + let amber_brightness = classdev.subleds()[1].brightness();
> > +
> > + let (color, subled_brightness) = if amber_brightness == 0 {
> > + (StatusLedColor::Green, classdev.subleds()[0].brightness())
> > + } else {
> > + (StatusLedColor::Amber, amber_brightness)
> > + };
> > +
> > + Command::StatusLed(
> > + color,
> > + if subled_brightness == 0 {
> > + State::Off
> > + } else if *blink {
> > + State::Blink
> > + } else {
> > + State::On
> > + },
>
> [Severity: Medium]
> Does the multi-color status LED suffer from the same logic flaw as
> LedHandler::brightness_set(), where the LED stays blinking instead of turning
> solid when a solid brightness level is requested?
As explained above, it is not a flaw.
>
> > + )
> > + .write(dev)
> > + }
> > +
> > + fn blink_set<'bound>(
> > + &self,
> [ ... ]
> > diff --git a/drivers/platform/synology_microp/synology_microp.rs b/drivers/platform/synology_microp/synology_microp.rs
> > new file mode 100644
> > index 0000000000000..f7168309e6116
> > --- /dev/null
> > +++ b/drivers/platform/synology_microp/synology_microp.rs
> > @@ -0,0 +1,91 @@
> [ ... ]
> > + fn probe<'bound>(
> > + dev: &'bound serdev::Device<device::Core<'_>>,
> > + model: Option<&'bound Model>,
> > + ) -> impl PinInit<Self::Data<'bound>, kernel::error::Error> + 'bound {
> > + pin_init_scope(move || {
> > + let model = model.ok_or(EINVAL)?;
> > +
> > + dev.set_baudrate(9600).map_err(|_| EINVAL)?;
> > + dev.set_flow_control(false);
> > + dev.set_parity(serdev::Parity::None)?;
> > +
> > + Ok(try_pin_init!(SynologyMicropDriver {
>
> [Severity: High]
> Is a call to dev.open() missing during this setup?
This function does not exist. The serdev rust abstraction automatically
opens the device before probe.
>
> The probe function configures the serdev device but doesn't seem to open it.
> When subsequent operations try to write to the bus, the closed tty port will
> accept 0 bytes and cause the driver's write logic to hang forever.
Writing to a closed serdev device would case a null pointer
dereference, which does not happen in testing.
>
> > + led <- led::Data::register(dev, model),
> > + }))
> > + })
> > + }
> > +}
This review does not contain a single issue. All false positives.
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^ permalink raw reply
* Re: [PATCH v3 2/2] hwmon: (pmbus/vt7505) Add driver for Analog Devices MAX16545/MAX16550 and Volterra VT7505
From: Guenter Roeck @ 2026-07-24 17:27 UTC (permalink / raw)
To: Pradhan, Sanman
Cc: linux-hwmon@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org,
krzk@kernel.org, conor+dt@kernel.org, corbet@lwn.net,
skhan@linuxfoundation.org, devicetree@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
Sanman Pradhan, Georgi Vlaev, Dhruva Devineni, Debjit Ghosh,
Jawahar Balaji Thirumalaisamy, Avadhut Naik,
Santhanakrishnan Balraj, Brian Mak
In-Reply-To: <20260724164919.247162-3-sanman.pradhan@hpe.com>
On Fri, Jul 24, 2026 at 04:50:00PM +0000, Pradhan, Sanman wrote:
> From: Georgi Vlaev <gvlaev@juniper.net>
>
> Add a PMBus driver for the Analog Devices MAX16545 and MAX16550, and the
> Volterra VT7505 controllers. The driver reports input/output voltage,
> input/output current, input power and temperature over PMBus. All values
> use the direct data format. Peak input voltage, output voltage, output
> current, input power and temperature readings are exposed and can be
> reset.
>
> The reported current and power depend on the external current-report
> resistor connected to the ILOAD pin, which can be provided through the
> "adi,rload-ohms" device tree property.
>
> On the MAX16550 and VT7505, the severe-OCP deglitch time can optionally
> be configured with the "adi,ocp-severe-filter-us" device tree property.
> When omitted, the existing hardware setting is left unchanged.
>
...
> +static void vt7505_set_m(int *m, u32 rload)
> +{
> + u64 val = (u64)*m * rload;
> +
> + /* Make sure m fits the s32 type */
> + *m = DIV_ROUND_CLOSEST_ULL(val, 1000);
The largest possible value of m is 7578. That means that this _will_
overflow if rload >= 283383960 because 283383960 * 7578 / 1000 =
2147483648.88, rounded up to to 2147483649 == 0x80000001.
Please add a range check in the probe function.
Thanks,
Guenter
^ permalink raw reply
* Re: [PATCH v4 3/3] arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes
From: sashiko-bot @ 2026-07-24 17:24 UTC (permalink / raw)
To: Imran Shaik; +Cc: robh, conor+dt, devicetree
In-Reply-To: <20260724-shikra-audiocorecc-v4-3-0a89bb13d817@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Unclocked MMIO regmap exposure on IQS variant leads to synchronous external abort.
--
--- Patch [3]: [PATCH v4 3/3] arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes ---
commit a056f645f45682f1008b321f5e639505f22bb979
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>
arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes
This commit adds support for the Audio Core Clock Controller and Audio Core
CSR nodes for the Qualcomm Shikra SoC. It describes different enablement
requirements based on the SoC variant (CQM, CQS, IQS).
> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> index 4e5bc9e17c8ed..b744534572d63 100644
> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
[ ... ]
> @@ -640,6 +641,22 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
> };
> };
>
> + audiocorecc: clock-controller@a0a0000 {
> + compatible = "qcom,shikra-audiocorecc";
> + reg = <0x0 0x0a0a0000 0x0 0x10000>;
> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> + <&sleep_clk>,
> + <0>;
> + #clock-cells = <1>;
> + status = "reserved"; /* Owned by Modem firmware */
> + };
> +
> + audiocore_csr: reset-controller@a0b4000 {
> + compatible = "qcom,shikra-audiocore-csr";
> + reg = <0x0 0x0a0b4000 0x0 0x1000>;
> + #reset-cells = <1>;
> + };
[Severity: High]
Will this node probe by default on the IQS variant?
The commit message mentions that on the IQS variant, no clocks or resets are
needed. Since this node lacks a status = "disabled" property, it appears it
will be left enabled and probed on all variants, including IQS.
If the audiocore-csr driver registers an MMIO regmap without clock management,
could reading from the regmap debugfs file on an IQS device attempt an
unclocked register access and trigger a synchronous external abort?
> sram@c11e000 {
> compatible = "qcom,shikra-imem", "mmio-sram";
> reg = <0x0 0x0c11e000 0x0 0x1000>;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260724-shikra-audiocorecc-v4-0-0a89bb13d817@oss.qualcomm.com?part=3
^ permalink raw reply
* Re: [PATCH v18 2/2] platform: Add initial synology microp driver
From: sashiko-bot @ 2026-07-24 17:21 UTC (permalink / raw)
To: Markus Probst; +Cc: conor+dt, devicetree, robh, ojeda, linux-leds, lee
In-Reply-To: <20260724-synology_microp_initial-v18-2-fb2f49f10e77@posteo.de>
Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
- [High] The dynamically formatted `name` CString for the alert LED is dropped immediately after initialization, leaving a dangling pointer in the LED subsystem.
- [High] The serdev device is never opened, causing subsequent LED operations to hang the kernel worker thread indefinitely.
- [High] The `blink_set` callback sleeps by acquiring a Mutex and waiting for synchronous serial I/O, but it is called from an RCU read-side critical section.
- [High] Incorrect struct field declaration order causes `power_name` to be freed before the `power` LED device is unregistered.
- [Medium] Hardware blinking is not disabled when setting a solid brightness level, preventing the LED from turning on solidly.
- [Medium] The driver lacks a device-level lock to serialize commands sent to the microcontroller over the shared serdev bus, allowing concurrent LED updates to interleave.
--
--- Patch [2]: [PATCH v18 2/2] platform: Add initial synology microp driver ---
commit 7eb4c67aa911615ee8b6562c3f14a129d9b90280
Author: Markus Probst <markus.probst@posteo.de>
platform: Add initial synology microp driver
Add a initial synology microp driver, written in Rust.
The driver targets a microcontroller found in Synology NAS devices. It
currently only supports controlling of the power led, status led, alert
led and usb led. Other components such as fan control or handling
on-device buttons will be added once the required rust abstractions are
there.
> diff --git a/drivers/platform/synology_microp/command.rs b/drivers/platform/synology_microp/command.rs
> new file mode 100644
> index 0000000000000..490719490391c
> --- /dev/null
> +++ b/drivers/platform/synology_microp/command.rs
> @@ -0,0 +1,54 @@
[ ... ]
> +impl Command {
> + pub(crate) fn write(self, dev: &serdev::Device<Bound>) -> Result {
> + dev.write_all(
[Severity: Medium]
Since multiple LEDs can be updated concurrently, does this write_all() call
need a device-level lock to prevent interleaving commands on the shared serdev
bus?
> + match self {
[ ... ]
> + },
> + 0,
> + )?;
> + dev.wait_until_sent(0);
[Severity: High]
Could this code cause a BUG by sleeping in an atomic context?
When the LED core invokes blink_set() (for instance, via a timer trigger),
it holds an rwlock and executes in an RCU read-side critical section. The
wait_until_sent() call performs a sleeping wait, which could cause a panic
or instability when called from that atomic context.
Additionally, could this block indefinitely if dev.open() hasn't been called?
> + Ok(())
> + }
> +}
> diff --git a/drivers/platform/synology_microp/led.rs b/drivers/platform/synology_microp/led.rs
> new file mode 100644
> index 0000000000000..01cad98616fdf
> --- /dev/null
> +++ b/drivers/platform/synology_microp/led.rs
> @@ -0,0 +1,304 @@
[ ... ]
> +#[pin_data]
> +pub(crate) struct Data<'bound> {
> + #[pin]
> + status: led::MultiColorDevice<'bound, StatusLedHandler>,
> + power_name: CString,
> + #[pin]
> + power: led::Device<'bound, LedHandler>,
[Severity: High]
Does this struct field declaration order cause a use-after-free during
device unbinding?
In Rust, struct fields are dropped in the order they are declared. Because
power_name is declared before power, the CString buffer for the name is freed
first. The kernel would be left with a dangling pointer in led_cdev->name while
the power LED device is still registered and active, which could lead to memory
corruption if read concurrently before unregistration completes.
> + alert: Option<Pin<KBox<led::Device<'bound, LedHandler>>>>,
> + usb_copy: Option<Pin<KBox<led::Device<'bound, LedHandler>>>>,
> + esata: Option<Pin<KBox<led::Device<'bound, LedHandler>>>>,
> +}
> +
> +impl<'bound> Data<'bound> {
> + pub(super) fn register<'a>(
> + dev: &'bound serdev::Device<Bound>,
> + model: &'a Model,
> + ) -> impl PinInit<Self, Error> + 'a
> + where
> + 'bound: 'a,
> + {
> + pin_init_scope(move || {
> + Ok(try_pin_init!(Self {
[ ... ]
> + alert: {
> + if let Some(color) = model.led_alert {
> + let name = CString::try_from_fmt(fmt!(
> + "synology:{}:alarm",
> + color.as_c_str().to_str()?
> + ))?;
> + Some(KBox::pin_init(
> + led::DeviceBuilder::new().color(color).name(&name).build(
[Severity: High]
Is the dynamically formatted name CString dropped immediately after this
initialization block?
The local CString variable is passed as a reference to the builder but is
dropped at the end of the `if let` block. The LED classdev will retain a
dangling pointer to its freed buffer, leading to a use-after-free when the LED
subsystem accesses the name.
> + dev,
> + try_pin_init!(LedHandler {
> + blink <- new_mutex!(false),
> + command: Command::AlertLed,
> + }),
> + ),
> + GFP_KERNEL,
> + )?)
> + } else {
> + None
> + }
> + },
[ ... ]
> + fn brightness_set<'bound>(
> + &self,
> + dev: &'bound Self::Bus,
> + _classdev: &led::Device<'bound, Self>,
> + brightness: u32,
> + ) -> Result<()> {
> + let mut blink = self.blink.lock();
> + (self.command)(if brightness == 0 {
> + *blink = false;
> + State::Off
> + } else if *blink {
> + State::Blink
> + } else {
> + State::On
> + })
[Severity: Medium]
If the LED is currently blinking, does this logic prevent it from turning on
solidly?
When a solid brightness is requested and the blink state is true, the state
remains State::Blink. The blink state needs to be reset so the hardware can
stop blinking and remain solidly on.
> + .write(dev)?;
> +
> + Ok(())
> + }
> +
> + fn blink_set<'bound>(
> + &self,
> + dev: &'bound Self::Bus,
> + _classdev: &led::Device<'bound, Self>,
> + delay_on: &mut usize,
> + delay_off: &mut usize,
> + ) -> Result<()> {
> + let mut blink = self.blink.lock();
[Severity: High]
Is it safe to acquire this sleeping Mutex here?
Since the blink_set() callback can be called from an RCU read-side critical
section by the LED core, acquiring a Mutex here could lead to a kernel panic.
> +
> + (self.command)(if *delay_on == 0 && *delay_off != 0 {
[ ... ]
> + fn brightness_set<'bound>(
> + &self,
> + dev: &'bound Self::Bus,
> + classdev: &led::MultiColorDevice<'bound, Self>,
> + brightness: u32,
> + ) -> Result<()> {
> + let mut blink = self.blink.lock();
> + if brightness == 0 {
> + *blink = false;
> + }
> +
> + let amber_brightness = classdev.subleds()[1].brightness();
> +
> + let (color, subled_brightness) = if amber_brightness == 0 {
> + (StatusLedColor::Green, classdev.subleds()[0].brightness())
> + } else {
> + (StatusLedColor::Amber, amber_brightness)
> + };
> +
> + Command::StatusLed(
> + color,
> + if subled_brightness == 0 {
> + State::Off
> + } else if *blink {
> + State::Blink
> + } else {
> + State::On
> + },
[Severity: Medium]
Does the multi-color status LED suffer from the same logic flaw as
LedHandler::brightness_set(), where the LED stays blinking instead of turning
solid when a solid brightness level is requested?
> + )
> + .write(dev)
> + }
> +
> + fn blink_set<'bound>(
> + &self,
[ ... ]
> diff --git a/drivers/platform/synology_microp/synology_microp.rs b/drivers/platform/synology_microp/synology_microp.rs
> new file mode 100644
> index 0000000000000..f7168309e6116
> --- /dev/null
> +++ b/drivers/platform/synology_microp/synology_microp.rs
> @@ -0,0 +1,91 @@
[ ... ]
> + fn probe<'bound>(
> + dev: &'bound serdev::Device<device::Core<'_>>,
> + model: Option<&'bound Model>,
> + ) -> impl PinInit<Self::Data<'bound>, kernel::error::Error> + 'bound {
> + pin_init_scope(move || {
> + let model = model.ok_or(EINVAL)?;
> +
> + dev.set_baudrate(9600).map_err(|_| EINVAL)?;
> + dev.set_flow_control(false);
> + dev.set_parity(serdev::Parity::None)?;
> +
> + Ok(try_pin_init!(SynologyMicropDriver {
[Severity: High]
Is a call to dev.open() missing during this setup?
The probe function configures the serdev device but doesn't seem to open it.
When subsequent operations try to write to the bus, the closed tty port will
accept 0 bytes and cause the driver's write logic to hang forever.
> + led <- led::Data::register(dev, model),
> + }))
> + })
> + }
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260724-synology_microp_initial-v18-0-fb2f49f10e77@posteo.de?part=2
^ permalink raw reply
* [PATCH v4 3/3] arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes
From: Imran Shaik @ 2026-07-24 17:15 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Konrad Dybcio
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
linux-kernel, devicetree, Imran Shaik, Konrad Dybcio
In-Reply-To: <20260724-shikra-audiocorecc-v4-0-0a89bb13d817@oss.qualcomm.com>
Add support for Audio Core Clock Controller (AudioCoreCC) and Audio Core
CSR nodes on Qualcomm Shikra SoC. The Audio Core Clocks and Resets support
differs across Shikra variants based on Audio subsystem enablement as
follows:
- CQM variant: The QAIF driver runs on HLOS, hence both clocks and resets
are required to be supported on HLOS.
- CQS variant: The QAIF driver runs on the Modem, and required clocks are
handled on Modem, so from HLOS only resets are needed.
- IQS variant: no soundwire codes, hence no clocks/resets are needed.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 4 ++++
arch/arm64/boot/dts/qcom/shikra.dtsi | 17 +++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index 0a52ab9b7a4c34d371f5ac23efe59d1c9d2723f4..0883c480bfbc80d7bead966b9ba932dee8a77bbf 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -23,6 +23,10 @@ chosen {
};
};
+&audiocorecc {
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 4e5bc9e17c8ed8914733ac9fdc9b69128b40216e..b744534572d63349c4274ffbe5cacbb8fdb4197d 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,shikra-audiocorecc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
@@ -640,6 +641,22 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
};
};
+ audiocorecc: clock-controller@a0a0000 {
+ compatible = "qcom,shikra-audiocorecc";
+ reg = <0x0 0x0a0a0000 0x0 0x10000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&sleep_clk>,
+ <0>;
+ #clock-cells = <1>;
+ status = "reserved"; /* Owned by Modem firmware */
+ };
+
+ audiocore_csr: reset-controller@a0b4000 {
+ compatible = "qcom,shikra-audiocore-csr";
+ reg = <0x0 0x0a0b4000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
sram@c11e000 {
compatible = "qcom,shikra-imem", "mmio-sram";
reg = <0x0 0x0c11e000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related
* [PATCH v4 2/3] clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC
From: Imran Shaik @ 2026-07-24 17:15 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Konrad Dybcio
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
linux-kernel, devicetree, Imran Shaik, Konrad Dybcio,
Dmitry Baryshkov
In-Reply-To: <20260724-shikra-audiocorecc-v4-0-0a89bb13d817@oss.qualcomm.com>
Add support for Audio Core Clock Controller (AUDIOCORECC) and Audio Core
CSR resets on Qualcomm Shikra SoC.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/audiocorecc-shikra.c | 810 ++++++++++++++++++++++++++++++++++
3 files changed, 821 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 63f271aff1771bea0885fb753dd28d02fd7d4ab6..29ae37ece3141438d6fb8162cc7ad3a361c5323c 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -192,6 +192,16 @@ config CLK_NORD_GCC
SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination
of GCC, SE_GCC, NE_GCC and NW_GCC.
+config CLK_SHIKRA_AUDIOCORECC
+ tristate "Shikra Audio Core Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ select CLK_SHIKRA_GCC
+ default m if ARCH_QCOM
+ help
+ Support for the Audio Core clock controller on Qualcomm Shikra devices.
+ Say Y if you want to use AudioCoreCC clocks required to support audio
+ devices and it's functionality.
+
config CLK_SHIKRA_GCC
tristate "Shikra Global Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index db7689ee5dc63bc8b7d12b8222188bc1e1ff78ba..f26a79658bb88c957f990d76d295a5a9a09bb7ee 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o
obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o
obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o
+obj-$(CONFIG_CLK_SHIKRA_AUDIOCORECC) += audiocorecc-shikra.o
obj-$(CONFIG_CLK_SHIKRA_GCC) += gcc-shikra.o
obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
diff --git a/drivers/clk/qcom/audiocorecc-shikra.c b/drivers/clk/qcom/audiocorecc-shikra.c
new file mode 100644
index 0000000000000000000000000000000000000000..19f67b50d6234655ebb8cbc242a8d7efbb0a6039
--- /dev/null
+++ b/drivers/clk/qcom/audiocorecc-shikra.c
@@ -0,0 +1,810 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,shikra-audiocorecc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "reset.h"
+
+enum {
+ DT_BI_TCXO,
+ DT_SLEEP_CLK,
+ DT_AUD_REF_CLK_SRC,
+};
+
+enum {
+ P_AUD_REF_CLK_SRC,
+ P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX,
+ P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2,
+ P_BI_TCXO,
+ P_SLEEP_CLK,
+};
+
+static const struct pll_vco spark_vco[] = {
+ { 500000000, 1000000000, 2 },
+};
+
+/* 614.4 MHz Configuration */
+static const struct alpha_pll_config audio_core_cc_dig_pll_config = {
+ .l = 0x20,
+ .alpha = 0x0,
+ .vco_val = BIT(21),
+ .post_div_val = 0x28100,
+ .post_div_mask = GENMASK(17, 8),
+ .vco_mask = GENMASK(21, 20),
+ .main_output_mask = BIT(0),
+ .aux_output_mask = BIT(1),
+ .aux2_output_mask = BIT(2),
+ .config_ctl_val = 0x4001055b,
+ .test_ctl_hi_val = 0x1,
+ .test_ctl_hi_mask = 0x1,
+};
+
+static struct clk_alpha_pll audio_core_cc_dig_pll = {
+ .offset = 0x0,
+ .config = &audio_core_cc_dig_pll_config,
+ .vco_table = spark_vco,
+ .num_vco = ARRAY_SIZE(spark_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_dig_pll",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_fixed_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor audio_core_cc_dig_pll_out_aux = {
+ .mult = 1,
+ .div = 5,
+ .hw.init = &(struct clk_init_data) {
+ .name = "audio_core_cc_dig_pll_out_aux",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &audio_core_cc_dig_pll.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_fixed_factor audio_core_cc_dig_pll_out_aux2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data) {
+ .name = "audio_core_cc_dig_pll_out_aux2",
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &audio_core_cc_dig_pll.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static const struct parent_map audio_core_cc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_AUD_REF_CLK_SRC, 1 },
+ { P_SLEEP_CLK, 2 },
+ { P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 4 },
+ { P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 6 },
+};
+
+static const struct clk_parent_data audio_core_cc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .index = DT_AUD_REF_CLK_SRC },
+ { .index = DT_SLEEP_CLK },
+ { .hw = &audio_core_cc_dig_pll_out_aux.hw },
+ { .hw = &audio_core_cc_dig_pll_out_aux2.hw },
+};
+
+static const struct freq_tbl ftbl_audio_core_cc_aif_if0_clk_src[] = {
+ F(240000, P_BI_TCXO, 10, 1, 8),
+ F(256000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 32),
+ F(512000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 16),
+ F(768000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 16),
+ F(1024000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 8),
+ F(1536000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 8),
+ F(2048000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 4),
+ F(3072000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 4),
+ F(4096000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 2),
+ F(6144000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 2),
+ F(8192000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 0, 0),
+ F(9600000, P_BI_TCXO, 2, 0, 0),
+ F(12288000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 0, 0),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 audio_core_cc_aif_if0_clk_src = {
+ .cmd_rcgr = 0x104c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = audio_core_cc_parent_map_0,
+ .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aif_if0_clk_src",
+ .parent_data = audio_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 audio_core_cc_aif_if1_clk_src = {
+ .cmd_rcgr = 0x10b0,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = audio_core_cc_parent_map_0,
+ .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aif_if1_clk_src",
+ .parent_data = audio_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 audio_core_cc_aif_if2_clk_src = {
+ .cmd_rcgr = 0x1114,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = audio_core_cc_parent_map_0,
+ .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aif_if2_clk_src",
+ .parent_data = audio_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_audio_core_cc_aif_if3_clk_src[] = {
+ F(240000, P_BI_TCXO, 10, 1, 8),
+ F(256000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 32),
+ F(512000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 16),
+ F(768000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 16),
+ F(1024000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 8),
+ F(1536000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 8),
+ F(2048000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 4),
+ F(3072000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 4),
+ F(4096000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 2),
+ F(6144000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 2),
+ F(8192000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 0, 0),
+ F(9600000, P_BI_TCXO, 2, 0, 0),
+ F(12288000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 0, 0),
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0),
+ F(49152000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 audio_core_cc_aif_if3_clk_src = {
+ .cmd_rcgr = 0x1178,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = audio_core_cc_parent_map_0,
+ .freq_tbl = ftbl_audio_core_cc_aif_if3_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aif_if3_clk_src",
+ .parent_data = audio_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_audio_core_cc_aud_dma_clk_src[] = {
+ F(38400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 8, 0, 0),
+ F(102400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 3, 0, 0),
+ F(153600000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 2, 0, 0),
+ F(307200000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 audio_core_cc_aud_dma_clk_src = {
+ .cmd_rcgr = 0x1028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = audio_core_cc_parent_map_0,
+ .freq_tbl = ftbl_audio_core_cc_aud_dma_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aud_dma_clk_src",
+ .parent_data = audio_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_audio_core_cc_bus_clk_src[] = {
+ F(38400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 8, 0, 0),
+ F(76800000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 audio_core_cc_bus_clk_src = {
+ .cmd_rcgr = 0x1008,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = audio_core_cc_parent_map_0,
+ .freq_tbl = ftbl_audio_core_cc_bus_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_bus_clk_src",
+ .parent_data = audio_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 audio_core_cc_ext_mclka_clk_src = {
+ .cmd_rcgr = 0x123c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = audio_core_cc_parent_map_0,
+ .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_ext_mclka_clk_src",
+ .parent_data = audio_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 audio_core_cc_ext_mclkb_clk_src = {
+ .cmd_rcgr = 0x125c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = audio_core_cc_parent_map_0,
+ .freq_tbl = ftbl_audio_core_cc_aif_if0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_ext_mclkb_clk_src",
+ .parent_data = audio_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_audio_core_cc_lpaif_pcmoe_clk_src[] = {
+ F(9600000, P_BI_TCXO, 2, 0, 0),
+ F(15360000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 8, 0, 0),
+ F(30720000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 4, 0, 0),
+ F(61440000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 audio_core_cc_lpaif_pcmoe_clk_src = {
+ .cmd_rcgr = 0x12ac,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = audio_core_cc_parent_map_0,
+ .freq_tbl = ftbl_audio_core_cc_lpaif_pcmoe_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_lpaif_pcmoe_clk_src",
+ .parent_data = audio_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_audio_core_cc_tx_mclk_rcg_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 audio_core_cc_tx_mclk_rcg_clk_src = {
+ .cmd_rcgr = 0x127c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = audio_core_cc_parent_map_0,
+ .freq_tbl = ftbl_audio_core_cc_tx_mclk_rcg_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_tx_mclk_rcg_clk_src",
+ .parent_data = audio_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(audio_core_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_regmap_div audio_core_cc_cdiv_tx_mclk_div_clk_src = {
+ .reg = 0x129c,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_cdiv_tx_mclk_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch audio_core_cc_aif_if0_ebit_clk = {
+ .halt_reg = 0x1068,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x1068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aif_if0_ebit_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_aif_if0_ibit_clk = {
+ .halt_reg = 0x1064,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1064,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aif_if0_ibit_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_aif_if0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_aif_if1_ebit_clk = {
+ .halt_reg = 0x10cc,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x10cc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aif_if1_ebit_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_aif_if1_ibit_clk = {
+ .halt_reg = 0x10c8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10c8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aif_if1_ibit_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_aif_if1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_aif_if2_ebit_clk = {
+ .halt_reg = 0x1130,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x1130,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aif_if2_ebit_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_aif_if2_ibit_clk = {
+ .halt_reg = 0x112c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x112c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aif_if2_ibit_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_aif_if2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_aif_if3_ebit_clk = {
+ .halt_reg = 0x1194,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x1194,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aif_if3_ebit_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_aif_if3_ibit_clk = {
+ .halt_reg = 0x1190,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1190,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aif_if3_ibit_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_aif_if3_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_aud_dma_clk = {
+ .halt_reg = 0x1040,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x1040,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aud_dma_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_aud_dma_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_aud_dma_mem_clk = {
+ .halt_reg = 0x1044,
+ .halt_check = BRANCH_HALT,
+ .hwcg_reg = 0x1044,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x1044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_aud_dma_mem_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_aud_dma_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_bus_clk = {
+ .halt_reg = 0x1020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x1020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_bus_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_bus_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_ext_mclka_out_clk = {
+ .halt_reg = 0x1254,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1254,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_ext_mclka_out_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_ext_mclka_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_ext_mclkb_out_clk = {
+ .halt_reg = 0x1274,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1274,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_ext_mclkb_out_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_ext_mclkb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_im_sleep_clk = {
+ .halt_reg = 0x12cc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12cc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_im_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_lpaif_pcmoe_clk = {
+ .halt_reg = 0x12c4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12c4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_lpaif_pcmoe_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_lpaif_pcmoe_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_rx_mclk_2x_clk = {
+ .halt_reg = 0x1298,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1298,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_rx_mclk_2x_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_rx_mclk_clk = {
+ .halt_reg = 0x12a4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12a4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_rx_mclk_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_sampling_clk = {
+ .halt_reg = 0x1000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_sampling_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_tx_mclk_2x_clk = {
+ .halt_reg = 0x1294,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1294,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_tx_mclk_2x_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch audio_core_cc_tx_mclk_clk = {
+ .halt_reg = 0x12a0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12a0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "audio_core_cc_tx_mclk_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_hw *audio_core_cc_shikra_hws[] = {
+ [AUDIO_CORE_CC_DIG_PLL_OUT_AUX] = &audio_core_cc_dig_pll_out_aux.hw,
+ [AUDIO_CORE_CC_DIG_PLL_OUT_AUX2] = &audio_core_cc_dig_pll_out_aux2.hw,
+};
+
+static struct clk_regmap *audio_core_cc_shikra_clocks[] = {
+ [AUDIO_CORE_CC_AIF_IF0_CLK_SRC] = &audio_core_cc_aif_if0_clk_src.clkr,
+ [AUDIO_CORE_CC_AIF_IF0_EBIT_CLK] = &audio_core_cc_aif_if0_ebit_clk.clkr,
+ [AUDIO_CORE_CC_AIF_IF0_IBIT_CLK] = &audio_core_cc_aif_if0_ibit_clk.clkr,
+ [AUDIO_CORE_CC_AIF_IF1_CLK_SRC] = &audio_core_cc_aif_if1_clk_src.clkr,
+ [AUDIO_CORE_CC_AIF_IF1_EBIT_CLK] = &audio_core_cc_aif_if1_ebit_clk.clkr,
+ [AUDIO_CORE_CC_AIF_IF1_IBIT_CLK] = &audio_core_cc_aif_if1_ibit_clk.clkr,
+ [AUDIO_CORE_CC_AIF_IF2_CLK_SRC] = &audio_core_cc_aif_if2_clk_src.clkr,
+ [AUDIO_CORE_CC_AIF_IF2_EBIT_CLK] = &audio_core_cc_aif_if2_ebit_clk.clkr,
+ [AUDIO_CORE_CC_AIF_IF2_IBIT_CLK] = &audio_core_cc_aif_if2_ibit_clk.clkr,
+ [AUDIO_CORE_CC_AIF_IF3_CLK_SRC] = &audio_core_cc_aif_if3_clk_src.clkr,
+ [AUDIO_CORE_CC_AIF_IF3_EBIT_CLK] = &audio_core_cc_aif_if3_ebit_clk.clkr,
+ [AUDIO_CORE_CC_AIF_IF3_IBIT_CLK] = &audio_core_cc_aif_if3_ibit_clk.clkr,
+ [AUDIO_CORE_CC_AUD_DMA_CLK] = &audio_core_cc_aud_dma_clk.clkr,
+ [AUDIO_CORE_CC_AUD_DMA_CLK_SRC] = &audio_core_cc_aud_dma_clk_src.clkr,
+ [AUDIO_CORE_CC_AUD_DMA_MEM_CLK] = &audio_core_cc_aud_dma_mem_clk.clkr,
+ [AUDIO_CORE_CC_BUS_CLK] = &audio_core_cc_bus_clk.clkr,
+ [AUDIO_CORE_CC_BUS_CLK_SRC] = &audio_core_cc_bus_clk_src.clkr,
+ [AUDIO_CORE_CC_CDIV_TX_MCLK_DIV_CLK_SRC] = &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr,
+ [AUDIO_CORE_CC_DIG_PLL] = &audio_core_cc_dig_pll.clkr,
+ [AUDIO_CORE_CC_EXT_MCLKA_CLK_SRC] = &audio_core_cc_ext_mclka_clk_src.clkr,
+ [AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK] = &audio_core_cc_ext_mclka_out_clk.clkr,
+ [AUDIO_CORE_CC_EXT_MCLKB_CLK_SRC] = &audio_core_cc_ext_mclkb_clk_src.clkr,
+ [AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK] = &audio_core_cc_ext_mclkb_out_clk.clkr,
+ [AUDIO_CORE_CC_IM_SLEEP_CLK] = &audio_core_cc_im_sleep_clk.clkr,
+ [AUDIO_CORE_CC_LPAIF_PCMOE_CLK] = &audio_core_cc_lpaif_pcmoe_clk.clkr,
+ [AUDIO_CORE_CC_LPAIF_PCMOE_CLK_SRC] = &audio_core_cc_lpaif_pcmoe_clk_src.clkr,
+ [AUDIO_CORE_CC_RX_MCLK_2X_CLK] = &audio_core_cc_rx_mclk_2x_clk.clkr,
+ [AUDIO_CORE_CC_RX_MCLK_CLK] = &audio_core_cc_rx_mclk_clk.clkr,
+ [AUDIO_CORE_CC_SAMPLING_CLK] = &audio_core_cc_sampling_clk.clkr,
+ [AUDIO_CORE_CC_TX_MCLK_2X_CLK] = &audio_core_cc_tx_mclk_2x_clk.clkr,
+ [AUDIO_CORE_CC_TX_MCLK_CLK] = &audio_core_cc_tx_mclk_clk.clkr,
+ [AUDIO_CORE_CC_TX_MCLK_RCG_CLK_SRC] = &audio_core_cc_tx_mclk_rcg_clk_src.clkr,
+};
+
+static struct clk_alpha_pll *audio_core_cc_shikra_plls[] = {
+ &audio_core_cc_dig_pll,
+};
+
+static const struct qcom_cc_driver_data audio_core_cc_shikra_driver_data = {
+ .alpha_plls = audio_core_cc_shikra_plls,
+ .num_alpha_plls = ARRAY_SIZE(audio_core_cc_shikra_plls),
+};
+
+static const struct regmap_config audio_core_cc_shikra_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x305c,
+ .fast_io = true,
+};
+
+static const struct qcom_reset_map audio_core_csr_shikra_resets[] = {
+ [AUDIO_CORE_CSR_RX_SWR_CGCR] = { 0x1c, 1 },
+ [AUDIO_CORE_CSR_TX_SWR_CGCR] = { 0x30, 1 },
+};
+
+static const struct regmap_config audio_core_csr_shikra_regmap_config = {
+ .name = "audio_core_cc_shikra_reset",
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .fast_io = true,
+ .max_register = 0x34,
+};
+
+static const struct qcom_cc_desc audio_core_csr_shikra_desc = {
+ .config = &audio_core_csr_shikra_regmap_config,
+ .resets = audio_core_csr_shikra_resets,
+ .num_resets = ARRAY_SIZE(audio_core_csr_shikra_resets),
+};
+
+static const struct qcom_cc_desc audio_core_cc_shikra_desc = {
+ .config = &audio_core_cc_shikra_regmap_config,
+ .clk_hws = audio_core_cc_shikra_hws,
+ .num_clk_hws = ARRAY_SIZE(audio_core_cc_shikra_hws),
+ .clks = audio_core_cc_shikra_clocks,
+ .num_clks = ARRAY_SIZE(audio_core_cc_shikra_clocks),
+ .driver_data = &audio_core_cc_shikra_driver_data,
+};
+
+static const struct of_device_id audio_core_cc_shikra_match_table[] = {
+ { .compatible = "qcom,shikra-audiocorecc", .data = &audio_core_cc_shikra_desc },
+ { .compatible = "qcom,shikra-audiocore-csr", .data = &audio_core_csr_shikra_desc },
+ { }
+};
+MODULE_DEVICE_TABLE(of, audio_core_cc_shikra_match_table);
+
+static int audio_core_cc_shikra_probe(struct platform_device *pdev)
+{
+ const struct qcom_cc_desc *desc;
+
+ desc = device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
+ return qcom_cc_probe(pdev, desc);
+}
+
+static struct platform_driver audio_core_cc_shikra_driver = {
+ .probe = audio_core_cc_shikra_probe,
+ .driver = {
+ .name = "audiocorecc-shikra",
+ .of_match_table = audio_core_cc_shikra_match_table,
+ },
+};
+
+module_platform_driver(audio_core_cc_shikra_driver);
+
+MODULE_DESCRIPTION("QTI AUDIOCORECC Shikra Driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related
* [PATCH v4 1/3] dt-bindings: clock: qcom: Add Qualcomm Shikra AudioCoreCC and AudioCoreCSR
From: Imran Shaik @ 2026-07-24 17:15 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Konrad Dybcio
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
linux-kernel, devicetree, Imran Shaik, Krzysztof Kozlowski
In-Reply-To: <20260724-shikra-audiocorecc-v4-0-0a89bb13d817@oss.qualcomm.com>
Add device tree bindings for the Audio Core Clock Controller (AudioCoreCC)
that provides clocks and Audio Core CSR that provides resets on Qualcomm
Shikra SoC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
.../bindings/clock/qcom,shikra-audiocorecc.yaml | 55 ++++++++++++++++++++++
.../bindings/reset/qcom,shikra-audiocore-csr.yaml | 42 +++++++++++++++++
.../dt-bindings/clock/qcom,shikra-audiocorecc.h | 49 +++++++++++++++++++
3 files changed, 146 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..d59f7e47a0d7d9ee9def49be9954038e43785e91
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,shikra-audiocorecc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Audio Core Clock Controller for Qualcomm Shikra SoC
+
+maintainers:
+ - Imran Shaik <imran.shaik@oss.qualcomm.com>
+
+description: |
+ Audio core clock control module provides the clocks on Qualcomm Shikra
+ SoC platform.
+
+ See also:
+ - include/dt-bindings/clock/qcom,shikra-audiocorecc.h
+
+properties:
+ compatible:
+ const: qcom,shikra-audiocorecc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board sleep clock
+ - description: Audio ref clock source
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/clock/qcom,shikra-gcc.h>
+ clock-controller@a0a0000 {
+ compatible = "qcom,shikra-audiocorecc";
+ reg = <0x0a0a0000 0x10000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&sleep_clk>,
+ <&aud_ref_clk_src>;
+ #clock-cells = <1>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/reset/qcom,shikra-audiocore-csr.yaml b/Documentation/devicetree/bindings/reset/qcom,shikra-audiocore-csr.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..bfad1d20e7cd1281c4c182d5f9f887d8c4c86125
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/qcom,shikra-audiocore-csr.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/qcom,shikra-audiocore-csr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Audio Core CSR for Qualcomm Shikra SoC
+
+maintainers:
+ - Imran Shaik <imran.shaik@oss.qualcomm.com>
+
+description: |
+ Audio Core CSR module provides the resets on Qualcomm Shikra SoC platform.
+
+ See also:
+ - include/dt-bindings/clock/qcom,shikra-audiocorecc.h
+
+properties:
+ compatible:
+ const: qcom,shikra-audiocore-csr
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@a0b4000 {
+ compatible = "qcom,shikra-audiocore-csr";
+ reg = <0x0a0b4000 0x1000>;
+ #reset-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,shikra-audiocorecc.h b/include/dt-bindings/clock/qcom,shikra-audiocorecc.h
new file mode 100644
index 0000000000000000000000000000000000000000..0e64a42523f1ec4213ce8cbbbe6f8262d414f0eb
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,shikra-audiocorecc.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_AUDIO_CORE_CC_SHIKRA_H
+#define _DT_BINDINGS_CLK_QCOM_AUDIO_CORE_CC_SHIKRA_H
+
+/* AUDIO_CORE_CC clocks */
+#define AUDIO_CORE_CC_DIG_PLL_OUT_AUX 0
+#define AUDIO_CORE_CC_DIG_PLL_OUT_AUX2 1
+#define AUDIO_CORE_CC_DIG_PLL 2
+#define AUDIO_CORE_CC_AIF_IF0_CLK_SRC 3
+#define AUDIO_CORE_CC_AIF_IF0_EBIT_CLK 4
+#define AUDIO_CORE_CC_AIF_IF0_IBIT_CLK 5
+#define AUDIO_CORE_CC_AIF_IF1_CLK_SRC 6
+#define AUDIO_CORE_CC_AIF_IF1_EBIT_CLK 7
+#define AUDIO_CORE_CC_AIF_IF1_IBIT_CLK 8
+#define AUDIO_CORE_CC_AIF_IF2_CLK_SRC 9
+#define AUDIO_CORE_CC_AIF_IF2_EBIT_CLK 10
+#define AUDIO_CORE_CC_AIF_IF2_IBIT_CLK 11
+#define AUDIO_CORE_CC_AIF_IF3_CLK_SRC 12
+#define AUDIO_CORE_CC_AIF_IF3_EBIT_CLK 13
+#define AUDIO_CORE_CC_AIF_IF3_IBIT_CLK 14
+#define AUDIO_CORE_CC_AUD_DMA_CLK 15
+#define AUDIO_CORE_CC_AUD_DMA_CLK_SRC 16
+#define AUDIO_CORE_CC_AUD_DMA_MEM_CLK 17
+#define AUDIO_CORE_CC_BUS_CLK 18
+#define AUDIO_CORE_CC_BUS_CLK_SRC 19
+#define AUDIO_CORE_CC_CDIV_TX_MCLK_DIV_CLK_SRC 20
+#define AUDIO_CORE_CC_EXT_MCLKA_CLK_SRC 21
+#define AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK 22
+#define AUDIO_CORE_CC_EXT_MCLKB_CLK_SRC 23
+#define AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK 24
+#define AUDIO_CORE_CC_IM_SLEEP_CLK 25
+#define AUDIO_CORE_CC_LPAIF_PCMOE_CLK 26
+#define AUDIO_CORE_CC_LPAIF_PCMOE_CLK_SRC 27
+#define AUDIO_CORE_CC_RX_MCLK_2X_CLK 28
+#define AUDIO_CORE_CC_RX_MCLK_CLK 29
+#define AUDIO_CORE_CC_SAMPLING_CLK 30
+#define AUDIO_CORE_CC_TX_MCLK_2X_CLK 31
+#define AUDIO_CORE_CC_TX_MCLK_CLK 32
+#define AUDIO_CORE_CC_TX_MCLK_RCG_CLK_SRC 33
+
+/* AUDIO_CORE_CSR resets */
+#define AUDIO_CORE_CSR_RX_SWR_CGCR 0
+#define AUDIO_CORE_CSR_TX_SWR_CGCR 1
+
+#endif
--
2.34.1
^ permalink raw reply related
* [PATCH v4 0/3] clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC
From: Imran Shaik @ 2026-07-24 17:15 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Konrad Dybcio
Cc: Ajit Pandey, Taniya Das, Jagadeesh Kona, linux-arm-msm, linux-clk,
linux-kernel, devicetree, Imran Shaik, Krzysztof Kozlowski,
Konrad Dybcio, Dmitry Baryshkov
This series adds support for the Audio Core Clock Controller (AUDIOCORECC)
and Audio Core CSR resets on Qualcomm Shikra SoC. The Audio Core Clocks and
Resets support differs across Shikra variants based on Audio subsystem
enablement as follows:
- CQM variant: The QAIF driver runs on HLOS, hence both clocks and resets
are required to be supported on HLOS.
- CQS variant: The QAIF driver runs on the Modem, and required clocks are
handled on Modem, so from HLOS only resets are needed.
- IQS variant: no soundwire codes, hence no clocks/resets are needed.
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
---
Changes in v4:
- Dropped "clk: qcom: common: Register reset controller only when resets are present" patch
- Sashiko AI review pointed a valid GDSC-only corner case issue with this
change, will address it in a separate patch.
- This patch is not needed for this series, after splitting AudioCoreCC
clocks and resets into different devices.
- Added NULL check for device_get_match_data() in driver [Sashiko AI review]
- Removed unnecessary <linux/mod_devicetable.h> include in driver [Uwe]
- Collected the R-By tags received on v2.
- Link to v3: https://lore.kernel.org/r/20260723-shikra-audiocorecc-v3-0-90b878ae0d4e@oss.qualcomm.com
Changes in v3:
- Rebased on next-20260722, as the dependent RPMCC/GCC and Shikra base
DTS changes were merged.
- Separated the audiocorecc and audiocore_csr bindings into separate schema
docs [Rob]
- Moved the AudioCoreCSR schema to bindings/reset/, since it now only
describes a reset controller.
- Updated audiocorecc DTS node to use status reserved [Konrad]
- Kept audiocore_csr node globally enabled by default in DTS [Konrad]
- Collected all the R-By received on v1.
- Link to v2: https://lore.kernel.org/r/20260708-shikra-audiocorecc-v2-0-b320d822cdd0@oss.qualcomm.com
Changes in v2:
- Separated AudioCoreCC and AudioCoreCSR nodes as both resides in two
different register spaces. [Konrad]
- Updated bindings and driver patches to handle the separate node
compatibles.
- Updated resets in driver patch to handle HW_CTL bit.
- Link to v1: https://lore.kernel.org/r/20260605-shikra-audiocorecc-v1-0-7ee6b5f2d928@oss.qualcomm.com
---
Imran Shaik (3):
dt-bindings: clock: qcom: Add Qualcomm Shikra AudioCoreCC and AudioCoreCSR
clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC
arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes
.../bindings/clock/qcom,shikra-audiocorecc.yaml | 55 ++
.../bindings/reset/qcom,shikra-audiocore-csr.yaml | 42 ++
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 4 +
arch/arm64/boot/dts/qcom/shikra.dtsi | 17 +
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/audiocorecc-shikra.c | 810 +++++++++++++++++++++
.../dt-bindings/clock/qcom,shikra-audiocorecc.h | 49 ++
8 files changed, 988 insertions(+)
---
base-commit: b4515cf4156356e8f4fe6e0fdc17f59adab9772f
change-id: 20260605-shikra-audiocorecc-85efef073474
Best regards,
--
Imran Shaik <imran.shaik@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v18 1/2] dt-bindings: embedded-controller: Add synology microp devices
From: sashiko-bot @ 2026-07-24 17:15 UTC (permalink / raw)
To: Markus Probst; +Cc: robh, lee, devicetree, conor+dt, linux-leds, ojeda
In-Reply-To: <20260724-synology_microp_initial-v18-1-fb2f49f10e77@posteo.de>
> Add the Synology Microp devicetree bindings. Those devices are
> microcontrollers found on Synology NAS devices. They are connected to a
> serial port on the host device.
>
> Those devices are used to control certain LEDs, fan speeds, a beeper, to
> handle buttons, fan failures and to properly shutdown and reboot the
> device.
>
> The device has a different feature set depending on the Synology NAS
> model, like having different number of fans, buttons and leds. Depending
> on the architecture of the model, they also need a different system
> shutdown behaviour.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> Signed-off-by: Markus Probst <markus.probst@posteo.de>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260724-synology_microp_initial-v18-0-fb2f49f10e77@posteo.de?part=1
^ permalink raw reply
* [PATCH v18 2/2] platform: Add initial synology microp driver
From: Markus Probst @ 2026-07-24 17:10 UTC (permalink / raw)
To: Hans de Goede, Ilpo Järvinen, Bryan O'Donoghue,
Lee Jones, Pavel Machek, Miguel Ojeda, Boqun Feng, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Trevor Gross, Danilo Krummrich, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Daniel Almeida,
Tamir Duberstein, Alexandre Courbot, Onur Özkan
Cc: platform-driver-x86, linux-leds, devicetree, linux-kernel,
rust-for-linux, Markus Probst
In-Reply-To: <20260724-synology_microp_initial-v18-0-fb2f49f10e77@posteo.de>
Add a initial synology microp driver, written in Rust.
The driver targets a microcontroller found in Synology NAS devices. It
currently only supports controlling of the power led, status led, alert
led and usb led. Other components such as fan control or handling
on-device buttons will be added once the required rust abstractions are
there.
This driver can be used both on arm and x86, thus it goes into the root
directory of drivers/platform.
Tested successfully on a Synology DS923+.
Signed-off-by: Markus Probst <markus.probst@posteo.de>
---
MAINTAINERS | 7 +
drivers/platform/Kconfig | 2 +
drivers/platform/Makefile | 1 +
drivers/platform/synology_microp/Kconfig | 13 +
drivers/platform/synology_microp/Makefile | 5 +
drivers/platform/synology_microp/command.rs | 54 ++++
drivers/platform/synology_microp/led.rs | 304 +++++++++++++++++++++
drivers/platform/synology_microp/model.rs | 49 ++++
.../platform/synology_microp/synology_microp.rs | 91 ++++++
9 files changed, 526 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index dacc8640926a..ced5fea318f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -26145,6 +26145,13 @@ F: drivers/dma-buf/sync_*
F: include/linux/sync_file.h
F: include/uapi/linux/sync_file.h
+SYNOLOGY MICROP DRIVER
+M: Markus Probst <markus.probst@posteo.de>
+L: platform-driver-x86@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/embedded-controller/synology,ds918p-microp.yaml
+F: drivers/platform/synology_microp/
+
SYNOPSYS ARC ARCHITECTURE
M: Vineet Gupta <vgupta@kernel.org>
L: linux-snps-arc@lists.infradead.org
diff --git a/drivers/platform/Kconfig b/drivers/platform/Kconfig
index 312788f249c9..996050566a4a 100644
--- a/drivers/platform/Kconfig
+++ b/drivers/platform/Kconfig
@@ -22,3 +22,5 @@ source "drivers/platform/arm64/Kconfig"
source "drivers/platform/raspberrypi/Kconfig"
source "drivers/platform/wmi/Kconfig"
+
+source "drivers/platform/synology_microp/Kconfig"
diff --git a/drivers/platform/Makefile b/drivers/platform/Makefile
index fa322e7f8716..2381872e9133 100644
--- a/drivers/platform/Makefile
+++ b/drivers/platform/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_SURFACE_PLATFORMS) += surface/
obj-$(CONFIG_ARM64_PLATFORM_DEVICES) += arm64/
obj-$(CONFIG_BCM2835_VCHIQ) += raspberrypi/
obj-$(CONFIG_ACPI_WMI) += wmi/
+obj-$(CONFIG_SYNOLOGY_MICROP) += synology_microp/
diff --git a/drivers/platform/synology_microp/Kconfig b/drivers/platform/synology_microp/Kconfig
new file mode 100644
index 000000000000..8878cfb7bcdd
--- /dev/null
+++ b/drivers/platform/synology_microp/Kconfig
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config SYNOLOGY_MICROP
+ tristate "Synology Microp driver"
+ depends on LEDS_CLASS && LEDS_CLASS_MULTICOLOR
+ depends on RUST_SERIAL_DEV_BUS_ABSTRACTIONS
+ help
+ Enable support for the EC found in Synology NAS devices.
+
+ This is needed to properly shutdown and reboot the device, as well as
+ additional functionality like fan and LED control.
+
+ This driver is work in progress and may not be fully functional.
diff --git a/drivers/platform/synology_microp/Makefile b/drivers/platform/synology_microp/Makefile
new file mode 100644
index 000000000000..2681a793d6d8
--- /dev/null
+++ b/drivers/platform/synology_microp/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_SYNOLOGY_MICROP) += synology-microp.o
+synology-microp-y += synology_microp.o
+
diff --git a/drivers/platform/synology_microp/command.rs b/drivers/platform/synology_microp/command.rs
new file mode 100644
index 000000000000..490719490391
--- /dev/null
+++ b/drivers/platform/synology_microp/command.rs
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use kernel::{
+ device::Bound,
+ error::Result,
+ serdev, //
+};
+
+use crate::led;
+
+#[expect(
+ clippy::enum_variant_names,
+ reason = "future variants will not end with Led"
+)]
+pub(crate) enum Command {
+ PowerLed(led::State),
+ StatusLed(led::StatusLedColor, led::State),
+ AlertLed(led::State),
+ UsbLed(led::State),
+ EsataLed(led::State),
+}
+
+impl Command {
+ pub(crate) fn write(self, dev: &serdev::Device<Bound>) -> Result {
+ dev.write_all(
+ match self {
+ Self::PowerLed(led::State::On) => &[0x34],
+ Self::PowerLed(led::State::Blink) => &[0x35],
+ Self::PowerLed(led::State::Off) => &[0x36],
+
+ Self::StatusLed(_, led::State::Off) => &[0x37],
+ Self::StatusLed(led::StatusLedColor::Green, led::State::On) => &[0x38],
+ Self::StatusLed(led::StatusLedColor::Green, led::State::Blink) => &[0x39],
+ Self::StatusLed(led::StatusLedColor::Amber, led::State::On) => &[0x3A],
+ Self::StatusLed(led::StatusLedColor::Amber, led::State::Blink) => &[0x3B],
+
+ Self::AlertLed(led::State::On) => &[0x4C, 0x41, 0x31],
+ Self::AlertLed(led::State::Blink) => &[0x4C, 0x41, 0x32],
+ Self::AlertLed(led::State::Off) => &[0x4C, 0x41, 0x33],
+
+ Self::UsbLed(led::State::On) => &[0x40],
+ Self::UsbLed(led::State::Blink) => &[0x41],
+ Self::UsbLed(led::State::Off) => &[0x42],
+
+ Self::EsataLed(led::State::On) => &[0x4C, 0x45, 0x31],
+ Self::EsataLed(led::State::Blink) => &[0x4C, 0x45, 0x32],
+ Self::EsataLed(led::State::Off) => &[0x4C, 0x45, 0x33],
+ },
+ 0,
+ )?;
+ dev.wait_until_sent(0);
+ Ok(())
+ }
+}
diff --git a/drivers/platform/synology_microp/led.rs b/drivers/platform/synology_microp/led.rs
new file mode 100644
index 000000000000..01cad98616fd
--- /dev/null
+++ b/drivers/platform/synology_microp/led.rs
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use kernel::{
+ device::Bound,
+ led::{
+ self,
+ LedOps,
+ MultiColorSubLed, //
+ },
+ new_mutex,
+ prelude::*,
+ serdev,
+ str::CString,
+ sync::Mutex,
+ time::Delta, //
+};
+use pin_init::pin_init_scope;
+
+use crate::{
+ command::Command,
+ model::Model, //
+};
+
+#[pin_data]
+pub(crate) struct Data<'bound> {
+ #[pin]
+ status: led::MultiColorDevice<'bound, StatusLedHandler>,
+ power_name: CString,
+ #[pin]
+ power: led::Device<'bound, LedHandler>,
+ alert: Option<Pin<KBox<led::Device<'bound, LedHandler>>>>,
+ usb_copy: Option<Pin<KBox<led::Device<'bound, LedHandler>>>>,
+ esata: Option<Pin<KBox<led::Device<'bound, LedHandler>>>>,
+}
+
+impl<'bound> Data<'bound> {
+ pub(super) fn register<'a>(
+ dev: &'bound serdev::Device<Bound>,
+ model: &'a Model,
+ ) -> impl PinInit<Self, Error> + 'a
+ where
+ 'bound: 'a,
+ {
+ pin_init_scope(move || {
+ Ok(try_pin_init!(Self {
+ status <- led::DeviceBuilder::new()
+ .color(led::Color::Multi)
+ .name(c"synology:multicolor:status")
+ .build_multicolor(
+ dev,
+ try_pin_init!(StatusLedHandler {
+ blink <- new_mutex!(false),
+ }),
+ &[
+ MultiColorSubLed::new(led::Color::Green).initial_intensity(1),
+ MultiColorSubLed::new(led::Color::Amber),
+ ],
+ ),
+ power_name: CString::try_from_fmt(fmt!(
+ "synology:{}:power",
+ model.led_power.as_c_str().to_str()?
+ ))?,
+ power <- led::DeviceBuilder::new()
+ .color(model.led_power)
+ .name(power_name)
+ .build(
+ dev,
+ try_pin_init!(LedHandler {
+ blink <- new_mutex!(false),
+ command: Command::PowerLed,
+ }),
+ ),
+ alert: {
+ if let Some(color) = model.led_alert {
+ let name = CString::try_from_fmt(fmt!(
+ "synology:{}:alarm",
+ color.as_c_str().to_str()?
+ ))?;
+ Some(KBox::pin_init(
+ led::DeviceBuilder::new().color(color).name(&name).build(
+ dev,
+ try_pin_init!(LedHandler {
+ blink <- new_mutex!(false),
+ command: Command::AlertLed,
+ }),
+ ),
+ GFP_KERNEL,
+ )?)
+ } else {
+ None
+ }
+ },
+ usb_copy: {
+ if model.led_usb_copy {
+ Some(KBox::pin_init(
+ led::DeviceBuilder::new()
+ .color(led::Color::Green)
+ .name(c"synology:green:usb")
+ .build(
+ dev,
+ try_pin_init!(LedHandler {
+ blink <- new_mutex!(false),
+ command: Command::UsbLed,
+ }),
+ ),
+ GFP_KERNEL,
+ )?)
+ } else {
+ None
+ }
+ },
+ esata: {
+ if model.led_esata {
+ Some(KBox::pin_init(
+ led::DeviceBuilder::new()
+ .color(led::Color::Green)
+ .name(c"synology:green:esata")
+ .build(
+ dev,
+ try_pin_init!(LedHandler {
+ blink <- new_mutex!(false),
+ command: Command::EsataLed,
+ }),
+ ),
+ GFP_KERNEL,
+ )?)
+ } else {
+ None
+ }
+ },
+ }))
+ })
+ }
+}
+
+#[derive(Copy, Clone)]
+pub(crate) enum StatusLedColor {
+ Green,
+ Amber,
+}
+
+#[derive(Copy, Clone)]
+pub(crate) enum State {
+ On,
+ Blink,
+ Off,
+}
+
+#[pin_data]
+struct LedHandler {
+ #[pin]
+ blink: Mutex<bool>,
+ command: fn(State) -> Command,
+}
+
+/// Blink delay measured using video recording on DS923+ for Power and Status Led.
+///
+/// We assume it is the same for all other leds and models.
+const BLINK_DELAY: Delta = Delta::from_millis(167);
+
+#[vtable]
+impl LedOps for LedHandler {
+ type Bus = serdev::Device<Bound>;
+ type Mode = led::Normal;
+ const BLOCKING: bool = true;
+ const MAX_BRIGHTNESS: u32 = 1;
+
+ fn brightness_set<'bound>(
+ &self,
+ dev: &'bound Self::Bus,
+ _classdev: &led::Device<'bound, Self>,
+ brightness: u32,
+ ) -> Result<()> {
+ let mut blink = self.blink.lock();
+ (self.command)(if brightness == 0 {
+ *blink = false;
+ State::Off
+ } else if *blink {
+ State::Blink
+ } else {
+ State::On
+ })
+ .write(dev)?;
+
+ Ok(())
+ }
+
+ fn blink_set<'bound>(
+ &self,
+ dev: &'bound Self::Bus,
+ _classdev: &led::Device<'bound, Self>,
+ delay_on: &mut usize,
+ delay_off: &mut usize,
+ ) -> Result<()> {
+ let mut blink = self.blink.lock();
+
+ (self.command)(if *delay_on == 0 && *delay_off != 0 {
+ *blink = false;
+
+ State::Off
+ } else if *delay_on != 0 && *delay_off == 0 {
+ *blink = false;
+
+ State::On
+ } else {
+ *blink = true;
+ *delay_on = BLINK_DELAY.as_millis() as usize;
+ *delay_off = BLINK_DELAY.as_millis() as usize;
+
+ State::Blink
+ })
+ .write(dev)
+ }
+}
+
+#[pin_data]
+struct StatusLedHandler {
+ #[pin]
+ blink: Mutex<bool>,
+}
+
+#[vtable]
+impl LedOps for StatusLedHandler {
+ type Bus = serdev::Device<Bound>;
+ type Mode = led::MultiColor;
+ const BLOCKING: bool = true;
+ const MAX_BRIGHTNESS: u32 = 1;
+
+ fn brightness_set<'bound>(
+ &self,
+ dev: &'bound Self::Bus,
+ classdev: &led::MultiColorDevice<'bound, Self>,
+ brightness: u32,
+ ) -> Result<()> {
+ let mut blink = self.blink.lock();
+ if brightness == 0 {
+ *blink = false;
+ }
+
+ let amber_brightness = classdev.subleds()[1].brightness();
+
+ let (color, subled_brightness) = if amber_brightness == 0 {
+ (StatusLedColor::Green, classdev.subleds()[0].brightness())
+ } else {
+ (StatusLedColor::Amber, amber_brightness)
+ };
+
+ Command::StatusLed(
+ color,
+ if subled_brightness == 0 {
+ State::Off
+ } else if *blink {
+ State::Blink
+ } else {
+ State::On
+ },
+ )
+ .write(dev)
+ }
+
+ fn blink_set<'bound>(
+ &self,
+ dev: &'bound Self::Bus,
+ classdev: &led::MultiColorDevice<'bound, Self>,
+ delay_on: &mut usize,
+ delay_off: &mut usize,
+ ) -> Result<()> {
+ let mut blink = self.blink.lock();
+
+ let amber_intensity = classdev.subleds()[1].intensity();
+
+ let (color, subled_intensity) = if amber_intensity == 0 {
+ (StatusLedColor::Green, classdev.subleds()[0].intensity())
+ } else {
+ (StatusLedColor::Amber, amber_intensity)
+ };
+ Command::StatusLed(
+ color,
+ if *delay_on == 0 && *delay_off != 0 {
+ *blink = false;
+ State::Off
+ } else if *delay_on != 0 && *delay_off == 0 {
+ *blink = false;
+
+ if subled_intensity == 0 {
+ State::Off
+ } else {
+ State::On
+ }
+ } else {
+ *blink = true;
+ *delay_on = BLINK_DELAY.as_millis() as usize;
+ *delay_off = BLINK_DELAY.as_millis() as usize;
+
+ if subled_intensity == 0 {
+ State::Off
+ } else {
+ State::Blink
+ }
+ },
+ )
+ .write(dev)
+ }
+}
diff --git a/drivers/platform/synology_microp/model.rs b/drivers/platform/synology_microp/model.rs
new file mode 100644
index 000000000000..715d8840f56b
--- /dev/null
+++ b/drivers/platform/synology_microp/model.rs
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use kernel::led::Color;
+
+pub(crate) struct Model {
+ pub(crate) led_power: Color,
+ pub(crate) led_alert: Option<Color>,
+ pub(crate) led_usb_copy: bool,
+ pub(crate) led_esata: bool,
+}
+
+impl Model {
+ pub(super) const fn new() -> Self {
+ Self {
+ led_power: Color::Blue,
+ led_alert: None,
+ led_usb_copy: false,
+ led_esata: false,
+ }
+ }
+
+ pub(super) const fn led_power(self, color: Color) -> Self {
+ Self {
+ led_power: color,
+ ..self
+ }
+ }
+
+ pub(super) const fn led_alert(self, color: Color) -> Self {
+ Self {
+ led_alert: Some(color),
+ ..self
+ }
+ }
+
+ pub(super) const fn led_esata(self) -> Self {
+ Self {
+ led_esata: true,
+ ..self
+ }
+ }
+
+ pub(super) const fn led_usb_copy(self) -> Self {
+ Self {
+ led_usb_copy: true,
+ ..self
+ }
+ }
+}
diff --git a/drivers/platform/synology_microp/synology_microp.rs b/drivers/platform/synology_microp/synology_microp.rs
new file mode 100644
index 000000000000..f7168309e611
--- /dev/null
+++ b/drivers/platform/synology_microp/synology_microp.rs
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0
+
+//! Synology Microp driver
+
+use kernel::{
+ device,
+ led::Color,
+ of::{
+ DeviceId,
+ IdTable, //
+ },
+ of_device_table,
+ prelude::*,
+ serdev, //
+};
+use pin_init::pin_init_scope;
+
+use crate::model::Model;
+
+pub(crate) mod command;
+mod led;
+mod model;
+
+kernel::module_serdev_device_driver! {
+ type: SynologyMicropDriver<'static>,
+ name: "synology_microp",
+ authors: ["Markus Probst <markus.probst@posteo.de>"],
+ description: "Synology Microp driver",
+ license: "GPL v2",
+}
+
+#[rustfmt::skip]
+of_device_table!(
+ OF_TABLE,
+ MODULE_OF_TABLE,
+ Model,
+ [
+ // apollolake
+ (DeviceId::new(c"synology,ds918p-microp"), Model::new()),
+
+ // evansport
+ (DeviceId::new(c"synology,ds214play-microp"), Model::new()),
+
+ // geminilakenk
+ (DeviceId::new(c"synology,ds225p-microp"), Model::new().led_usb_copy()),
+
+ // pineview
+ (DeviceId::new(c"synology,ds710p-microp"), Model::new().led_esata()),
+ (DeviceId::new(c"synology,ds1010p-microp"), Model::new().led_alert(Color::Amber)),
+
+ // rtd1296
+ (DeviceId::new(c"synology,ds118-microp"), Model::new()),
+
+ // rtd1619b
+ (DeviceId::new(c"synology,ds223-microp"), Model::new().led_usb_copy()),
+
+ // v1000
+ (DeviceId::new(c"synology,ds1823xsp-microp"), Model::new()),
+ (DeviceId::new(c"synology,rs1221p-microp"), Model::new().led_power(Color::Green)),
+ ]
+);
+
+#[pin_data]
+struct SynologyMicropDriver<'bound> {
+ #[pin]
+ led: led::Data<'bound>,
+}
+
+#[vtable]
+impl serdev::Driver for SynologyMicropDriver<'_> {
+ type IdInfo = Model;
+ type Data<'bound> = SynologyMicropDriver<'bound>;
+ const OF_ID_TABLE: Option<IdTable<Self::IdInfo>> = Some(&OF_TABLE);
+
+ fn probe<'bound>(
+ dev: &'bound serdev::Device<device::Core<'_>>,
+ model: Option<&'bound Model>,
+ ) -> impl PinInit<Self::Data<'bound>, kernel::error::Error> + 'bound {
+ pin_init_scope(move || {
+ let model = model.ok_or(EINVAL)?;
+
+ dev.set_baudrate(9600).map_err(|_| EINVAL)?;
+ dev.set_flow_control(false);
+ dev.set_parity(serdev::Parity::None)?;
+
+ Ok(try_pin_init!(SynologyMicropDriver {
+ led <- led::Data::register(dev, model),
+ }))
+ })
+ }
+}
--
2.54.0
^ permalink raw reply related
* [PATCH v18 1/2] dt-bindings: embedded-controller: Add synology microp devices
From: Markus Probst @ 2026-07-24 17:10 UTC (permalink / raw)
To: Hans de Goede, Ilpo Järvinen, Bryan O'Donoghue,
Lee Jones, Pavel Machek, Miguel Ojeda, Boqun Feng, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Trevor Gross, Danilo Krummrich, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Daniel Almeida,
Tamir Duberstein, Alexandre Courbot, Onur Özkan
Cc: platform-driver-x86, linux-leds, devicetree, linux-kernel,
rust-for-linux, Markus Probst, Krzysztof Kozlowski
In-Reply-To: <20260724-synology_microp_initial-v18-0-fb2f49f10e77@posteo.de>
Add the Synology Microp devicetree bindings. Those devices are
microcontrollers found on Synology NAS devices. They are connected to a
serial port on the host device.
Those devices are used to control certain LEDs, fan speeds, a beeper, to
handle buttons, fan failures and to properly shutdown and reboot the
device.
The device has a different feature set depending on the Synology NAS
model, like having different number of fans, buttons and leds. Depending
on the architecture of the model, they also need a different system
shutdown behaviour.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Markus Probst <markus.probst@posteo.de>
---
.../synology,ds918p-microp.yaml | 100 +++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/Documentation/devicetree/bindings/embedded-controller/synology,ds918p-microp.yaml b/Documentation/devicetree/bindings/embedded-controller/synology,ds918p-microp.yaml
new file mode 100644
index 000000000000..a44101884322
--- /dev/null
+++ b/Documentation/devicetree/bindings/embedded-controller/synology,ds918p-microp.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/embedded-controller/synology,ds918p-microp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synology NAS on-board Microcontroller
+
+maintainers:
+ - Markus Probst <markus.probst@posteo.de>
+
+description: |
+ Synology Microp is a microcontroller found in Synology NAS devices.
+ It is connected to a serial port on the host device.
+
+ It is necessary to properly shutdown and reboot the NAS device and
+ provides additional functionality such as led control, fan speed control,
+ a beeper and buttons on the NAS device.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - synology,rs1221rpp-microp
+ - synology,rs822p-microp
+ - synology,rs422p-microp
+ - const: synology,rs1221p-microp
+
+ - items:
+ - const: synology,ds1825p-microp
+ - const: synology,ds1823xsp-microp
+
+ - items:
+ - enum:
+ - synology,ds725p-microp
+ - synology,ds225p-microp
+ - synology,ds723p-microp
+ - synology,ds710p-microp
+ - const: synology,ds214play-microp
+
+ - items:
+ - enum:
+ - synology,ds425p-microp
+ - synology,ds1525p-microp
+ - synology,ds925p-microp
+ - synology,ds923p-microp
+ - synology,ds1522p-microp
+ - synology,ds1010p-microp
+ - synology,ds411p-microp
+ - const: synology,ds918p-microp
+
+ - items:
+ - enum:
+ - synology,ds124-microp
+ - synology,ds223j-microp
+ - synology,ds223-microp
+ - const: synology,ds118-microp
+
+ - enum:
+ - synology,ds118-microp
+ - synology,ds1823xsp-microp
+ - synology,rs1221p-microp
+ - synology,ds918p-microp
+ - synology,ds214play-microp
+
+ fan-failure-gpios:
+ description: GPIOs needed to determine which fans stopped working on a fan failure event.
+ minItems: 2
+ maxItems: 3
+
+required:
+ - compatible
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - synology,ds918p-microp
+ - synology,rs422p-microp
+ then:
+ required:
+ - fan-failure-gpios
+ else:
+ properties:
+ fan-failure-gpios: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ embedded-controller {
+ compatible = "synology,ds923p-microp", "synology,ds918p-microp";
+
+ fan-failure-gpios = <&gpio 68 GPIO_ACTIVE_HIGH>, <&gpio 69 GPIO_ACTIVE_HIGH>;
+ };
--
2.54.0
^ permalink raw reply related
* [PATCH v18 0/2] Introduce Synology Microp driver
From: Markus Probst @ 2026-07-24 17:10 UTC (permalink / raw)
To: Hans de Goede, Ilpo Järvinen, Bryan O'Donoghue,
Lee Jones, Pavel Machek, Miguel Ojeda, Boqun Feng, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Trevor Gross, Danilo Krummrich, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Daniel Almeida,
Tamir Duberstein, Alexandre Courbot, Onur Özkan
Cc: platform-driver-x86, linux-leds, devicetree, linux-kernel,
rust-for-linux, Markus Probst, Krzysztof Kozlowski
Synology uses a microcontroller in their NAS devices connected to a
serial port to control certain LEDs, fan speeds, a beeper, to handle
proper shutdown and restart, buttons and fan failures.
This patch series depends on the rust led abstraction [1] and the rust
serdev abstraction [2]. The latter already being in driver-core.
This is only a initial version of the driver able to control LEDs.
The following rust abstractions would be required, to implement the
remaining features:
- hwmon (include/linux/hwmon.h)
- input (include/linux/input.h)
- sysoff handler (include/linux/reboot.h)
[1] https://lore.kernel.org/rust-for-linux/20260716-rust_leds-v23-0-e91f5b608b56@posteo.de/
[2] https://lore.kernel.org/rust-for-linux/20260718-rust_serdev-v16-0-5809384d2e1b@posteo.de/
Signed-off-by: Markus Probst <markus.probst@posteo.de>
---
Changes in v18:
- fix issues reported by Sashiko:
- fix hardware blink delays not reported if every subled has
intensity = 0
- fix blink aborting if every subled has intensity = 0
- Link to v17: https://patch.msgid.link/20260724-synology_microp_initial-v17-0-e2f70b4dc691@posteo.de
Changes in v17:
- adapted to rust serdev abstraction v16
- Link to v16: https://patch.msgid.link/20260629-synology_microp_initial-v16-0-601e91c49e0d@posteo.de
Changes in v16:
- fix issues reported by Sashiko:
- fix typo in dt compatible
- fix not compilable as loadable module
- Link to v15: https://patch.msgid.link/20260629-synology_microp_initial-v15-0-4b3d7367c7cf@posteo.de
Changes in v15:
- adapted to rust led abstractiopn v21
- Link to v14: https://patch.msgid.link/20260531-synology_microp_initial-v14-0-1377d425b24b@posteo.de
Changes in v14:
- adapt to led abstraction v18 and serdev abstraction v11
- Link to v13: https://patch.msgid.link/20260530-synology_microp_initial-v13-0-aa2bb9c56efc@posteo.de
Changes in v13:
- adapted to driver-lifetime v5 patch series.
- set blink = false as initial power led state, as set_blink hasn't been
called yet (even though the led is blinking at startup)
- Link to v12: https://patch.msgid.link/20260429-synology_microp_initial-v12-0-40a05033c620@posteo.de
Changes in v12:
- adapted to driver-lifetime patch series. The driver can't take
advantage of it, until class devices like led also make use of it.
- Link to v11: https://patch.msgid.link/20260427-synology_microp_initial-v11-0-9c1bd5a6f3ed@posteo.de
Changes in v11:
- rebased on top of 7.1-rc1
- add "synology" as devicename to led, like it is done in existing dts
files in the kernel
- fix color for led being orange instead of amber. I personally can't
clearly tell them apart, but apparently its amber.
- replaced MCU with EC in Kconfig help
- Link to v10: https://patch.msgid.link/20260424-synology_microp_initial-v10-0-e852d2f3eba1@posteo.de
Changes in v10:
- resolved issues reported by Sashiko Bot:
- removed unneeded include from device tree
- fix typo in of device table
- fix blink not set to false, if delay_off or delay_on is 0
- Link to v9: https://patch.msgid.link/20260423-synology_microp_initial-v9-0-4a8533f87e07@posteo.de
Changes in v9:
- separate fallback and front compatibles in dt schema
- remove front compatibles from of id table, if all functionality is
by covered by the fallback
- remove TODO file
- add platform-driver-x86@vger.kernel.org to Maintainers file entry
- use `Delta` type in `BLINK_DELAY` const
- Link to v8: https://patch.msgid.link/20260420-synology_microp_initial-v8-0-7946a9124491@posteo.de
Changes in v8:
- removed unnecessary Copy and Clone derive
- added `BLINK_DELAY` constant
- added compatible id fallbacks
- moved dt schema patch before the driver
- added ds411p
- Link to v7: https://lore.kernel.org/r/20260411-synology_microp_initial-v7-0-9a3a094e763a@posteo.de
Changes in v7:
- remove list of compatible ids from commit msg
- explain what makes the different models not compatible in the commit msg
- remove unnecessary examples
- Link to v6: https://lore.kernel.org/r/20260405-synology_microp_initial-v6-0-08fde474b6c9@posteo.de
Changes in v6:
- moved devicetree bindings patch at the end of the set
- remove several patches
- move of id table from model.rs to synology_microp.rs
- remove the model! macro
- use if blocks in devicetree schema to narrow down the
fan-failure-gpios property
- add multiple devicetree examples to test if blocks
- Link to v5: https://lore.kernel.org/r/20260329-synology_microp_initial-v5-0-27cb80bdf591@posteo.de
Changes in v5:
- add esata led support
- use different compatible for each model
- add visibility modifier to of_device_table macro
- fix match data missing when using PRP0001
- Link to v4: https://lore.kernel.org/r/20260320-synology_microp_initial-v4-0-0423ddb83ca4@posteo.de
Changes in v4:
- convert to monolithic driver and moved it into drivers/platform
- removed mfd rust abstraction
- moved dt-bindings to embedded-controller
- Link to v3: https://lore.kernel.org/r/20260313-synology_microp_initial-v3-0-ad6ac463a201@posteo.de
Changes in v3:
- remove `default n` from Kconfig entry, as n is the default already.
- select RUST_SERIAL_DEV_BUS_ABSTRACTIONS in Kconfig
- add mfd rust abstraction
- split core and led parts into their own driver. It should now be considered a
MFD device.
- split led part of dt binding into its own file
- Link to v2: https://lore.kernel.org/r/20260308-synology_microp_initial-v2-0-9389963f31c5@posteo.de
Changes in v2:
- fix missing tabs in MAINTAINERS file
- remove word binding from patch subject
- add missing signed-off-by
- add missing help entry in Kconfig
- add missing spdx license headers
- remove no-check{,-cpu}-fan properties from the dt-bindings and replace
them with the check_fan module parameter
- use patternProperties for leds in dt-bindings
- license dt-binding as GPL-2.0-only OR BSD-2-Clause
- move driver from staging tree into mfd tree and mark it as work in
progress inside Kconfig
- only register alert and usb led if fwnode is present
- Link to v1: https://lore.kernel.org/r/20260306-synology_microp_initial-v1-0-fcffede6448c@posteo.de
---
Markus Probst (2):
dt-bindings: embedded-controller: Add synology microp devices
platform: Add initial synology microp driver
.../synology,ds918p-microp.yaml | 100 +++++++
MAINTAINERS | 7 +
drivers/platform/Kconfig | 2 +
drivers/platform/Makefile | 1 +
drivers/platform/synology_microp/Kconfig | 13 +
drivers/platform/synology_microp/Makefile | 5 +
drivers/platform/synology_microp/command.rs | 54 ++++
drivers/platform/synology_microp/led.rs | 304 +++++++++++++++++++++
drivers/platform/synology_microp/model.rs | 49 ++++
.../platform/synology_microp/synology_microp.rs | 91 ++++++
10 files changed, 626 insertions(+)
---
base-commit: 6946cd5d0aa4dd10a414ddcb7a10844fdb0ad345
change-id: 20260306-synology_microp_initial-0f7dac7b7496
prerequisite-message-id: 20260530132736.3298549-1-dakr@kernel.org
prerequisite-patch-id: 310c6bee038ca3909a8e5e58ec12b74f7189b869
prerequisite-patch-id: 92812c3d42b29504838e6dc66c307ff5c035bb5e
prerequisite-change-id: 20251217-rust_serdev-ee5481e9085c:v16
prerequisite-patch-id: 758729124be172e4a5e7d3b1f23fbfc890c53142
prerequisite-patch-id: cfe1067f048223fca63fffebdaab3e5901aefc91
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^ permalink raw reply
* Re: [PATCH v2 2/4] drm: mxsfb: Add optional DPI output bus-width configuration
From: Frank Li @ 2026-07-24 17:01 UTC (permalink / raw)
To: Francesco Dolcini
Cc: Marek Vasut, Stefan Agner, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Alexander Stein,
Francesco Dolcini, dri-devel, devicetree, linux-kernel, imx,
linux-arm-kernel
In-Reply-To: <20260723155332.GB4453@francesco-nb>
On Thu, Jul 23, 2026 at 05:53:32PM +0200, Francesco Dolcini wrote:
> On Thu, Jul 23, 2026 at 10:47:36AM -0500, Frank Li wrote:
> > On Thu, Jul 23, 2026 at 11:38:09AM +0200, Francesco Dolcini wrote:
> > > From: Francesco Dolcini <francesco.dolcini@toradex.com>
> > >
> > > LCDIF programs LCD_DATABUS_WIDTH from the selected media bus format. The
> > > format reported by the downstream panel or bridge describes the display
> > > input, but it does not describe how the LCDIF data pins are physically
> > > wired on the board.
> > >
> > > These can differ. For example, a 16-bit LCDIF bus can be connected to a
> > > 24-bit display by wiring the available color bits to the corresponding
> > > display inputs. In that case, using the display's 24-bit format to
> > > configure LCDIF selects the wrong data-bus mode and changes the assignment
> > > of color bits on the LCD_DATA pins.
> > >
> > > Read the optional bus-width endpoint property from the LCDIF output port
> > > and use it to select the media bus format used to configure LCDIF. This
> > > allows the LCDIF bus mode to describe the physical interface
> > > independently of the downstream display format.
> > >
> > > When the optional property is absent, continue using the format reported
> > > by the downstream display device, preserving the existing behavior.
> > >
> > > Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
> > > ---
> > > v2: use the common bus-width property instead of the legacy interface-pix-fmt
> > > ---
> > > drivers/gpu/drm/mxsfb/mxsfb_drv.c | 24 ++++++++++++++++++++++++
> > > drivers/gpu/drm/mxsfb/mxsfb_drv.h | 2 ++
> > > drivers/gpu/drm/mxsfb/mxsfb_kms.c | 12 ++++++++++++
> > > 3 files changed, 38 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> > > index 9b8fbda85d28..0545718a4b65 100644
> > > --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> > > +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c
> > > @@ -12,7 +12,10 @@
> > > #include <linux/clk.h>
> > > #include <linux/dma-mapping.h>
> > > #include <linux/io.h>
> > > +#include <linux/media-bus-format.h>
> > > #include <linux/module.h>
> > > +#include <linux/of.h>
> > > +#include <linux/of_graph.h>
> > > #include <linux/platform_device.h>
> > > #include <linux/property.h>
> > > #include <linux/pm_runtime.h>
> > > @@ -209,7 +212,10 @@ static int mxsfb_load(struct drm_device *drm,
> > > const struct mxsfb_devdata *devdata)
> > > {
> > > struct platform_device *pdev = to_platform_device(drm->dev);
> > > + struct device_node *np = pdev->dev.of_node;
> > > struct mxsfb_drm_private *mxsfb;
> > > + struct device_node *ep;
> > > + u32 bus_width = 0;
> > > int ret;
> > >
> > > mxsfb = devm_kzalloc(&pdev->dev, sizeof(*mxsfb), GFP_KERNEL);
> > > @@ -236,6 +242,24 @@ static int mxsfb_load(struct drm_device *drm,
> > > if (IS_ERR(mxsfb->clk_disp_axi))
> > > mxsfb->clk_disp_axi = NULL;
> > >
> > > + ep = of_graph_get_next_endpoint(np, NULL);
> >
> > use auto cleanup
> >
> > struct device_node *ep __free(device_node) = of_graph_get_next_endpoint(np, NULL);
>
> Does it makes the code more read-able or better in this specific case? I
> would say no, to me it is more compact and clear the way it is.
Recently there are bunch of patch to fix miss of_put_node(). auto cleanup
help avoid manual to manage it and let us to force key part.
recently, perfer use fwnode_graph_get_next_endpoint() and other fwnode_xxx
node function.
it is also okay to keep use of_xxx() to align existing code.
Frank
>
>
^ permalink raw reply
* Re: [PATCH v3 2/2] hwmon: (pmbus/vt7505) Add driver for Analog Devices MAX16545/MAX16550 and Volterra VT7505
From: sashiko-bot @ 2026-07-24 16:59 UTC (permalink / raw)
To: Pradhan, Sanman; +Cc: conor+dt, devicetree, linux-hwmon, robh
In-Reply-To: <20260724164919.247162-3-sanman.pradhan@hpe.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The arithmetic calculation in `vt7505_set_m()` can overflow when converting the 64-bit result to a signed 32-bit integer, resulting in a negative or corrupted PMBus coefficient.
--
--- Patch [2]: [PATCH v3 2/2] hwmon: (pmbus/vt7505) Add driver for Analog Devices MAX16545/MAX16550 and Volterra VT7505 ---
commit 6d968d4ee814c7e869f893c1177921f54e4e55cd
Author: Georgi Vlaev <gvlaev@juniper.net>
hwmon: (pmbus/vt7505) Add driver for Analog Devices MAX16545/MAX16550 and Volterra VT7505
This commit adds a PMBus driver for the MAX16545, MAX16550, and VT7505
controllers. It reports voltage, current, power, and temperature over
PMBus, calculating current and power coefficients based on the
adi,rload-ohms device tree property.
> diff --git a/drivers/hwmon/pmbus/vt7505.c b/drivers/hwmon/pmbus/vt7505.c
> new file mode 100644
> index 0000000000000..c60f849e1f9ea
> --- /dev/null
> +++ b/drivers/hwmon/pmbus/vt7505.c
[ ... ]
> +static void vt7505_set_m(int *m, u32 rload)
> +{
> + u64 val = (u64)*m * rload;
> +
> + /* Make sure m fits the s32 type */
> + *m = DIV_ROUND_CLOSEST_ULL(val, 1000);
[Severity: Medium]
Does this downcast to a signed 32-bit integer safely handle large values of
rload?
If the rload value is sufficiently large, could the result of
DIV_ROUND_CLOSEST_ULL() exceed INT_MAX and silently overflow into a
negative PMBus coefficient?
> +}
> +
> +static int vt7505_probe(struct i2c_client *client)
> +{
> + struct device *dev = &client->dev;
> + const struct vt7505_chip_data *chip;
> + struct pmbus_driver_info *info;
> + u32 rload;
> + int ret;
[ ... ]
> + /*
> + * The m coefficient used in the direct-format current and power
> + * calculations depends on RLOAD, the external current-report resistor
> + * connected between the ILOAD pin and ground. Use the default value if
> + * none is specified.
> + */
> + if (of_property_read_u32(dev->of_node, "adi,rload-ohms", &rload))
> + rload = VT7505_RLOAD_DEFAULT;
> +
> + if (!rload)
> + return dev_err_probe(dev, -EINVAL,
> + "adi,rload-ohms must be non-zero\n");
[Severity: Medium]
Should there be an upper bound validation for rload here?
Because rload is read directly from the device tree and passed to
vt7505_set_m(), an unexpectedly large unbounded value could trigger the
arithmetic overflow mentioned above.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260724164919.247162-1-sanman.pradhan@hpe.com?part=2
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: hwmon: pmbus: Add Analog Devices MAX16545/MAX16550 and Volterra VT7505
From: sashiko-bot @ 2026-07-24 16:53 UTC (permalink / raw)
To: Pradhan, Sanman; +Cc: conor+dt, robh, linux-hwmon, devicetree
In-Reply-To: <20260724164919.247162-2-sanman.pradhan@hpe.com>
> From: Sanman Pradhan <psanman@juniper.net>
>
> Add device tree binding documentation for the Analog Devices MAX16545 and
> MAX16550, and the Volterra VT7505 PMBus controllers.
>
> Signed-off-by: Sanman Pradhan <psanman@juniper.net>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260724164919.247162-1-sanman.pradhan@hpe.com?part=1
^ permalink raw reply
* Re: [PATCH v2 1/6] dt-bindings: iio: dac: ad5696: add AD5673R/AD5677R support
From: Conor Dooley @ 2026-07-24 16:53 UTC (permalink / raw)
To: rodrigo.alencar
Cc: Michael Auchter, linux, linux-iio, devicetree, linux-kernel,
Michael Hennerich, Jonathan Cameron, David Lechner,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <20260724-ad5686-extend-dev-support-v2-1-cfc2b30ce988@analog.com>
[-- Attachment #1: Type: text/plain, Size: 430 bytes --]
On Fri, Jul 24, 2026 at 01:03:11PM +0100, Rodrigo Alencar via B4 Relay wrote:
> From: Rodrigo Alencar <rodrigo.alencar@analog.com>
>
> Add compatible entries for AD5673R and AD5677R. These 16-channel devices
> have different bit resolutions so no fallback compatibles are used.
>
> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v2 4/6] dt-bindings: iio: dac: ad5696: extend device support
From: Conor Dooley @ 2026-07-24 16:53 UTC (permalink / raw)
To: rodrigo.alencar
Cc: Michael Auchter, linux, linux-iio, devicetree, linux-kernel,
Michael Hennerich, Jonathan Cameron, David Lechner,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <20260724-ad5686-extend-dev-support-v2-4-cfc2b30ce988@analog.com>
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v5 3/4] hwmon: (kb9002) Add driver for Kandou KB9002 retimer
From: Guenter Roeck @ 2026-07-24 16:52 UTC (permalink / raw)
To: Andy Chung
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jonathan Corbet,
Shuah Khan, devicetree, linux-kernel, linux-hwmon, linux-doc
In-Reply-To: <20260724-kb9002-upstream-v5-3-9523c3ffe83a@amd.com>
On Fri, Jul 24, 2026 at 12:47:39PM +0800, Andy Chung wrote:
> From: Andy Chung <Andy.Chung@amd.com>
>
> The Kandou KB9002 is an 8-lane PCIe 5.0 retimer that exposes an SMBus
> target with mandatory PEC. Add a hwmon driver reporting the firmware
> aggregated maximum die temperature as temp1_input, with the firmware
> version and boot status under debugfs.
>
> Signed-off-by: Andy Chung <Andy.Chung@amd.com>
For my reference:
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Thanks,
Guenter
^ permalink raw reply
* Re: [PATCH v5 4/4] hwmon: (kb9002) Add documentation
From: Guenter Roeck @ 2026-07-24 16:51 UTC (permalink / raw)
To: Andy Chung
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Jonathan Corbet,
Shuah Khan, devicetree, linux-kernel, linux-hwmon, linux-doc
In-Reply-To: <20260724-kb9002-upstream-v5-4-9523c3ffe83a@amd.com>
On Fri, Jul 24, 2026 at 12:47:40PM +0800, Andy Chung wrote:
> From: Andy Chung <Andy.Chung@amd.com>
>
> Document the sysfs and debugfs interfaces of the Kandou KB9002 hwmon
> driver.
>
> Signed-off-by: Andy Chung <Andy.Chung@amd.com>
For my reference:
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
(waiting for DT patch review)
Thanks,
Guenter
^ permalink raw reply
* Re: [PATCH v3 3/8] dt-bindings: arm: altera: add Agilex5 SOCDK eMMC board variant
From: Conor Dooley @ 2026-07-24 16:51 UTC (permalink / raw)
To: Tanmay Kathpalia
Cc: linux-mmc, ulfh, adrian.hunter, krzk+dt, robh, conor+dt, dinguyen,
p.zabel, devicetree, linux-kernel
In-Reply-To: <20260724145009.7456-3-tanmay.kathpalia@altera.com>
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v2 2/2] hwmon: (pmbus/vt7505) Add driver for Analog Devices MAX16545/MAX16550 and Volterra VT7505
From: Pradhan, Sanman @ 2026-07-24 16:50 UTC (permalink / raw)
To: linux@roeck-us.net
Cc: krzk@kernel.org, linux-hwmon@vger.kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, corbet@lwn.net,
skhan@linuxfoundation.org, devicetree@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
Sanman Pradhan
In-Reply-To: <668b28b1-875f-4fdd-b367-b09edef95367@roeck-us.net>
From: Sanman Pradhan <psanman@juniper.net>
On Fri, Jul 24, 2026 at 06:15:35 -0700, Guenter Roeck wrote:
> On 7/24/26 02:03, Krzysztof Kozlowski wrote:
> > On Thu, Jul 23, 2026 at 04:43:59PM +0000, Pradhan, Sanman wrote:
> > > +enum chips { max16550, vt7505 };
> >
> > You must adjust to upstream kernel style and such constants/defines are
> > UPPER CASE
>
> No, you must not. Not in the hardware monitoring subsystem, where the
> chips enumeration is and always has been traditionally lower case.
Thanks for the reviews, Krzysztof and Guenter. I've tried to address
all the comments in v3.
Regarding adi,rload-ohms: after checking the datasheet more carefully,
this does not seem to be the same as the current-path sense resistor
that shunt-resistor-micro-ohms describes. These devices use integrated
lossless current sensing the ILOAD pin sources a small reporting
current proportional to the load current (typically 5 uA/A), and RLOAD
simply converts that reporting current into a voltage for telemetry
scaling. It does not carry the load current itself. I've kept the
device-specific property and tried to clarify this distinction in the
binding description.
I've also moved additionalProperties after the allOf block and added
adi,ocp-severe-filter-us to the example. The property is still
optional, when absent, the driver leaves the existing MFR_CONFIG
setting unchanged.
In the driver, I've replaced the raw enum match values with per-device
match data for MAX16545, MAX16550, and VT7505. This avoids the
zero-valued match data concern and removes the compatible-string check
from probe. The match data now carries the temperature coefficients and
a flag indicating whether the severe OCP filter is programmable.
Thank you.
Regards,
Sanman Pradhan
^ permalink raw reply
* [PATCH v3 2/2] hwmon: (pmbus/vt7505) Add driver for Analog Devices MAX16545/MAX16550 and Volterra VT7505
From: Pradhan, Sanman @ 2026-07-24 16:50 UTC (permalink / raw)
To: linux-hwmon@vger.kernel.org
Cc: linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org,
krzk@kernel.org, conor+dt@kernel.org, corbet@lwn.net,
skhan@linuxfoundation.org, devicetree@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
Sanman Pradhan, Georgi Vlaev, Dhruva Devineni, Debjit Ghosh,
Jawahar Balaji Thirumalaisamy, Avadhut Naik,
Santhanakrishnan Balraj, Brian Mak
In-Reply-To: <20260724164919.247162-1-sanman.pradhan@hpe.com>
From: Georgi Vlaev <gvlaev@juniper.net>
Add a PMBus driver for the Analog Devices MAX16545 and MAX16550, and the
Volterra VT7505 controllers. The driver reports input/output voltage,
input/output current, input power and temperature over PMBus. All values
use the direct data format. Peak input voltage, output voltage, output
current, input power and temperature readings are exposed and can be
reset.
The reported current and power depend on the external current-report
resistor connected to the ILOAD pin, which can be provided through the
"adi,rload-ohms" device tree property.
On the MAX16550 and VT7505, the severe-OCP deglitch time can optionally
be configured with the "adi,ocp-severe-filter-us" device tree property.
When omitted, the existing hardware setting is left unchanged.
Signed-off-by: Georgi Vlaev <gvlaev@juniper.net>
Co-developed-by: Dhruva Devineni <ddevineni@juniper.net>
Signed-off-by: Dhruva Devineni <ddevineni@juniper.net>
Co-developed-by: Debjit Ghosh <dghosh@juniper.net>
Signed-off-by: Debjit Ghosh <dghosh@juniper.net>
Co-developed-by: JawaharBalaji Thirumalaisamy <jawaharb@juniper.net>
Signed-off-by: JawaharBalaji Thirumalaisamy <jawaharb@juniper.net>
Co-developed-by: Avadhut Naik <avadhutn@juniper.net>
Signed-off-by: Avadhut Naik <avadhutn@juniper.net>
Co-developed-by: Santhanakrishnan Balraj <sbalraj@juniper.net>
Signed-off-by: Santhanakrishnan Balraj <sbalraj@juniper.net>
Co-developed-by: Brian Mak <makb@juniper.net>
Signed-off-by: Brian Mak <makb@juniper.net>
Signed-off-by: Sanman Pradhan <psanman@juniper.net>
---
Changes in v3:
- Use per-device match data instead of an enum (no zero-valued match
data); derive the temperature coefficients and severe-OCP filter
support from it.
- Add an explicit adi,max16545 match entry and drop the compatible-string
check in probe.
- Use designated initializers for the I2C device ID table.
- Replace the SPDX-FileCopyrightText tag with a plain copyright line.
Changes in v2:
- Map the microsecond adi,ocp-severe-filter-us value to the
MFR_CONFIG[15:14] register field.
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/vt7505.rst | 89 +++++++++++
MAINTAINERS | 8 +
drivers/hwmon/pmbus/Kconfig | 9 ++
drivers/hwmon/pmbus/Makefile | 1 +
drivers/hwmon/pmbus/vt7505.c | 284 +++++++++++++++++++++++++++++++++
6 files changed, 392 insertions(+)
create mode 100644 Documentation/hwmon/vt7505.rst
create mode 100644 drivers/hwmon/pmbus/vt7505.c
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index 956f3da0b7223..62687bb994ac1 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -281,6 +281,7 @@ Hardware Monitoring Kernel Drivers
vexpress
via686a
vt1211
+ vt7505
w83627ehf
w83627hf
w83773g
diff --git a/Documentation/hwmon/vt7505.rst b/Documentation/hwmon/vt7505.rst
new file mode 100644
index 0000000000000..e56dc0055e89f
--- /dev/null
+++ b/Documentation/hwmon/vt7505.rst
@@ -0,0 +1,89 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+Kernel driver vt7505
+====================
+
+Supported chips:
+
+ * Analog Devices MAX16545
+
+ Prefix: 'max16545'
+
+ Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/max16545b-max16545c.pdf
+
+ * Analog Devices MAX16550
+
+ Prefix: 'max16550'
+
+ Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/max16550.pdf
+
+ * Volterra VT7505
+
+ Prefix: 'vt7505'
+
+ Datasheet: Not publicly available; register-compatible with the MAX16545.
+
+Author: Georgi Vlaev <gvlaev@juniper.net>
+
+Description
+-----------
+
+This driver supports hardware monitoring for the Analog Devices MAX16545 and
+MAX16550, and the Volterra VT7505 PMBus controllers.
+
+The devices report input and output voltage, input and output current,
+input power, and temperature. All values use the PMBus direct data format.
+Peak (maximum) values for input voltage, output voltage, output current,
+input power and temperature are exposed and can be reset. Writing to any
+``*_reset_history`` attribute clears all of the device's peak values.
+
+The reported current and power values depend on the resistance of the
+external current-report resistor connected between the ILOAD pin and
+ground. This resistance can be provided via the ``adi,rload-ohms``
+device tree property; a default of 4750 ohms is used when it is absent.
+
+Sysfs entries
+-------------
+
+The limit and alarm attributes are created by the PMBus core for the limit
+registers that the device implements. See
+Documentation/hwmon/sysfs-interface.rst for the meaning of each attribute.
+
+======================= ========================================================
+in1_label "vin"
+in1_input Measured input voltage.
+in1_min Input undervoltage warning limit.
+in1_min_alarm Input undervoltage warning alarm.
+in1_lcrit Input undervoltage fault limit.
+in1_lcrit_alarm Input undervoltage fault alarm.
+in1_highest Historical maximum input voltage.
+in1_reset_history Write to reset all peak values.
+in2_label "vout1"
+in2_input Measured output voltage.
+in2_min Output undervoltage warning limit.
+in2_min_alarm Output undervoltage warning alarm.
+in2_highest Historical maximum output voltage.
+in2_reset_history Write to reset all peak values.
+curr1_label "iin"
+curr1_input Measured input current.
+curr1_alarm Input current alarm.
+curr2_label "iout1"
+curr2_input Measured output current.
+curr2_max Output overcurrent warning limit.
+curr2_max_alarm Output overcurrent warning alarm.
+curr2_highest Historical maximum output current.
+curr2_reset_history Write to reset all peak values.
+power1_label "pin"
+power1_input Measured input power.
+power1_max Input overpower warning limit.
+power1_alarm Input overpower warning alarm.
+power1_input_highest Historical maximum input power.
+power1_reset_history Write to reset all peak values.
+temp1_input Measured temperature.
+temp1_max Overtemperature warning limit.
+temp1_max_alarm Overtemperature warning alarm.
+temp1_crit Overtemperature fault limit.
+temp1_crit_alarm Overtemperature fault alarm.
+temp1_highest Historical maximum temperature.
+temp1_reset_history Write to reset all peak values.
+======================= ========================================================
diff --git a/MAINTAINERS b/MAINTAINERS
index d88c0dd4c8142..b914aafb8514c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -28958,6 +28958,14 @@ S: Maintained
F: Documentation/hwmon/vt1211.rst
F: drivers/hwmon/vt1211.c
+VT7505 HARDWARE MONITOR DRIVER
+M: Sanman Pradhan <psanman@juniper.net>
+L: linux-hwmon@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/hwmon/pmbus/adi,vt7505.yaml
+F: Documentation/hwmon/vt7505.rst
+F: drivers/hwmon/pmbus/vt7505.c
+
VT8231 HARDWARE MONITOR DRIVER
M: Roger Lucas <vt8231@hiddenengine.co.uk>
L: linux-hwmon@vger.kernel.org
diff --git a/drivers/hwmon/pmbus/Kconfig b/drivers/hwmon/pmbus/Kconfig
index ca312be58ed5c..6c97a6dc88a59 100644
--- a/drivers/hwmon/pmbus/Kconfig
+++ b/drivers/hwmon/pmbus/Kconfig
@@ -795,6 +795,15 @@ config SENSORS_UCD9200
This driver can also be built as a module. If so, the module will
be called ucd9200.
+config SENSORS_VT7505
+ tristate "Analog Devices MAX16545, MAX16550 and Volterra VT7505"
+ help
+ If you say yes here you get hardware monitoring support for Analog
+ Devices MAX16545, MAX16550 and Volterra VT7505 PMBus controllers.
+
+ This driver can also be built as a module. If so, the module will
+ be called vt7505.
+
config SENSORS_XDP710
tristate "Infineon XDP710 family"
help
diff --git a/drivers/hwmon/pmbus/Makefile b/drivers/hwmon/pmbus/Makefile
index 080d366809f32..daa4b49bc90fd 100644
--- a/drivers/hwmon/pmbus/Makefile
+++ b/drivers/hwmon/pmbus/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_SENSORS_TPS53679) += tps53679.o
obj-$(CONFIG_SENSORS_TPS546D24) += tps546d24.o
obj-$(CONFIG_SENSORS_UCD9000) += ucd9000.o
obj-$(CONFIG_SENSORS_UCD9200) += ucd9200.o
+obj-$(CONFIG_SENSORS_VT7505) += vt7505.o
obj-$(CONFIG_SENSORS_XDP710) += xdp710.o
obj-$(CONFIG_SENSORS_XDP720) += xdp720.o
obj-$(CONFIG_SENSORS_XDPE122) += xdpe12284.o
diff --git a/drivers/hwmon/pmbus/vt7505.c b/drivers/hwmon/pmbus/vt7505.c
new file mode 100644
index 0000000000000..c60f849e1f9ea
--- /dev/null
+++ b/drivers/hwmon/pmbus/vt7505.c
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Hardware monitoring driver for Analog Devices MAX16545/MAX16550 and
+ * Volterra VT7505 PMBus controllers.
+ *
+ * Copyright 2026 Hewlett Packard Enterprise Development LP
+ */
+
+#include <linux/bitfield.h>
+#include <linux/i2c.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pmbus.h>
+
+#include "pmbus.h"
+
+#define VT7505_MFR_CONFIG 0xd0
+#define VT7505_CFG_OCP_S_FILT_MASK GENMASK(15, 14)
+
+#define VT7505_MFR_PEAK_VIN 0xd1
+#define VT7505_MFR_PEAK_IOUT 0xd2
+#define VT7505_MFR_PEAK_PIN 0xd3
+#define VT7505_MFR_PEAK_TEMP 0xd4
+#define VT7505_MFR_CLEAR_PEAKS 0xd5
+#define VT7505_MFR_PEAK_VOUT 0xfd
+
+#define VT7505_RLOAD_DEFAULT 4750
+
+struct vt7505_chip_data {
+ int temp_m;
+ int temp_b;
+ bool has_ocp_filter;
+};
+
+static const struct vt7505_chip_data max16545_data = {
+ .temp_m = 205,
+ .temp_b = 6545,
+};
+
+static const struct vt7505_chip_data max16550_data = {
+ .temp_m = 199,
+ .temp_b = 7046,
+ .has_ocp_filter = true,
+};
+
+static const struct vt7505_chip_data vt7505_data = {
+ .temp_m = 205,
+ .temp_b = 6545,
+ .has_ocp_filter = true,
+};
+
+static int vt7505_read_word_data(struct i2c_client *client, int page,
+ int phase, int reg)
+{
+ switch (reg) {
+ case PMBUS_VIRT_READ_VIN_MAX:
+ return pmbus_read_word_data(client, page, phase,
+ VT7505_MFR_PEAK_VIN);
+ case PMBUS_VIRT_READ_IOUT_MAX:
+ return pmbus_read_word_data(client, page, phase,
+ VT7505_MFR_PEAK_IOUT);
+ case PMBUS_VIRT_READ_PIN_MAX:
+ return pmbus_read_word_data(client, page, phase,
+ VT7505_MFR_PEAK_PIN);
+ case PMBUS_VIRT_READ_TEMP_MAX:
+ return pmbus_read_word_data(client, page, phase,
+ VT7505_MFR_PEAK_TEMP);
+ case PMBUS_VIRT_READ_VOUT_MAX:
+ return pmbus_read_word_data(client, page, phase,
+ VT7505_MFR_PEAK_VOUT);
+ case PMBUS_VIRT_RESET_VIN_HISTORY:
+ case PMBUS_VIRT_RESET_IOUT_HISTORY:
+ case PMBUS_VIRT_RESET_PIN_HISTORY:
+ case PMBUS_VIRT_RESET_TEMP_HISTORY:
+ case PMBUS_VIRT_RESET_VOUT_HISTORY:
+ return 0;
+ default:
+ return -ENODATA;
+ }
+}
+
+static int vt7505_write_word_data(struct i2c_client *client, int page,
+ int reg, u16 word)
+{
+ switch (reg) {
+ /*
+ * A single reset command clears all peak values. CLEAR_PEAKS is a
+ * send-byte command; the device NAKs a word or byte-data write to it.
+ */
+ case PMBUS_VIRT_RESET_VIN_HISTORY:
+ case PMBUS_VIRT_RESET_IOUT_HISTORY:
+ case PMBUS_VIRT_RESET_PIN_HISTORY:
+ case PMBUS_VIRT_RESET_TEMP_HISTORY:
+ case PMBUS_VIRT_RESET_VOUT_HISTORY:
+ return pmbus_write_byte(client, page,
+ VT7505_MFR_CLEAR_PEAKS);
+ default:
+ return -ENODATA;
+ }
+}
+
+/*
+ * None of these controllers implement the standard PMBus WRITE_PROTECT
+ * (0x10) register, so tell the core not to access it.
+ */
+static struct pmbus_platform_data vt7505_pdata = {
+ .flags = PMBUS_NO_WRITE_PROTECT,
+};
+
+static int vt7505_set_ocp_filter(struct i2c_client *client)
+{
+ u32 ocp_us;
+ u8 field;
+ int ret;
+ u16 word;
+
+ if (of_property_read_u32(client->dev.of_node, "adi,ocp-severe-filter-us",
+ &ocp_us))
+ return 0;
+
+ switch (ocp_us) {
+ case 0:
+ field = 0;
+ break;
+ case 1:
+ field = 1;
+ break;
+ case 2:
+ field = 2;
+ break;
+ case 10:
+ field = 3;
+ break;
+ default:
+ return dev_err_probe(&client->dev, -EINVAL,
+ "invalid adi,ocp-severe-filter-us value %u\n",
+ ocp_us);
+ }
+
+ ret = i2c_smbus_read_word_data(client, VT7505_MFR_CONFIG);
+ if (ret < 0)
+ return dev_err_probe(&client->dev, ret,
+ "failed to read MFR_CONFIG\n");
+
+ word = ret & ~VT7505_CFG_OCP_S_FILT_MASK;
+ word |= FIELD_PREP(VT7505_CFG_OCP_S_FILT_MASK, field);
+
+ ret = i2c_smbus_write_word_data(client, VT7505_MFR_CONFIG, word);
+ if (ret < 0)
+ return dev_err_probe(&client->dev, ret,
+ "failed to write MFR_CONFIG\n");
+
+ return 0;
+}
+
+static void vt7505_set_m(int *m, u32 rload)
+{
+ u64 val = (u64)*m * rload;
+
+ /* Make sure m fits the s32 type */
+ *m = DIV_ROUND_CLOSEST_ULL(val, 1000);
+}
+
+static int vt7505_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ const struct vt7505_chip_data *chip;
+ struct pmbus_driver_info *info;
+ u32 rload;
+ int ret;
+
+ chip = i2c_get_match_data(client);
+ if (!chip)
+ return -ENODEV;
+
+ info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
+ if (!info)
+ return -ENOMEM;
+
+ dev->platform_data = &vt7505_pdata;
+
+ /*
+ * The m coefficient used in the direct-format current and power
+ * calculations depends on RLOAD, the external current-report resistor
+ * connected between the ILOAD pin and ground. Use the default value if
+ * none is specified.
+ */
+ if (of_property_read_u32(dev->of_node, "adi,rload-ohms", &rload))
+ rload = VT7505_RLOAD_DEFAULT;
+
+ if (!rload)
+ return dev_err_probe(dev, -EINVAL,
+ "adi,rload-ohms must be non-zero\n");
+
+ info->pages = 1;
+ info->read_word_data = vt7505_read_word_data;
+ info->write_word_data = vt7505_write_word_data;
+
+ info->format[PSC_VOLTAGE_IN] = direct;
+ info->format[PSC_VOLTAGE_OUT] = direct;
+ info->format[PSC_CURRENT_IN] = direct;
+ info->format[PSC_CURRENT_OUT] = direct;
+ info->format[PSC_POWER] = direct;
+ info->format[PSC_TEMPERATURE] = direct;
+
+ /*
+ * Direct data format coefficients from the device datasheet ("PMBus
+ * Equation Parameters"). The current and power m coefficients scale
+ * with RLOAD; vt7505_set_m() applies the 1/1000 factor below, giving
+ * m = 3.824 * RLOAD for current and 0.895 * RLOAD for power. The
+ * temperature coefficients are chip specific (see the chip data).
+ */
+ info->m[PSC_VOLTAGE_IN] = 7578;
+ info->R[PSC_VOLTAGE_IN] = -2;
+ info->m[PSC_VOLTAGE_OUT] = 7578;
+ info->R[PSC_VOLTAGE_OUT] = -2;
+ info->m[PSC_CURRENT_IN] = 3824;
+ info->b[PSC_CURRENT_IN] = -4300;
+ info->R[PSC_CURRENT_IN] = -3;
+ info->m[PSC_CURRENT_OUT] = 3824;
+ info->b[PSC_CURRENT_OUT] = -4300;
+ info->R[PSC_CURRENT_OUT] = -3;
+ info->m[PSC_POWER] = 895;
+ info->b[PSC_POWER] = -9100;
+ info->R[PSC_POWER] = -2;
+
+ vt7505_set_m(&info->m[PSC_CURRENT_IN], rload);
+ vt7505_set_m(&info->m[PSC_CURRENT_OUT], rload);
+ vt7505_set_m(&info->m[PSC_POWER], rload);
+
+ info->m[PSC_TEMPERATURE] = chip->temp_m;
+ info->b[PSC_TEMPERATURE] = chip->temp_b;
+ info->R[PSC_TEMPERATURE] = -2;
+
+ info->func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_STATUS_INPUT |
+ PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT |
+ PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT |
+ PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP |
+ PMBUS_HAVE_IIN | PMBUS_HAVE_PIN;
+
+ /*
+ * The severe OCP deglitch filter is programmable on the MAX16550 and
+ * the VT7505, but fixed on the MAX16545.
+ */
+ if (chip->has_ocp_filter) {
+ ret = vt7505_set_ocp_filter(client);
+ if (ret)
+ return ret;
+ }
+
+ return pmbus_do_probe(client, info);
+}
+
+static const struct i2c_device_id vt7505_id[] = {
+ { .name = "max16545", .driver_data = (kernel_ulong_t)&max16545_data },
+ { .name = "max16550", .driver_data = (kernel_ulong_t)&max16550_data },
+ { .name = "vt7505", .driver_data = (kernel_ulong_t)&vt7505_data },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, vt7505_id);
+
+static const struct of_device_id vt7505_of_match[] = {
+ { .compatible = "adi,max16545", .data = &max16545_data },
+ { .compatible = "adi,max16550", .data = &max16550_data },
+ { .compatible = "adi,vt7505", .data = &vt7505_data },
+ { }
+};
+MODULE_DEVICE_TABLE(of, vt7505_of_match);
+
+static struct i2c_driver vt7505_driver = {
+ .driver = {
+ .name = "vt7505",
+ .of_match_table = vt7505_of_match,
+ },
+ .probe = vt7505_probe,
+ .id_table = vt7505_id,
+};
+module_i2c_driver(vt7505_driver);
+
+MODULE_AUTHOR("Georgi Vlaev <gvlaev@juniper.net>");
+MODULE_DESCRIPTION("PMBus driver for Analog Devices MAX16545/MAX16550 and Volterra VT7505");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("PMBUS");
--
2.34.1
^ permalink raw reply related
* [PATCH v3 1/2] dt-bindings: hwmon: pmbus: Add Analog Devices MAX16545/MAX16550 and Volterra VT7505
From: Pradhan, Sanman @ 2026-07-24 16:49 UTC (permalink / raw)
To: linux-hwmon@vger.kernel.org
Cc: linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org,
krzk@kernel.org, conor+dt@kernel.org, corbet@lwn.net,
skhan@linuxfoundation.org, devicetree@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
Sanman Pradhan
In-Reply-To: <20260724164919.247162-1-sanman.pradhan@hpe.com>
From: Sanman Pradhan <psanman@juniper.net>
Add device tree binding documentation for the Analog Devices MAX16545 and
MAX16550, and the Volterra VT7505 PMBus controllers.
Signed-off-by: Sanman Pradhan <psanman@juniper.net>
---
Changes in v3:
- Clarify that adi,rload-ohms is the ILOAD telemetry resistor, not a
current-path shunt.
- Note that the severe-OCP filter retains the existing hardware setting
when omitted, and add it to the example.
- Move additionalProperties after the allOf block.
Changes in v2:
- Represent the severe-OCP deglitch filter in microseconds
(renamed to adi,ocp-severe-filter-us, values 0/1/2/10).
.../bindings/hwmon/pmbus/adi,vt7505.yaml | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/pmbus/adi,vt7505.yaml
diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/adi,vt7505.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/adi,vt7505.yaml
new file mode 100644
index 0000000000000..cc538de6c0675
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/pmbus/adi,vt7505.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/pmbus/adi,vt7505.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices MAX16545/MAX16550 and Volterra VT7505 PMBus controllers
+
+maintainers:
+ - Sanman Pradhan <psanman@juniper.net>
+
+description: |
+ The Analog Devices MAX16545 and MAX16550, and the Volterra VT7505, are PMBus
+ controllers that provide input/output voltage, input/output current,
+ input power and temperature monitoring over the PMBus interface.
+
+ The MAX16545 uses the same programming model as the VT7505.
+
+ Datasheets:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/max16545b-max16545c.pdf
+ https://www.analog.com/media/en/technical-documentation/data-sheets/max16550.pdf
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - adi,max16550
+ - adi,vt7505
+ - items:
+ - const: adi,max16545
+ - const: adi,vt7505
+
+ reg:
+ maxItems: 1
+
+ adi,rload-ohms:
+ description:
+ Resistance in ohms of the external telemetry load resistor connected
+ between the ILOAD current-output pin and ground. This is not a
+ current-path shunt resistor; it sets the scaling of the reported input
+ current, output current and input power.
+ minimum: 1
+ default: 4750
+
+ adi,ocp-severe-filter-us:
+ description:
+ Deglitch time, in microseconds, applied to the severe
+ overcurrent-protection comparator, programmed into the
+ MFR_CONFIG[15:14] field. The MAX16550 and VT7505 expose this field.
+ On the MAX16545 the severe overcurrent delay is fixed and these bits
+ are reserved. If omitted, the existing hardware setting is retained.
+ enum: [0, 1, 2, 10]
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ # The severe OCP deglitch filter is fixed on the MAX16545, so the property
+ # is only valid for the MAX16550 and VT7505.
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: adi,max16545
+ then:
+ properties:
+ adi,ocp-severe-filter-us: false
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ regulator@40 {
+ compatible = "adi,vt7505";
+ reg = <0x40>;
+ adi,rload-ohms = <4750>;
+ adi,ocp-severe-filter-us = <10>;
+ };
+ };
--
2.34.1
^ permalink raw reply related
* [PATCH v3 0/2] hwmon: (pmbus) Add Analog Devices MAX16545/MAX16550 and Volterra VT7505 driver
From: Pradhan, Sanman @ 2026-07-24 16:49 UTC (permalink / raw)
To: linux-hwmon@vger.kernel.org
Cc: linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org,
krzk@kernel.org, conor+dt@kernel.org, corbet@lwn.net,
skhan@linuxfoundation.org, devicetree@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
Sanman Pradhan
From: Sanman Pradhan <psanman@juniper.net>
This series adds a PMBus driver for the Analog Devices MAX16545 and
MAX16550, and the Volterra VT7505 controllers.
The driver reports input and output voltage, input and output current,
input power, and temperature over PMBus. All sensors use the direct data
format. Peak input voltage, output voltage, output current, input power
and temperature readings are exposed and can be reset.
The MAX16545 uses the same programming model as the VT7505 and is
described with a fallback compatible.
The current and power scaling depend on the external current-report
resistor on the ILOAD pin, which can be specified with the
"adi,rload-ohms" device tree property. On the MAX16550 and VT7505, the
severe overcurrent-protection deglitch time can optionally be programmed
with the "adi,ocp-severe-filter-us" property; on the MAX16545 that delay
is fixed, so the property is rejected for that part.
The driver was tested on Juniper PTX hardware.
Changes in v3:
- dt-bindings: clarify that adi,rload-ohms is the ILOAD telemetry
resistor, not a current-path shunt; note that the severe-OCP filter
retains the existing hardware setting when omitted, and add it to the
example; move additionalProperties after the allOf block.
- driver: use per-device match data instead of an enum (no zero-valued
match data), derive the temperature coefficients and severe-OCP filter
support from it, add an explicit adi,max16545 match entry, and replace
the SPDX-FileCopyrightText tag with a plain copyright line.
Changes in v2:
- dt-bindings: represent the severe-OCP deglitch filter in microseconds
(renamed to adi,ocp-severe-filter-us, values 0/1/2/10).
- driver: map the microsecond value to the MFR_CONFIG[15:14] field.
Georgi Vlaev (1):
hwmon: (pmbus/vt7505) Add driver for Analog Devices MAX16545/MAX16550
and Volterra VT7505
Sanman Pradhan (1):
dt-bindings: hwmon: pmbus: Add Analog Devices MAX16545/MAX16550 and
Volterra VT7505
.../bindings/hwmon/pmbus/adi,vt7505.yaml | 84 ++++++
Documentation/hwmon/index.rst | 1 +
Documentation/hwmon/vt7505.rst | 89 ++++++
MAINTAINERS | 8 +
drivers/hwmon/pmbus/Kconfig | 9 +
drivers/hwmon/pmbus/Makefile | 1 +
drivers/hwmon/pmbus/vt7505.c | 284 ++++++++++++++++++
7 files changed, 476 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/pmbus/adi,vt7505.yaml
create mode 100644 Documentation/hwmon/vt7505.rst
create mode 100644 drivers/hwmon/pmbus/vt7505.c
base-commit: fa8ff8bde9207509f90adacc157b208ee732adad
--
2.34.1
^ permalink raw reply
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