[PATCH] arm64: dts: qcom: sc7280: Add ports subnodes in usb/dp qmpphy node

[PATCH] arm64: dts: qcom: sc7280: Add ports subnodes in usb/dp qmpphy node

[Luca Weiss]

Add the USB3+DP Combo QMP PHY port subnodes in the SC7280 SoC DTSI to
avoid duplication in the devices DTs.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 66f1eb83cca7..4e34d00e246b 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3399,6 +3399,32 @@ usb_1_qmpphy: phy@88e8000 {
 
 			#clock-cells = <1>;
 			#phy-cells = <1>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usb_dp_qmpphy_out: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usb_dp_qmpphy_usb_ss_in: endpoint {
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					usb_dp_qmpphy_dp_in: endpoint {
+					};
+				};
+			};
 		};
 
 		usb_2: usb@8cf8800 {

---
base-commit: df964ce9ef9fea10cf131bf6bad8658fde7956f6
change-id: 20230929-sc7280-qmpphy-ports-20afd4212470

Best regards,
-- 
Luca Weiss <luca.weiss@fairphone.com>

Re: [PATCH] arm64: dts: qcom: sc7280: Add ports subnodes in usb/dp qmpphy node

[Konrad Dybcio]

On 29.09.2023 09:31, Luca Weiss wrote:
> Add the USB3+DP Combo QMP PHY port subnodes in the SC7280 SoC DTSI to
> avoid duplication in the devices DTs.
The rationale here is to make describing the connections between
certain hw blocks possible. Defining it in the soc dtsi gives us
a very cool side-effect of not having to repeat this, but it's not
the main point here

With the commit msg amended:

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

Re: [PATCH] arm64: dts: qcom: sc7280: Add ports subnodes in usb/dp qmpphy node

[Luca Weiss]

On Fri Sep 29, 2023 at 1:44 PM CEST, Konrad Dybcio wrote:
> On 29.09.2023 09:31, Luca Weiss wrote:
> > Add the USB3+DP Combo QMP PHY port subnodes in the SC7280 SoC DTSI to
> > avoid duplication in the devices DTs.
> The rationale here is to make describing the connections between
> certain hw blocks possible. Defining it in the soc dtsi gives us
> a very cool side-effect of not having to repeat this, but it's not
> the main point here

Commit message is copy-pasted from sm8550 commit with has your R-b ;)

But I'll change it for this commit since your comment makes sense.

>
> With the commit msg amended:
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Konrad