Re: [PATCH 2/2] arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc

["Luca Weiss" <luca.weiss@fairphone.com>]

Hi Taniya,

On Thu Mar 13, 2025 at 12:57 PM CET, Taniya Das wrote:
>
>
> On 3/13/2025 1:22 PM, Luca Weiss wrote:
>> Hi Taniya,
>> 
>> On Thu Mar 13, 2025 at 5:39 AM CET, Taniya Das wrote:
>>>
>>>
>>> On 3/4/2025 2:10 PM, Dmitry Baryshkov wrote:
>>>> On Tue, 4 Mar 2025 at 09:37, Vladimir Zapolskiy
>>>> <vladimir.zapolskiy@linaro.org> wrote:
>>>>>
>>>>> On 3/4/25 01:53, Dmitry Baryshkov wrote:
>>>>>> On Tue, Mar 04, 2025 at 12:55:21AM +0200, Vladimir Zapolskiy wrote:
>>>>>>> SM8550 Camera Clock Controller shall enable both MXC and MMCX power
>>>>>>> domains.
>>>>>>
>>>>>> Are those really required to access the registers of the cammcc? Or is
>>>>>> one of those (MXC?) required to setup PLLs? Also, is this applicable
>>>>>> only to sm8550 or to other similar clock controllers?
>>>>>
>>>>> Due to the described problem I experience a fatal CPU stall on SM8550-QRD,
>>>>> not on any SM8450 or SM8650 powered board for instance, however it does
>>>>> not exclude an option that the problem has to be fixed for other clock
>>>>> controllers, but it's Qualcomm to confirm any other touched platforms,
>>>>
>>>> Please work with Taniya to identify used power domains.
>>>>
>>>
>>> CAMCC requires both MMCX and MXC to be functional.
>> 
>> Could you check whether any clock controllers on SM6350/SM7225 (Bitra)
>> need multiple power domains, or in general which clock controller uses
>> which power domain.
>> 
>> That SoC has camcc, dispcc, gcc, gpucc, npucc and videocc.
>> 
>> That'd be highly appreciated since I've been hitting weird issues there
>> that could be explained by some missing power domains.
>> 
>
> Hi Luca,
>
> The targets you mentioned does not have any have multiple rail
> dependency, but could you share the weird issues with respect to clock
> controller I can take a look.

Coming back to this, I've taken a shot at camera on SM6350 (Fairphone 4)
again, but again hitting some clock issues.

For reference, I am testing with following change:
https://lore.kernel.org/linux-arm-msm/20250911011218.861322-3-vladimir.zapolskiy@linaro.org/

Trying to enable CAMCC_MCLK1_CLK - wired up to the IMX576 camera sensor
on this phone - results in following error.

[    3.140232] ------------[ cut here ]------------
[    3.141264] camcc_mclk1_clk status stuck at 'off'
[    3.141276] WARNING: CPU: 6 PID: 12 at drivers/clk/qcom/clk-branch.c:87 clk_branch_toggle+0x170/0x190

Checking the driver against downstream driver, it looks like the RCGs
should be using clk_rcg2_shared_ops because of enable_safe_config in
downstream, but changing that doesn't really improve the situation, but
it does change the error message to this:

[    2.933254] ------------[ cut here ]------------
[    2.933961] camcc_mclk1_clk_src: rcg didn't update its configuration.
[    2.933970] WARNING: CPU: 7 PID: 12 at drivers/clk/qcom/clk-rcg2.c:136 update_config+0xd4/0xe4

I've also noticed that some camcc drivers take in GCC_CAMERA_AHB_CLK as
iface clk, could something like this be missing on sm6350?

I'd appreciate any help or tips for resolving this.

Regards
Luca

>
>> Regards
>> Luca
>> 
>>>
>>>>> for instance x1e80100-camcc has it resolved right at the beginning.
>>>>>
>>>>> To my understanding here 'required-opps' shall also be generalized, so
>>>>> the done copy from x1e80100-camcc was improper, and the latter dt-binding
>>>>> should be fixed.
>>>>
>>>> Yes
>>>>
>>>
>>> required-opps is not mandatory for MXC as we ensure that MxC would never
>>> hit retention.
>>>
>>> https://lore.kernel.org/r/20240625-avoid_mxc_retention-v2-1-af9c2f549a5f@quicinc.com
>>>
>>>
>>>>
>>>>
>>