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* [PATCH AUTOSEL 6.7 01/14] arm64: tegra: Set the correct PHY mode for MGBE
@ 2024-03-11 18:36 Sasha Levin
  2024-03-11 18:36 ` [PATCH AUTOSEL 6.7 05/14] arm64: dts: qcom: sc8280xp-crd: limit pcie4 link speed Sasha Levin
  0 siblings, 1 reply; 4+ messages in thread
From: Sasha Levin @ 2024-03-11 18:36 UTC (permalink / raw)
  To: linux-kernel, stable
  Cc: Thierry Reding, Jon Hunter, Sasha Levin, robh+dt, mark.rutland,
	thierry.reding, devicetree, linux-tegra

From: Thierry Reding <treding@nvidia.com>

[ Upstream commit 4c892121d43bc2b45896ca207b54f39a8fa6b852 ]

The PHY is configured in 10GBASE-R, so make sure to reflect that in DT.

Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
index ea13c4a7027c4..81a82933e3500 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
@@ -175,7 +175,7 @@
 			status = "okay";
 
 			phy-handle = <&mgbe0_phy>;
-			phy-mode = "usxgmii";
+			phy-mode = "10gbase-r";
 
 			mdio {
 				#address-cells = <1>;
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2024-03-18  1:38 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2024-03-11 18:36 [PATCH AUTOSEL 6.7 01/14] arm64: tegra: Set the correct PHY mode for MGBE Sasha Levin
2024-03-11 18:36 ` [PATCH AUTOSEL 6.7 05/14] arm64: dts: qcom: sc8280xp-crd: limit pcie4 link speed Sasha Levin
2024-03-12  7:50   ` Johan Hovold
2024-03-18  1:38     ` Sasha Levin

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