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From: <Ryan.Wanner@microchip.com>
To: <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
	<claudiu.beznea@tuxon.dev>, <lee@kernel.org>, <sre@kernel.org>,
	<p.zabel@pengutronix.de>
Cc: <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linux-pm@vger.kernel.org>,
	<linux-rtc@vger.kernel.org>,
	Ryan Wanner <Ryan.Wanner@microchip.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [PATCH v5 07/11] dt-bindings: mfd: syscon: atmel,sama5d2-secumod: convert to yaml
Date: Mon, 14 Apr 2025 14:41:24 -0700	[thread overview]
Message-ID: <a999a719a652ec834f1176d69a3e9b207cbd63e6.1744666011.git.Ryan.Wanner@microchip.com> (raw)
In-Reply-To: <cover.1744666011.git.Ryan.Wanner@microchip.com>

From: Ryan Wanner <Ryan.Wanner@microchip.com>

Convert Microchip AT91 secumod to YAML format.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../bindings/arm/atmel,sama5d2-secumod.yaml   | 48 +++++++++++++++++++
 .../devicetree/bindings/arm/atmel-sysregs.txt | 25 ----------
 2 files changed, 48 insertions(+), 25 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml

diff --git a/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml b/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml
new file mode 100644
index 000000000000..b1f766e333d4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/atmel,sama5d2-secumod.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/atmel,sama5d2-secumod.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip AT91 Security Module (SECUMOD)
+
+maintainers:
+  - Nicolas Ferre <nicolas.ferre@microchip.com>
+
+description:
+  The Security Module also offers the PIOBU pins which can be used as GPIO pins.
+  Note that they maintain their voltage during Backup/Self-refresh.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: atmel,sama5d2-secumod
+          - const: syscon
+      - items:
+          - enum:
+              - microchip,sama7g5-secumod
+          - const: atmel,sama5d2-secumod
+          - const: syscon
+  reg:
+    maxItems: 1
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    const: 2
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    security-module@fc040000 {
+      compatible = "atmel,sama5d2-secumod", "syscon";
+      reg = <0xfc040000 0x100>;
+      gpio-controller;
+      #gpio-cells = <2>;
+    };
diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
index d3821f651e72..5ce54f9befe6 100644
--- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
@@ -46,28 +46,3 @@ Examples:
 		reg = <0xffffe800 0x200>;
 	};
 
-Security Module (SECUMOD)
-
-The Security Module macrocell provides all necessary secure functions to avoid
-voltage, temperature, frequency and mechanical attacks on the chip. It also
-embeds secure memories that can be scrambled.
-
-The Security Module also offers the PIOBU pins which can be used as GPIO pins.
-Note that they maintain their voltage during Backup/Self-refresh.
-
-required properties:
-- compatible: Should be "atmel,<chip>-secumod", "syscon".
-  <chip> can be "sama5d2".
-- reg: Should contain registers location and length
-- gpio-controller:	Marks the port as GPIO controller.
-- #gpio-cells:		There are 2. The pin number is the
-			first, the second represents additional
-			parameters such as GPIO_ACTIVE_HIGH/LOW.
-
-
-	secumod@fc040000 {
-		compatible = "atmel,sama5d2-secumod", "syscon";
-		reg = <0xfc040000 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-- 
2.43.0


  parent reply	other threads:[~2025-04-14 21:42 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-14 21:41 [PATCH v5 00/11] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
2025-04-14 21:41 ` [PATCH v5 01/11] dt-bindings: sram: Add microchip,sama7d65-sram Ryan.Wanner
2025-04-14 21:41 ` [PATCH v5 02/11] dt-bindings: power: reset: atmel,sama5d2-shdwc: Add microchip,sama7d65-shdwc Ryan.Wanner
2025-04-15  7:59   ` Krzysztof Kozlowski
2025-04-14 21:41 ` [PATCH v5 03/11] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc Ryan.Wanner
2025-04-14 21:41 ` [PATCH v5 04/11] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc Ryan.Wanner
2025-04-14 21:41 ` [PATCH v5 05/11] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Ryan.Wanner
2025-04-14 21:41 ` [PATCH v5 06/11] dt-bindings: mfd: atmel: Add microchip,sama7d65-gpbr Ryan.Wanner
2025-04-14 21:41 ` Ryan.Wanner [this message]
2025-04-14 21:41 ` [PATCH v5 08/11] dt-bindings: mfd: syscon: add microchip,sama7d65-secumod Ryan.Wanner
2025-04-14 21:41 ` [PATCH v5 09/11] ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support Ryan.Wanner
2025-04-26 13:17   ` Claudiu Beznea
2025-04-14 21:41 ` [PATCH v5 10/11] ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC Ryan.Wanner
2025-04-26 13:16   ` Claudiu Beznea
2025-04-14 21:41 ` [PATCH v5 11/11] ARM: dts: microchip: sama7d65: Add RTT timer to curiosity board Ryan.Wanner
2025-04-15 17:11 ` [PATCH v5 00/11] Enable Power Modes Support for SAMA7D65 SoC Rob Herring (Arm)
2025-04-15 17:23 ` (subset) " Lee Jones
2025-04-27 13:41 ` Claudiu Beznea
2025-04-27 23:27 ` (subset) " Sebastian Reichel
2025-05-24 22:31 ` Alexandre Belloni

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