[RFC PATCH 0/2] ARM: dts: renesas: r9a06g032: rework UARTs

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* [RFC PATCH 0/2] ARM: dts: renesas: r9a06g032: rework UARTs
@ 2025-04-14 11:12 Wolfram Sang
  2025-04-14 11:12 ` [RFC PATCH 1/2] ARM: dts: renesas: r9a06g032: rename uart port labels Wolfram Sang
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Wolfram Sang @ 2025-04-14 11:12 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: Wolfram Sang, Conor Dooley, devicetree, Geert Uytterhoeven,
	Krzysztof Kozlowski, Magnus Damm, Rob Herring

The intention of this series is to enable the UART attached to the
9-pin-SubD connector on the extentsion board (patch 2). I got confused
while doing this, because currently the uarts are counted from 0 in the
SoC DTSI while they start from 1 in the documentation and the
schematics. Thus, patch 1 renames the labels accordingly. However, the
series is still RFC because I am calling for opinions if we maybe also
want to fix the pinmux defines like this one 'RZN1_FUNC_UART2? to the
official numbering?

Looking forward to comments...

Based on renesas-dts-for-v6.16 as of today + my GMAC1 patch sent a few
minutes ago.

Wolfram Sang (2):
  ARM: dts: renesas: r9a06g032: rename uart port labels
  ARM: dts: renesas: r9a06g032-rzn1d400-eb: describe 9-pin SubD-serial
    port

 .../boot/dts/renesas/r9a06g032-rzn1d400-db.dts   |  4 ++--
 .../boot/dts/renesas/r9a06g032-rzn1d400-eb.dts   | 15 +++++++++++++++
 arch/arm/boot/dts/renesas/r9a06g032.dtsi         | 16 ++++++++--------
 3 files changed, 25 insertions(+), 10 deletions(-)

-- 
2.47.2

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [RFC PATCH 1/2] ARM: dts: renesas: r9a06g032: rename uart port labels
  2025-04-14 11:12 [RFC PATCH 0/2] ARM: dts: renesas: r9a06g032: rework UARTs Wolfram Sang
@ 2025-04-14 11:12 ` Wolfram Sang
  2025-04-14 11:12 ` [RFC PATCH 2/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: describe 9-pin SubD-serial port Wolfram Sang
  2025-04-23 12:03 ` [RFC PATCH 0/2] ARM: dts: renesas: r9a06g032: rework UARTs Geert Uytterhoeven
  2 siblings, 0 replies; 5+ messages in thread
From: Wolfram Sang @ 2025-04-14 11:12 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: Wolfram Sang, Geert Uytterhoeven, Magnus Damm, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, devicetree

In the documentation and schematics, UARTs are counted from '1' not '0'.
Rename the labels accordingly, otherwise it is too easy to get confused
with eight UARTs available.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 .../boot/dts/renesas/r9a06g032-rzn1d400-db.dts   |  4 ++--
 arch/arm/boot/dts/renesas/r9a06g032.dtsi         | 16 ++++++++--------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
index 322e4c95ad3d..fef40e288679 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
+++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
@@ -24,7 +24,7 @@ chosen {
 	};
 
 	aliases {
-		serial0 = &uart0;
+		serial0 = &uart1;
 	};
 
 	keyboard {
@@ -278,7 +278,7 @@ &switch_port4 {
 	status = "okay";
 };
 
-&uart0 {
+&uart1 {
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index 80ad1fdc77a0..b71c5483545a 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -170,7 +170,7 @@ usb@2,0 {
 			};
 		};
 
-		uart0: serial@40060000 {
+		uart1: serial@40060000 {
 			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
 			reg = <0x40060000 0x400>;
 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -181,7 +181,7 @@ uart0: serial@40060000 {
 			status = "disabled";
 		};
 
-		uart1: serial@40061000 {
+		uart2: serial@40061000 {
 			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
 			reg = <0x40061000 0x400>;
 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -192,7 +192,7 @@ uart1: serial@40061000 {
 			status = "disabled";
 		};
 
-		uart2: serial@40062000 {
+		uart3: serial@40062000 {
 			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
 			reg = <0x40062000 0x400>;
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -203,7 +203,7 @@ uart2: serial@40062000 {
 			status = "disabled";
 		};
 
-		uart3: serial@50000000 {
+		uart4: serial@50000000 {
 			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 			reg = <0x50000000 0x400>;
 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
@@ -216,7 +216,7 @@ uart3: serial@50000000 {
 			status = "disabled";
 		};
 
-		uart4: serial@50001000 {
+		uart5: serial@50001000 {
 			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 			reg = <0x50001000 0x400>;
 			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
@@ -229,7 +229,7 @@ uart4: serial@50001000 {
 			status = "disabled";
 		};
 
-		uart5: serial@50002000 {
+		uart6: serial@50002000 {
 			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 			reg = <0x50002000 0x400>;
 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
@@ -242,7 +242,7 @@ uart5: serial@50002000 {
 			status = "disabled";
 		};
 
-		uart6: serial@50003000 {
+		uart7: serial@50003000 {
 			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 			reg = <0x50003000 0x400>;
 			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
@@ -255,7 +255,7 @@ uart6: serial@50003000 {
 			status = "disabled";
 		};
 
-		uart7: serial@50004000 {
+		uart8: serial@50004000 {
 			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
 			reg = <0x50004000 0x400>;
 			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.47.2


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [RFC PATCH 2/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: describe 9-pin SubD-serial port
  2025-04-14 11:12 [RFC PATCH 0/2] ARM: dts: renesas: r9a06g032: rework UARTs Wolfram Sang
  2025-04-14 11:12 ` [RFC PATCH 1/2] ARM: dts: renesas: r9a06g032: rename uart port labels Wolfram Sang
@ 2025-04-14 11:12 ` Wolfram Sang
  2025-04-23 12:03 ` [RFC PATCH 0/2] ARM: dts: renesas: r9a06g032: rework UARTs Geert Uytterhoeven
  2 siblings, 0 replies; 5+ messages in thread
From: Wolfram Sang @ 2025-04-14 11:12 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: Wolfram Sang, Geert Uytterhoeven, Magnus Damm, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, devicetree

A simple CTS/RTS capable UART on a good old SubD connector.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 .../boot/dts/renesas/r9a06g032-rzn1d400-eb.dts    | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
index 975446b2ac97..e103a18ccc24 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
+++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
@@ -145,6 +145,14 @@ pins_sdio1_clk: pins-sdio1-clk {
 		pinmux = <RZN1_PINMUX(96, RZN1_FUNC_SDIO)>;
 		drive-strength = <12>;
 	};
+
+	pins_uart3: pins_uart3 {
+		pinmux = <RZN1_PINMUX(105, RZN1_FUNC_UART2)>,
+			 <RZN1_PINMUX(106, RZN1_FUNC_UART2)>,
+			 <RZN1_PINMUX(107, RZN1_FUNC_UART2)>,
+			 <RZN1_PINMUX(108, RZN1_FUNC_UART2)>;
+		bias-disable;
+	};
 };
 
 &sdio1 {
@@ -221,3 +229,10 @@ &switch_port3 {
 	phy-handle = <&switch0phy1>;
 	status = "okay";
 };
+
+&uart3 {
+	pinctrl-0 = <&pins_uart3>;
+	pinctrl-names = "default";
+	status = "okay";
+	uart-has-rtscts;
+};
-- 
2.47.2


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [RFC PATCH 0/2] ARM: dts: renesas: r9a06g032: rework UARTs
  2025-04-14 11:12 [RFC PATCH 0/2] ARM: dts: renesas: r9a06g032: rework UARTs Wolfram Sang
  2025-04-14 11:12 ` [RFC PATCH 1/2] ARM: dts: renesas: r9a06g032: rename uart port labels Wolfram Sang
  2025-04-14 11:12 ` [RFC PATCH 2/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: describe 9-pin SubD-serial port Wolfram Sang
@ 2025-04-23 12:03 ` Geert Uytterhoeven
  2025-04-23 13:17   ` Wolfram Sang
  2 siblings, 1 reply; 5+ messages in thread
From: Geert Uytterhoeven @ 2025-04-23 12:03 UTC (permalink / raw)
  To: Wolfram Sang
  Cc: linux-renesas-soc, Conor Dooley, devicetree, Krzysztof Kozlowski,
	Magnus Damm, Rob Herring, Fabrizio Castro

Hi Wolfram,

CC Fabrizio

On Mon, 14 Apr 2025 at 13:12, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> The intention of this series is to enable the UART attached to the
> 9-pin-SubD connector on the extentsion board (patch 2). I got confused
> while doing this, because currently the uarts are counted from 0 in the
> SoC DTSI while they start from 1 in the documentation and the
> schematics. Thus, patch 1 renames the labels accordingly. However, the
> series is still RFC because I am calling for opinions if we maybe also
> want to fix the pinmux defines like this one 'RZN1_FUNC_UART2? to the
> official numbering?

The pinmux definitions in include/dt-bindings/pinctrl/rzn1-pinctrl.h are
ABI, so we cannot change them.

If we only renumber the UARTs in the DT, we end up with a mix,
which is even more confusing:

    pins_uart3: pins_uart3 {
            pinmux = <RZN1_PINMUX(105, RZN1_FUNC_UART2)>,
                     <RZN1_PINMUX(106, RZN1_FUNC_UART2)>,
                     <RZN1_PINMUX(107, RZN1_FUNC_UART2)>,
                     <RZN1_PINMUX(108, RZN1_FUNC_UART2)>;
            bias-disable;
    };

So I am in favour of not renumbering the UARTs.

BTW, the RZ/N1 CD contains a webapp (Toosl/PinMux/index.html)
to generate pinmux DTS, but it uses (a) different properties and
macros than upstream, and (b) the numbering from the documentation
(i.e. UART1-8), so people cannot use it with upstream anyway.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [RFC PATCH 0/2] ARM: dts: renesas: r9a06g032: rework UARTs
  2025-04-23 12:03 ` [RFC PATCH 0/2] ARM: dts: renesas: r9a06g032: rework UARTs Geert Uytterhoeven
@ 2025-04-23 13:17   ` Wolfram Sang
  0 siblings, 0 replies; 5+ messages in thread
From: Wolfram Sang @ 2025-04-23 13:17 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: linux-renesas-soc, Conor Dooley, devicetree, Krzysztof Kozlowski,
	Magnus Damm, Rob Herring, Fabrizio Castro

[-- Attachment #1: Type: text/plain, Size: 126 bytes --]


> So I am in favour of not renumbering the UARTs.

Fine with me, I'll resend the latter patch adding the new port as uart2.


[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 5+ messages in thread

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2025-04-14 11:12 [RFC PATCH 0/2] ARM: dts: renesas: r9a06g032: rework UARTs Wolfram Sang
2025-04-14 11:12 ` [RFC PATCH 1/2] ARM: dts: renesas: r9a06g032: rename uart port labels Wolfram Sang
2025-04-14 11:12 ` [RFC PATCH 2/2] ARM: dts: renesas: r9a06g032-rzn1d400-eb: describe 9-pin SubD-serial port Wolfram Sang
2025-04-23 12:03 ` [RFC PATCH 0/2] ARM: dts: renesas: r9a06g032: rework UARTs Geert Uytterhoeven
2025-04-23 13:17   ` Wolfram Sang

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