From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>,
Sascha Bischoff <sascha.bischoff@arm.com>,
Timothy Hayes <timothy.hayes@arm.com>,
"Liam R. Howlett" <Liam.Howlett@oracle.com>,
Mark Rutland <mark.rutland@arm.com>,
Jiri Slaby <jirislaby@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v4 18/26] arm64: smp: Support non-SGIs for IPIs
Date: Wed, 14 May 2025 12:39:28 +0200 [thread overview]
Message-ID: <aCRy4K/jvLr95GOp@lpieralisi> (raw)
In-Reply-To: <20250513-gicv5-host-v4-18-b36e9b15a6c3@kernel.org>
On Tue, May 13, 2025 at 07:48:11PM +0200, Lorenzo Pieralisi wrote:
[...]
> /*
> * Called from the secondary holding pen, this is the secondary CPU entry point.
> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
> index 3b3f6b56e733039cad7ff5b8995db16a68f3c762..3f3712e47c94c62836fb89cd4bfb3595fbb41557 100644
> --- a/arch/arm64/kernel/smp.c
> +++ b/arch/arm64/kernel/smp.c
> @@ -83,7 +83,26 @@ enum ipi_msg_type {
>
> static int ipi_irq_base __ro_after_init;
> static int nr_ipi __ro_after_init = NR_IPI;
> -static struct irq_desc *ipi_desc[MAX_IPI] __ro_after_init;
> +
> +struct ipi_descs {
> + struct irq_desc *descs[MAX_IPI];
> +};
> +
> +static DEFINE_PER_CPU(struct ipi_descs, pcpu_ipi_desc);
> +
> +#define get_ipi_desc(__cpu, __ipi) (per_cpu_ptr(&pcpu_ipi_desc, __cpu)->descs[__ipi])
> +
> +static bool percpu_ipi_descs __ro_after_init;
> +
> +static int ipi_to_irq(int ipi, int cpu)
> +{
> + return ipi_irq_base + (cpu * nr_ipi) + ipi;
> +}
> +
> +static int irq_to_ipi(int irq)
> +{
> + return (irq - ipi_irq_base) % nr_ipi;
> +}
>
> static bool crash_stop;
>
> @@ -844,7 +863,7 @@ int arch_show_interrupts(struct seq_file *p, int prec)
> seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
> prec >= 4 ? " " : "");
> for_each_online_cpu(cpu)
> - seq_printf(p, "%10u ", irq_desc_kstat_cpu(ipi_desc[i], cpu));
> + seq_printf(p, "%10u ", irq_desc_kstat_cpu(get_ipi_desc(cpu, i), cpu));
> seq_printf(p, " %s\n", ipi_types[i]);
> }
>
> @@ -919,7 +938,13 @@ static void __noreturn ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs
>
> static void arm64_backtrace_ipi(cpumask_t *mask)
> {
> - __ipi_send_mask(ipi_desc[IPI_CPU_BACKTRACE], mask);
> + unsigned int cpu;
> +
> + if (!percpu_ipi_descs)
> + __ipi_send_mask(get_ipi_desc(0, IPI_CPU_BACKTRACE), mask);
> + else
> + for_each_cpu(cpu, mask)
> + __ipi_send_single(get_ipi_desc(cpu, IPI_CPU_BACKTRACE), cpu);
> }
>
> void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu)
> @@ -944,7 +969,7 @@ void kgdb_roundup_cpus(void)
> if (cpu == this_cpu)
> continue;
>
> - __ipi_send_single(ipi_desc[IPI_KGDB_ROUNDUP], cpu);
> + __ipi_send_single(get_ipi_desc(cpu, IPI_KGDB_ROUNDUP), cpu);
> }
> }
> #endif
> @@ -1013,14 +1038,21 @@ static void do_handle_IPI(int ipinr)
>
> static irqreturn_t ipi_handler(int irq, void *data)
> {
> - do_handle_IPI(irq - ipi_irq_base);
> + do_handle_IPI(irq_to_ipi(irq));
> return IRQ_HANDLED;
> }
>
> static void smp_cross_call(const struct cpumask *target, unsigned int ipinr)
> {
> + unsigned int cpu;
> +
> trace_ipi_raise(target, ipi_types[ipinr]);
> - __ipi_send_mask(ipi_desc[ipinr], target);
> +
> + if (!percpu_ipi_descs)
> + __ipi_send_mask(get_ipi_desc(0, ipinr), target);
> + else
> + for_each_cpu(cpu, target)
> + __ipi_send_single(get_ipi_desc(cpu, ipinr), cpu);
> }
>
> static bool ipi_should_be_nmi(enum ipi_msg_type ipi)
> @@ -1046,11 +1078,15 @@ static void ipi_setup(int cpu)
> return;
>
> for (i = 0; i < nr_ipi; i++) {
> - if (ipi_should_be_nmi(i)) {
> - prepare_percpu_nmi(ipi_irq_base + i);
> - enable_percpu_nmi(ipi_irq_base + i, 0);
> + if (!percpu_ipi_descs) {
> + if (ipi_should_be_nmi(i)) {
> + prepare_percpu_nmi(ipi_irq_base + i);
> + enable_percpu_nmi(ipi_irq_base + i, 0);
> + } else {
> + enable_percpu_irq(ipi_irq_base + i, 0);
> + }
> } else {
> - enable_percpu_irq(ipi_irq_base + i, 0);
> + enable_irq(irq_desc_get_irq(get_ipi_desc(cpu, i)));
> }
> }
> }
> @@ -1064,44 +1100,79 @@ static void ipi_teardown(int cpu)
> return;
>
> for (i = 0; i < nr_ipi; i++) {
> - if (ipi_should_be_nmi(i)) {
> - disable_percpu_nmi(ipi_irq_base + i);
> - teardown_percpu_nmi(ipi_irq_base + i);
> + if (!percpu_ipi_descs) {
> + if (ipi_should_be_nmi(i)) {
> + disable_percpu_nmi(ipi_irq_base + i);
> + teardown_percpu_nmi(ipi_irq_base + i);
> + } else {
> + disable_percpu_irq(ipi_irq_base + i);
> + }
> } else {
> - disable_percpu_irq(ipi_irq_base + i);
> + disable_irq(irq_desc_get_irq(get_ipi_desc(cpu, i)));
> }
> }
> }
> #endif
>
> -void __init set_smp_ipi_range(int ipi_base, int n)
> +static void ipi_setup_ppi(int ipi)
> +{
> + int err, irq, cpu;
> +
> + irq = ipi_irq_base + ipi;
> +
> + if (ipi_should_be_nmi(irq)) {
> + err = request_percpu_nmi(irq, ipi_handler, "IPI", &irq_stat);
> + WARN(err, "Could not request IRQ %d as NMI, err=%d\n", irq, err);
> + } else {
> + err = request_percpu_irq(irq, ipi_handler, "IPI", &irq_stat);
> + WARN(err, "Could not request IRQ %d as IRQ, err=%d\n", irq, err);
> + }
> +
> + for_each_possible_cpu(cpu)
> + get_ipi_desc(cpu, ipi) = irq_to_desc(irq);
> +
> + irq_set_status_flags(irq, IRQ_HIDDEN);
> +}
> +
> +static void ipi_setup_lpi(int ipi, int ncpus)
> +{
> + for (int cpu = 0; cpu < ncpus; cpu++) {
> + int err, irq;
> +
> + irq = ipi_to_irq(ipi, cpu);
> +
> + err = irq_force_affinity(irq, cpumask_of(cpu));
> +
> + WARN(err, "Could not force affinity IRQ %d, err=%d\n", irq, err);
> +
> + err = request_irq(irq, ipi_handler, IRQF_NO_AUTOEN, "IPI",
> + &irq_stat);
Heads-up, kbuild bot (sparse) barfed (correctly) at this, because the
&irq_stat pointer does not match the request_irq() void *dev_id parameter
signature (it is void __percpu *).
Of course, the &irq_stat parameter is unused so this is harmless.
I would just pass NULL (because AFAICS irq_stat in the action handler is
unused), the question is why are we passing &irq_stat in
request_percpu_irq() if that's unused in ipi_handler() ?
Was it used before and we removed its usage ? Should we clean it up
for completeness ?
Thanks,
Lorenzo
> +
> + WARN(err, "Could not request IRQ %d, err=%d\n", irq, err);
> +
> + irq_set_status_flags(irq, (IRQ_HIDDEN | IRQ_NO_BALANCING_MASK));
> +
> + get_ipi_desc(cpu, ipi) = irq_to_desc(irq);
> + }
> +}
> +
> +void __init set_smp_ipi_range_percpu(int ipi_base, int n, int ncpus)
> {
> int i;
>
> WARN_ON(n < MAX_IPI);
> nr_ipi = min(n, MAX_IPI);
>
> - for (i = 0; i < nr_ipi; i++) {
> - int err;
> -
> - if (ipi_should_be_nmi(i)) {
> - err = request_percpu_nmi(ipi_base + i, ipi_handler,
> - "IPI", &irq_stat);
> - WARN(err, "Could not request IPI %d as NMI, err=%d\n",
> - i, err);
> - } else {
> - err = request_percpu_irq(ipi_base + i, ipi_handler,
> - "IPI", &irq_stat);
> - WARN(err, "Could not request IPI %d as IRQ, err=%d\n",
> - i, err);
> - }
> -
> - ipi_desc[i] = irq_to_desc(ipi_base + i);
> - irq_set_status_flags(ipi_base + i, IRQ_HIDDEN);
> - }
> -
> + percpu_ipi_descs = !!ncpus;
> ipi_irq_base = ipi_base;
>
> + for (i = 0; i < nr_ipi; i++) {
> + if (!percpu_ipi_descs)
> + ipi_setup_ppi(i);
> + else
> + ipi_setup_lpi(i, ncpus);
> + }
> +
> /* Setup the boot CPU immediately */
> ipi_setup(smp_processor_id());
> }
>
> --
> 2.48.0
>
next prev parent reply other threads:[~2025-05-14 10:39 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-13 17:47 [PATCH v4 00/26] Arm GICv5: Host driver implementation Lorenzo Pieralisi
2025-05-13 17:47 ` [PATCH v4 01/26] dt-bindings: interrupt-controller: Add Arm GICv5 Lorenzo Pieralisi
2025-05-20 20:43 ` Rob Herring (Arm)
2025-05-29 12:44 ` Lorenzo Pieralisi
2025-05-29 13:17 ` Peter Maydell
2025-05-29 14:21 ` Lorenzo Pieralisi
2025-05-29 14:30 ` Peter Maydell
2025-05-30 9:17 ` Lorenzo Pieralisi
2025-05-30 9:51 ` Peter Maydell
2025-06-03 7:48 ` Lorenzo Pieralisi
2025-06-03 8:49 ` Peter Maydell
2025-06-03 15:15 ` Rob Herring
2025-06-03 15:36 ` Peter Maydell
2025-06-03 19:11 ` Rob Herring
2025-06-04 7:24 ` Lorenzo Pieralisi
2025-06-04 15:56 ` Marc Zyngier
2025-06-04 16:35 ` Lorenzo Pieralisi
2025-06-04 20:09 ` Peter Maydell
2025-06-05 8:06 ` Lorenzo Pieralisi
2025-06-03 15:53 ` Lorenzo Pieralisi
2025-06-03 16:04 ` Peter Maydell
2025-06-03 16:54 ` Lorenzo Pieralisi
2025-05-13 17:47 ` [PATCH v4 02/26] arm64/sysreg: Add GCIE field to ID_AA64PFR2_EL1 Lorenzo Pieralisi
2025-05-13 17:47 ` [PATCH v4 03/26] arm64/sysreg: Add ICC_PPI_PRIORITY<n>_EL1 Lorenzo Pieralisi
2025-05-13 17:47 ` [PATCH v4 04/26] arm64/sysreg: Add ICC_ICSR_EL1 Lorenzo Pieralisi
2025-05-13 17:47 ` [PATCH v4 05/26] arm64/sysreg: Add ICC_PPI_HMR<n>_EL1 Lorenzo Pieralisi
2025-05-13 17:47 ` [PATCH v4 06/26] arm64/sysreg: Add ICC_PPI_ENABLER<n>_EL1 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 07/26] arm64/sysreg: Add ICC_PPI_{C/S}ACTIVER<n>_EL1 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 08/26] arm64/sysreg: Add ICC_PPI_{C/S}PENDR<n>_EL1 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 09/26] arm64/sysreg: Add ICC_CR0_EL1 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 10/26] arm64/sysreg: Add ICC_PCR_EL1 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 11/26] arm64/sysreg: Add ICC_IDR0_EL1 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 12/26] arm64/sysreg: Add ICH_HFGRTR_EL2 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 13/26] arm64/sysreg: Add ICH_HFGWTR_EL2 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 14/26] arm64/sysreg: Add ICH_HFGITR_EL2 Lorenzo Pieralisi
2025-05-28 11:28 ` Jonathan Cameron
2025-05-28 14:30 ` Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 15/26] arm64: Disable GICv5 read/write/instruction traps Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 16/26] arm64: cpucaps: Rename GICv3 CPU interface capability Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 17/26] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 18/26] arm64: smp: Support non-SGIs for IPIs Lorenzo Pieralisi
2025-05-14 10:39 ` Lorenzo Pieralisi [this message]
2025-05-14 16:05 ` Lorenzo Pieralisi
2025-05-28 12:17 ` Jonathan Cameron
2025-05-28 14:28 ` Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 19/26] arm64: Add support for GICv5 GSB barriers Lorenzo Pieralisi
2025-05-28 13:17 ` Jonathan Cameron
2025-05-28 14:34 ` Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 20/26] irqchip/gic-v5: Add GICv5 PPI support Lorenzo Pieralisi
2025-05-28 14:15 ` Jonathan Cameron
2025-05-29 7:57 ` Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 21/26] irqchip/gic-v5: Add GICv5 IRS/SPI support Lorenzo Pieralisi
2025-05-28 16:03 ` Jonathan Cameron
2025-05-29 8:38 ` Lorenzo Pieralisi
2025-05-29 8:45 ` Alireza Sanaee
2025-05-29 9:32 ` Lorenzo Pieralisi
2025-05-29 11:17 ` Alireza Sanaee
2025-05-13 17:48 ` [PATCH v4 22/26] irqchip/gic-v5: Add GICv5 LPI/IPI support Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 23/26] irqchip/gic-v5: Enable GICv5 SMP booting Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 24/26] irqchip/gic-v5: Add GICv5 ITS support Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 25/26] irqchip/gic-v5: Add GICv5 IWB support Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 26/26] arm64: Kconfig: Enable GICv5 Lorenzo Pieralisi
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