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From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Peter Maydell <peter.maydell@linaro.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Conor Dooley <conor+dt@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	andre.przywara@arm.com, Arnd Bergmann <arnd@arndb.de>,
	Sascha Bischoff <sascha.bischoff@arm.com>,
	Timothy Hayes <timothy.hayes@arm.com>,
	"Liam R. Howlett" <Liam.Howlett@oracle.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Jiri Slaby <jirislaby@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	suzuki.poulose@arm.com
Subject: Re: [PATCH v4 01/26] dt-bindings: interrupt-controller: Add Arm GICv5
Date: Thu, 5 Jun 2025 10:06:19 +0200	[thread overview]
Message-ID: <aEFP+wsYCmMgIyhs@lpieralisi> (raw)
In-Reply-To: <CAFEAcA9xBJiRQ+UMvyOSOqOwMPYrjja0Vhk8j4_0V7f7_0ETtg@mail.gmail.com>

On Wed, Jun 04, 2025 at 09:09:27PM +0100, Peter Maydell wrote:

[...]

> > When I said "a separate problem", I meant that, extending secure- tag
> > (that applies to the "status" property only) to cover other PASes is
> > independent from the GICv5 binding *if* we define, for a single DT an eg
> > IRS device per-PAS (with realm-status, root-status, describing what the
> > reg property represents. Is that what secure-status does today ? Does
> > it say "this device MMIO space is secure-only" ?).
> >
> > It does not look like there is much appetite for tagging the reg
> > property either and making it GICv5 specific is a shortcut IMO.
> 
> I think something GICv5 specific is not unreasonable.

We need to define up to 4 interrupt domains (so max 4 frames per
component per frame type: EL3, Secure, Realm, Non-Secure).

Options:

1) Using reg and reg-names, I don't know if reg-names allows us to
   describe all possible resource names and the order does not matter,
   please let me know. Keep in mind that some resources are optional.

   Something like, for an IRS:

   reg-names = "el3-config", "secure-config", "realm-config",
   "non-secure-config", "el3-setlpi", "secure-setlpi", "realm-setlpi",
   "non-secure-setlpi";

   With that, I would remove the description in the reg property and
   just say minItems: 1

   This implicitly means that describing in DT a resource that the
   CPU possibly is not able to reach depending on
   security-state/exception level is OK. AFAICS reg-names achieves
   the same purpose of tagging below, at the end of the day it is
   a means to say eg "if you are non-secure stay away from something
   that does not belong to you".

2) We add a tagged "reg" property for GICv5 ("reg" refers to non-secure):

   reg
   el3-reg
   secure-reg
   realm-reg

3) We add a GICv5 tagged "status" property and define an eg IRS device per
   interrupt-domain ("status" refers to non-secure):

   status
   el3-status
   secure-status
   realm-status

4) Anything else that I have not thought of

What's the best option ? Please let me know, I'd like to repost the
series at v6.16-rc1 with a solution.

Thanks,
Lorenzo

  reply	other threads:[~2025-06-05  8:06 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-13 17:47 [PATCH v4 00/26] Arm GICv5: Host driver implementation Lorenzo Pieralisi
2025-05-13 17:47 ` [PATCH v4 01/26] dt-bindings: interrupt-controller: Add Arm GICv5 Lorenzo Pieralisi
2025-05-20 20:43   ` Rob Herring (Arm)
2025-05-29 12:44   ` Lorenzo Pieralisi
2025-05-29 13:17     ` Peter Maydell
2025-05-29 14:21       ` Lorenzo Pieralisi
2025-05-29 14:30         ` Peter Maydell
2025-05-30  9:17           ` Lorenzo Pieralisi
2025-05-30  9:51             ` Peter Maydell
2025-06-03  7:48       ` Lorenzo Pieralisi
2025-06-03  8:49         ` Peter Maydell
2025-06-03 15:15         ` Rob Herring
2025-06-03 15:36           ` Peter Maydell
2025-06-03 19:11             ` Rob Herring
2025-06-04  7:24               ` Lorenzo Pieralisi
2025-06-04 15:56                 ` Marc Zyngier
2025-06-04 16:35                   ` Lorenzo Pieralisi
2025-06-04 20:09                     ` Peter Maydell
2025-06-05  8:06                       ` Lorenzo Pieralisi [this message]
2025-06-03 15:53           ` Lorenzo Pieralisi
2025-06-03 16:04             ` Peter Maydell
2025-06-03 16:54               ` Lorenzo Pieralisi
2025-05-13 17:47 ` [PATCH v4 02/26] arm64/sysreg: Add GCIE field to ID_AA64PFR2_EL1 Lorenzo Pieralisi
2025-05-13 17:47 ` [PATCH v4 03/26] arm64/sysreg: Add ICC_PPI_PRIORITY<n>_EL1 Lorenzo Pieralisi
2025-05-13 17:47 ` [PATCH v4 04/26] arm64/sysreg: Add ICC_ICSR_EL1 Lorenzo Pieralisi
2025-05-13 17:47 ` [PATCH v4 05/26] arm64/sysreg: Add ICC_PPI_HMR<n>_EL1 Lorenzo Pieralisi
2025-05-13 17:47 ` [PATCH v4 06/26] arm64/sysreg: Add ICC_PPI_ENABLER<n>_EL1 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 07/26] arm64/sysreg: Add ICC_PPI_{C/S}ACTIVER<n>_EL1 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 08/26] arm64/sysreg: Add ICC_PPI_{C/S}PENDR<n>_EL1 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 09/26] arm64/sysreg: Add ICC_CR0_EL1 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 10/26] arm64/sysreg: Add ICC_PCR_EL1 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 11/26] arm64/sysreg: Add ICC_IDR0_EL1 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 12/26] arm64/sysreg: Add ICH_HFGRTR_EL2 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 13/26] arm64/sysreg: Add ICH_HFGWTR_EL2 Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 14/26] arm64/sysreg: Add ICH_HFGITR_EL2 Lorenzo Pieralisi
2025-05-28 11:28   ` Jonathan Cameron
2025-05-28 14:30     ` Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 15/26] arm64: Disable GICv5 read/write/instruction traps Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 16/26] arm64: cpucaps: Rename GICv3 CPU interface capability Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 17/26] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 18/26] arm64: smp: Support non-SGIs for IPIs Lorenzo Pieralisi
2025-05-14 10:39   ` Lorenzo Pieralisi
2025-05-14 16:05     ` Lorenzo Pieralisi
2025-05-28 12:17   ` Jonathan Cameron
2025-05-28 14:28     ` Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 19/26] arm64: Add support for GICv5 GSB barriers Lorenzo Pieralisi
2025-05-28 13:17   ` Jonathan Cameron
2025-05-28 14:34     ` Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 20/26] irqchip/gic-v5: Add GICv5 PPI support Lorenzo Pieralisi
2025-05-28 14:15   ` Jonathan Cameron
2025-05-29  7:57     ` Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 21/26] irqchip/gic-v5: Add GICv5 IRS/SPI support Lorenzo Pieralisi
2025-05-28 16:03   ` Jonathan Cameron
2025-05-29  8:38     ` Lorenzo Pieralisi
2025-05-29  8:45       ` Alireza Sanaee
2025-05-29  9:32         ` Lorenzo Pieralisi
2025-05-29 11:17           ` Alireza Sanaee
2025-05-13 17:48 ` [PATCH v4 22/26] irqchip/gic-v5: Add GICv5 LPI/IPI support Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 23/26] irqchip/gic-v5: Enable GICv5 SMP booting Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 24/26] irqchip/gic-v5: Add GICv5 ITS support Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 25/26] irqchip/gic-v5: Add GICv5 IWB support Lorenzo Pieralisi
2025-05-13 17:48 ` [PATCH v4 26/26] arm64: Kconfig: Enable GICv5 Lorenzo Pieralisi

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