Devicetree
 help / color / mirror / Atom feed
* [PATCH] arm64: dts: renesas: r9a09g047e57-smarc: Reduce I2C2 clock frequency
@ 2025-05-18 22:08 John Madieu
  2025-05-19  6:21 ` Wolfram Sang
  2025-05-19  8:28 ` Geert Uytterhoeven
  0 siblings, 2 replies; 5+ messages in thread
From: John Madieu @ 2025-05-18 22:08 UTC (permalink / raw)
  To: geert+renesas, magnus.damm, robh, krzk+dt, conor+dt
  Cc: biju.das.jz, linux-renesas-soc, devicetree, linux-kernel,
	John Madieu

Lower the I2C2 bus clock frequency on the RZ/G3E SMARC SoM from 1MHz to 400KHz
to improve compatibility with a wider range of I2C peripherals. The previous
1MHz setting was too aggressive for some devices on the bus, which experienced
timing issues at such a frequency.

Fixes: f7a98e256ee3 ("arm64: dts: renesas: rzg3e-smarc-som: Add I2C2 device pincontrol")
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
index 43d79158d81a..ecea29a76b14 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -85,7 +85,7 @@ &gpu {
 &i2c2 {
 	pinctrl-0 = <&i2c2_pins>;
 	pinctrl-names = "default";
-	clock-frequency = <1000000>;
+	clock-frequency = <400000>;
 	status = "okay";
 
 	raa215300: pmic@12 {
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [PATCH] arm64: dts: renesas: r9a09g047e57-smarc: Reduce I2C2 clock frequency
  2025-05-18 22:08 [PATCH] arm64: dts: renesas: r9a09g047e57-smarc: Reduce I2C2 clock frequency John Madieu
@ 2025-05-19  6:21 ` Wolfram Sang
  2025-05-19  8:28 ` Geert Uytterhoeven
  1 sibling, 0 replies; 5+ messages in thread
From: Wolfram Sang @ 2025-05-19  6:21 UTC (permalink / raw)
  To: John Madieu
  Cc: geert+renesas, magnus.damm, robh, krzk+dt, conor+dt, biju.das.jz,
	linux-renesas-soc, devicetree, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 568 bytes --]

On Mon, May 19, 2025 at 12:08:12AM +0200, John Madieu wrote:
> Lower the I2C2 bus clock frequency on the RZ/G3E SMARC SoM from 1MHz to 400KHz
> to improve compatibility with a wider range of I2C peripherals. The previous
> 1MHz setting was too aggressive for some devices on the bus, which experienced
> timing issues at such a frequency.
> 
> Fixes: f7a98e256ee3 ("arm64: dts: renesas: rzg3e-smarc-som: Add I2C2 device pincontrol")
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] arm64: dts: renesas: r9a09g047e57-smarc: Reduce I2C2 clock frequency
  2025-05-18 22:08 [PATCH] arm64: dts: renesas: r9a09g047e57-smarc: Reduce I2C2 clock frequency John Madieu
  2025-05-19  6:21 ` Wolfram Sang
@ 2025-05-19  8:28 ` Geert Uytterhoeven
  2025-05-19  8:56   ` John Madieu
  1 sibling, 1 reply; 5+ messages in thread
From: Geert Uytterhoeven @ 2025-05-19  8:28 UTC (permalink / raw)
  To: John Madieu
  Cc: geert+renesas, magnus.damm, robh, krzk+dt, conor+dt, biju.das.jz,
	linux-renesas-soc, devicetree, linux-kernel

Hi John,

On Mon, 19 May 2025 at 00:08, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> Lower the I2C2 bus clock frequency on the RZ/G3E SMARC SoM from 1MHz to 400KHz
> to improve compatibility with a wider range of I2C peripherals. The previous
> 1MHz setting was too aggressive for some devices on the bus, which experienced
> timing issues at such a frequency.
>
> Fixes: f7a98e256ee3 ("arm64: dts: renesas: rzg3e-smarc-som: Add I2C2 device pincontrol")
> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> @@ -85,7 +85,7 @@ &gpu {
>  &i2c2 {
>         pinctrl-0 = <&i2c2_pins>;
>         pinctrl-names = "default";
> -       clock-frequency = <1000000>;
> +       clock-frequency = <400000>;
>         status = "okay";
>
>         raa215300: pmic@12 {

Can you please clarify which devices on this bus do not support 1 MHz?
Or perhaps this is a board layout issue?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 5+ messages in thread

* RE: [PATCH] arm64: dts: renesas: r9a09g047e57-smarc: Reduce I2C2 clock frequency
  2025-05-19  8:28 ` Geert Uytterhoeven
@ 2025-05-19  8:56   ` John Madieu
  2025-05-23 15:39     ` Geert Uytterhoeven
  0 siblings, 1 reply; 5+ messages in thread
From: John Madieu @ 2025-05-19  8:56 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: geert+renesas@glider.be, magnus.damm@gmail.com, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, Biju Das,
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Monday, May 19, 2025 10:29 AM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH] arm64: dts: renesas: r9a09g047e57-smarc: Reduce I2C2
> clock frequency
> 
> Hi John,
> 
> On Mon, 19 May 2025 at 00:08, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > Lower the I2C2 bus clock frequency on the RZ/G3E SMARC SoM from 1MHz
> > to 400KHz to improve compatibility with a wider range of I2C
> > peripherals. The previous 1MHz setting was too aggressive for some
> > devices on the bus, which experienced timing issues at such a frequency.
> >

Thanks for the feedback.

> 
> > --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > @@ -85,7 +85,7 @@ &gpu {
> >  &i2c2 {
> >         pinctrl-0 = <&i2c2_pins>;
> >         pinctrl-names = "default";
> > -       clock-frequency = <1000000>;
> > +       clock-frequency = <400000>;
> >         status = "okay";
> >
> >         raa215300: pmic@12 {
> 
> Can you please clarify which devices on this bus do not support 1 MHz?
> Or perhaps this is a board layout issue?
> 

This is mainly the case for the GreenPAK device, that is programmed to
Operate at 400KHz.

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
Regards,
John

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] arm64: dts: renesas: r9a09g047e57-smarc: Reduce I2C2 clock frequency
  2025-05-19  8:56   ` John Madieu
@ 2025-05-23 15:39     ` Geert Uytterhoeven
  0 siblings, 0 replies; 5+ messages in thread
From: Geert Uytterhoeven @ 2025-05-23 15:39 UTC (permalink / raw)
  To: John Madieu
  Cc: magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, Biju Das, linux-renesas-soc@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org

Hi John,

On Mon, 19 May 2025 at 10:56, John Madieu <john.madieu.xa@bp.renesas.com> wrote:
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > On Mon, 19 May 2025 at 00:08, John Madieu <john.madieu.xa@bp.renesas.com>
> > wrote:
> > > Lower the I2C2 bus clock frequency on the RZ/G3E SMARC SoM from 1MHz
> > > to 400KHz to improve compatibility with a wider range of I2C
> > > peripherals. The previous 1MHz setting was too aggressive for some
> > > devices on the bus, which experienced timing issues at such a frequency.
> > >
> > > --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
> > > @@ -85,7 +85,7 @@ &gpu {
> > >  &i2c2 {
> > >         pinctrl-0 = <&i2c2_pins>;
> > >         pinctrl-names = "default";
> > > -       clock-frequency = <1000000>;
> > > +       clock-frequency = <400000>;
> > >         status = "okay";
> > >
> > >         raa215300: pmic@12 {
> >
> > Can you please clarify which devices on this bus do not support 1 MHz?
> > Or perhaps this is a board layout issue?
>
> This is mainly the case for the GreenPAK device, that is programmed to
> Operate at 400KHz.

Thanks for the clarification!

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel as a fix for v6.16, with the clarification
added.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2025-05-23 15:39 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-05-18 22:08 [PATCH] arm64: dts: renesas: r9a09g047e57-smarc: Reduce I2C2 clock frequency John Madieu
2025-05-19  6:21 ` Wolfram Sang
2025-05-19  8:28 ` Geert Uytterhoeven
2025-05-19  8:56   ` John Madieu
2025-05-23 15:39     ` Geert Uytterhoeven

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox