[PATCH v3 0/3] Add SpacemiT K1 USB3.0 host controller support

[PATCH v3 0/3] Add SpacemiT K1 USB3.0 host controller support

[Ze Huang]

The USB 3.0 controller found in the SpacemiT K1 SoC[1] supports both USB3.0
Host and USB2.0 Dual-Role Device (DRD). The PHY interfaces required for the
K1 USB subsystem — PIPE3 (for USB 3.0) and UTMI+ (for USB 2.0) — have
already been supported in a separate patchset [2].

This controller is compatible with DesignWare Core USB 3 (DWC3) driver.
However, constraints in the snps,dwc3 binding limit the ability to extend
properties to describe hardware variations. The existing generic DWC3 driver,
dwc3-of-simple, still functions as a glue layer.

To address this and promote trasition to flattened dwc node, this patch
introduces dwc3-common, building upon prior work that exposed the DWC3 core
driver [3].

This patchset is based on usb-next (6.15-rc6) and has been tested on BananaPi and Jupiter development boards.

Link: https://developer.spacemit.com/documentation?token=AjHDwrW78igAAEkiHracBI9HnTb [1]
Link: https://lore.kernel.org/linux-riscv/20250418-b4-k1-usb3-phy-v2-v2-0-b69e02da84eb@whut.edu.cn [2]
Link: https://lore.kernel.org/all/20250414-dwc3-refactor-v7-3-f015b358722d@oss.qualcomm.com [3]

Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
Changes in v3:
- introduce dwc3-common for generic dwc3 hardware
- fix warnings in usb host dt-bindings
- fix errors in dts
- Link to v2: https://lore.kernel.org/r/20250428-b4-k1-dwc3-v2-v1-0-7cb061abd619@whut.edu.cn

Changes in v2:
- dt-bindings:
  - add missing 'maxItems'
  - remove 'status' property in exmaple
  - fold dwc3 node into parent
- drop dwc3 glue driver and use snps,dwc3 driver directly
- rename dts nodes and reorder properties to fit coding style
- Link to v1: https://lore.kernel.org/all/20250407-b4-k1-usb3-v3-2-v1-0-bf0bcc41c9ba@whut.edu.cn

---
Ze Huang (3):
      dt-bindings: usb: dwc3: add support for SpacemiT K1
      usb: dwc3: add common driver to support flattened DT
      riscv: dts: spacemit: add usb3.0 support for K1

 .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml  |  84 +++++++++
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts    |  50 ++++++
 arch/riscv/boot/dts/spacemit/k1.dtsi               |  69 ++++++++
 drivers/usb/dwc3/Kconfig                           |   9 +
 drivers/usb/dwc3/Makefile                          |   1 +
 drivers/usb/dwc3/dwc3-common.c                     | 191 +++++++++++++++++++++
 6 files changed, 404 insertions(+)
---
base-commit: ab6dc9a6c721c2eed867c157447764ae68ff9b7e
change-id: 20250517-b4-k1-dwc3-v3-5208a002728a

Best regards,
-- 
Ze Huang <huangze@whut.edu.cn>

[PATCH v3 1/3] dt-bindings: usb: dwc3: add support for SpacemiT K1

[Ze Huang]

Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
in the SpacemiT K1 SoC. The controller is based on the Synopsys
DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0
DRD mode.

Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
 .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml  | 84 ++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..2fb9f1014c4e901417818a37b6289814a2d3d49a
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller
+
+maintainers:
+  - Ze Huang <huangze@whut.edu.cn>
+
+description: |
+  The SpacemiT K1 embeds a DWC3 USB IP Core which supports Host functions
+  for USB 3.0 and DRD for USB 2.0.
+
+  Key features:
+  - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support
+  - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3)
+  - Internal DMA controller and flexible endpoint FIFO sizing
+
+  Communication Interface:
+  - Use of PIPE3 (125MHz) interface for USB3.0 PHY
+  - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY
+
+allOf:
+  - $ref: snps,dwc3-common.yaml#
+
+properties:
+  compatible:
+    const: spacemit,k1-dwc3
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: usbdrd30
+
+  resets:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interconnects:
+    maxItems: 1
+    description:
+      On SpacemiT K1, USB performs DMA through bus other than parent DT node.
+      The 'interconnects' property explicitly describes this path, ensuring
+      correct address translation.
+
+  interconnect-names:
+    const: dma-mem
+
+  vbus-supply:
+    description: A phandle to the regulator supplying the VBUS voltage.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - interrupts
+  - interconnects
+  - interconnect-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    usb@c0a00000 {
+        compatible = "spacemit,k1-dwc3";
+        reg = <0xc0a00000 0x10000>;
+        clocks = <&syscon_apmu 16>;
+        clock-names = "usbdrd30";
+        resets = <&syscon_apmu 8>;
+        interrupt-parent = <&plic>;
+        interrupts = <125>;
+        interconnects = <&mbus0>;
+        interconnect-names = "dma-mem";
+    };

-- 
2.49.0

Re: [PATCH v3 1/3] dt-bindings: usb: dwc3: add support for SpacemiT K1

[Krzysztof Kozlowski]

On Sun, May 18, 2025 at 03:19:19AM GMT, Ze Huang wrote:
> +properties:
> +  compatible:
> +    const: spacemit,k1-dwc3
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    const: usbdrd30
> +

How many phys?

> +  resets:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interconnects:

compatible, reg and then order by name: clocks +names, interconnects +
names, interrupts, resets, vdd-supply.

> +    maxItems: 1
> +    description:
> +      On SpacemiT K1, USB performs DMA through bus other than parent DT node.
> +      The 'interconnects' property explicitly describes this path, ensuring
> +      correct address translation.
> +
> +  interconnect-names:
> +    const: dma-mem
> +
> +  vbus-supply:
> +    description: A phandle to the regulator supplying the VBUS voltage.
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - resets
> +  - interrupts
> +  - interconnects
> +  - interconnect-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    usb@c0a00000 {
> +        compatible = "spacemit,k1-dwc3";
> +        reg = <0xc0a00000 0x10000>;
> +        clocks = <&syscon_apmu 16>;
> +        clock-names = "usbdrd30";
> +        resets = <&syscon_apmu 8>;
> +        interrupt-parent = <&plic>;
> +        interrupts = <125>;
> +        interconnects = <&mbus0>;
> +        interconnect-names = "dma-mem";

Feels like missing port or ports. Are you sure your example is complete?

> +    };
> 
> -- 
> 2.49.0
> 

Re: [PATCH v3 1/3] dt-bindings: usb: dwc3: add support for SpacemiT K1

[Ze Huang]

On Mon, May 19, 2025 at 11:35:28AM +0200, Krzysztof Kozlowski wrote:
> On Sun, May 18, 2025 at 03:19:19AM GMT, Ze Huang wrote:
> > +properties:
> > +  compatible:
> > +    const: spacemit,k1-dwc3
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  clock-names:
> > +    const: usbdrd30
> > +
> 
> How many phys?
> 

Two phys: USB2.0 phy and USB3.0 phy

Will update the bindings in next version.

> > +  resets:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  interconnects:
> 
> compatible, reg and then order by name: clocks +names, interconnects +
> names, interrupts, resets, vdd-supply.
> 

Got it wrong again - thanks for your patience.

I'll update the property order as you suggested.

> > +    maxItems: 1
> > +    description:
> > +      On SpacemiT K1, USB performs DMA through bus other than parent DT node.
> > +      The 'interconnects' property explicitly describes this path, ensuring
> > +      correct address translation.
> > +
> > +  interconnect-names:
> > +    const: dma-mem
> > +
> > +  vbus-supply:
> > +    description: A phandle to the regulator supplying the VBUS voltage.
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - clock-names
> > +  - resets
> > +  - interrupts
> > +  - interconnects
> > +  - interconnect-names
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > +  - |
> > +    usb@c0a00000 {
> > +        compatible = "spacemit,k1-dwc3";
> > +        reg = <0xc0a00000 0x10000>;
> > +        clocks = <&syscon_apmu 16>;
> > +        clock-names = "usbdrd30";
> > +        resets = <&syscon_apmu 8>;
> > +        interrupt-parent = <&plic>;
> > +        interrupts = <125>;
> > +        interconnects = <&mbus0>;
> > +        interconnect-names = "dma-mem";
> 
> Feels like missing port or ports. Are you sure your example is complete?
> 

Will include ports in next version

    hub@1 {
        compatible = "usb2109,2817";
        reg = <0x1>;
        vdd-supply = <&usb3_vhub>;
        peer-hub = <&hub_3_0>;
        reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
    };

    hub@2 {
        compatible = "usb2109,817";
        reg = <0x1>;
        vdd-supply = <&usb3_vhub>;
        peer-hub = <&hub_2_0>;
        reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
    };

[PATCH v3 2/3] usb: dwc3: add common driver to support flattened DT

[Ze Huang]

To support flattened dwc3 dt model and drop the glue layer, introduce the
`dwc3-common` driver. This enables direct binding of the DWC3 core driver
and offers an alternative to the existing glue driver `dwc3-of-simple`.

Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
 drivers/usb/dwc3/Kconfig       |   9 ++
 drivers/usb/dwc3/Makefile      |   1 +
 drivers/usb/dwc3/dwc3-common.c | 191 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 201 insertions(+)

diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 310d182e10b50b253d7e5a51674806e6ec442a2a..852f94f906e4f339dcbb562e1ce708409ba77b76 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
 	  Currently supports Xilinx and Qualcomm DWC USB3 IP.
 	  Say 'Y' or 'M' if you have one such device.
 
+config USB_DWC3_COMMON
+       tristate "DWC3 Platform common Driver"
+       depends on OF && COMMON_CLK
+       default USB_DWC3
+       help
+         Support USB3 functionality in simple SoC integrations.
+         Currently supports SpacemiT DWC USB3 IP.
+         Say 'Y' or 'M' if you have one such device.
+
 config USB_DWC3_ST
 	tristate "STMicroelectronics Platforms"
 	depends on (ARCH_STI || COMPILE_TEST) && OF
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..ad1b0705c4d464f19e79ed0c3c63d942446e4742 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP)		+= dwc3-imx8mp.o
 obj-$(CONFIG_USB_DWC3_XILINX)		+= dwc3-xilinx.o
 obj-$(CONFIG_USB_DWC3_OCTEON)		+= dwc3-octeon.o
 obj-$(CONFIG_USB_DWC3_RTK)		+= dwc3-rtk.o
+obj-$(CONFIG_USB_DWC3_COMMON)		+= dwc3-common.o
diff --git a/drivers/usb/dwc3/dwc3-common.c b/drivers/usb/dwc3/dwc3-common.c
new file mode 100644
index 0000000000000000000000000000000000000000..afd9a7bec14b68dfd4f2353d714041882660a1a4
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-common.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * dwc3-common.c - DesignWare USB3 common driver
+ *
+ * Copyright (C) 2025 Ze Huang <huangze@whut.edu.cn>
+ *
+ * Inspired by dwc3-qcom.c and dwc3-of-simple.c
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include "glue.h"
+
+struct dwc3_common {
+	struct device		*dev;
+	struct dwc3		dwc;
+	struct clk_bulk_data	*clks;
+	int			num_clocks;
+	struct reset_control	*resets;
+};
+
+static int dwc3_common_probe(struct platform_device *pdev)
+{
+	struct dwc3_probe_data probe_data = {};
+	struct device *dev = &pdev->dev;
+	struct dwc3_common *dwc3c;
+	struct resource *res;
+	int ret;
+
+	dwc3c = devm_kzalloc(dev, sizeof(*dwc3c), GFP_KERNEL);
+	if (!dwc3c)
+		return -ENOMEM;
+
+	dwc3c->dev = dev;
+
+	platform_set_drvdata(pdev, dwc3c);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "missing memory resource\n");
+		return -ENODEV;
+	}
+
+	dwc3c->resets = of_reset_control_array_get_optional_exclusive(dev->of_node);
+	if (IS_ERR(dwc3c->resets))
+		return dev_err_probe(dev, PTR_ERR(dwc3c->resets), "failed to get reset\n");
+
+	ret = reset_control_assert(dwc3c->resets);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to assert reset\n");
+
+	usleep_range(10, 1000);
+
+	ret = reset_control_deassert(dwc3c->resets);
+	if (ret) {
+		dev_err(dev, "failed to deassert reset\n");
+		goto reset_assert;
+	}
+
+	ret = clk_bulk_get_all(dwc3c->dev, &dwc3c->clks);
+	if (ret < 0) {
+		dev_err(dev, "failed to get clocks\n");
+		goto reset_assert;
+	}
+
+	dwc3c->num_clocks = ret;
+
+	ret = clk_bulk_prepare_enable(dwc3c->num_clocks, dwc3c->clks);
+	if (ret) {
+		dev_err(dev, "failed to enable clocks\n");
+		goto reset_assert;
+	}
+
+	dwc3c->dwc.dev = dev;
+	probe_data.dwc = &dwc3c->dwc;
+	probe_data.res = res;
+	probe_data.ignore_clocks_and_resets = true;
+	ret = dwc3_core_probe(&probe_data);
+	if (ret)  {
+		dev_err(dev, "failed to register DWC3 Core\n");
+		goto clk_disable;
+	}
+
+	return 0;
+
+clk_disable:
+	clk_bulk_disable_unprepare(dwc3c->num_clocks, dwc3c->clks);
+	clk_bulk_put_all(dwc3c->num_clocks, dwc3c->clks);
+
+reset_assert:
+	reset_control_assert(dwc3c->resets);
+
+	return ret;
+}
+
+static void dwc3_common_remove(struct platform_device *pdev)
+{
+	struct dwc3_common *dwc3c = platform_get_drvdata(pdev);
+
+	dwc3_core_remove(&dwc3c->dwc);
+
+	clk_bulk_disable_unprepare(dwc3c->num_clocks, dwc3c->clks);
+	clk_bulk_put_all(dwc3c->num_clocks, dwc3c->clks);
+
+	reset_control_assert(dwc3c->resets);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int dwc3_common_suspend(struct device *dev)
+{
+	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
+	int ret;
+
+	ret = dwc3_pm_suspend(&dwc3c->dwc);
+	if (ret)
+		return ret;
+
+	clk_bulk_disable_unprepare(dwc3c->num_clocks, dwc3c->clks);
+
+	return 0;
+}
+
+static int dwc3_common_resume(struct device *dev)
+{
+	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
+	int ret;
+
+	ret = clk_bulk_prepare_enable(dwc3c->num_clocks, dwc3c->clks);
+	if (ret)
+		return ret;
+
+	ret = dwc3_pm_resume(&dwc3c->dwc);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int dwc3_common_runtime_suspend(struct device *dev)
+{
+	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
+
+	return dwc3_runtime_suspend(&dwc3c->dwc);
+}
+
+static int dwc3_common_runtime_resume(struct device *dev)
+{
+	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
+
+	return dwc3_runtime_resume(&dwc3c->dwc);
+}
+
+static int dwc3_common_runtime_idle(struct device *dev)
+{
+	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
+
+	return dwc3_runtime_idle(&dwc3c->dwc);
+}
+
+static const struct dev_pm_ops dwc3_common_dev_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(dwc3_common_suspend, dwc3_common_resume)
+	RUNTIME_PM_OPS(dwc3_common_runtime_suspend, dwc3_common_runtime_resume,
+		       dwc3_common_runtime_idle)
+};
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct of_device_id dwc3_common_of_match[] = {
+	{ .compatible = "spacemit,k1-dwc3", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dwc3_common_of_match);
+
+static struct platform_driver dwc3_common_driver = {
+	.probe		= dwc3_common_probe,
+	.remove		= dwc3_common_remove,
+	.driver		= {
+		.name	= "dwc3-common",
+		.of_match_table = dwc3_common_of_match,
+#ifdef CONFIG_PM_SLEEP
+		.pm	= &dwc3_common_dev_pm_ops,
+#endif /* CONFIG_PM_SLEEP */
+	},
+};
+module_platform_driver(dwc3_common_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("DesignWare USB3 common driver");

-- 
2.49.0

Re: [PATCH v3 2/3] usb: dwc3: add common driver to support flattened DT

[Thinh Nguyen]

On Sun, May 18, 2025, Ze Huang wrote:
> To support flattened dwc3 dt model and drop the glue layer, introduce the
> `dwc3-common` driver. This enables direct binding of the DWC3 core driver
> and offers an alternative to the existing glue driver `dwc3-of-simple`.
> 
> Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> ---
>  drivers/usb/dwc3/Kconfig       |   9 ++
>  drivers/usb/dwc3/Makefile      |   1 +
>  drivers/usb/dwc3/dwc3-common.c | 191 +++++++++++++++++++++++++++++++++++++++++

Let's rename the dwc3-common to dwc3-generic-plat. I'd associate
"common" to common code that exists in all drivers; where as this is
mainly for generic platform driver.

>  3 files changed, 201 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> index 310d182e10b50b253d7e5a51674806e6ec442a2a..852f94f906e4f339dcbb562e1ce708409ba77b76 100644
> --- a/drivers/usb/dwc3/Kconfig
> +++ b/drivers/usb/dwc3/Kconfig
> @@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
>  	  Currently supports Xilinx and Qualcomm DWC USB3 IP.
>  	  Say 'Y' or 'M' if you have one such device.
>  
> +config USB_DWC3_COMMON

Let's rename to USB_DWC3_GENERIC_PLAT. I would expect to also have
USB_DWC3_GENERIC_PCI at some point in the future.

Side note: flattened driver for PCI driver will allow the dwc3
host controllers to take advantage of MSIX interrupts going through the
dwc3 code path.

> +       tristate "DWC3 Platform common Driver"
> +       depends on OF && COMMON_CLK
> +       default USB_DWC3
> +       help
> +         Support USB3 functionality in simple SoC integrations.
> +         Currently supports SpacemiT DWC USB3 IP.
> +         Say 'Y' or 'M' if you have one such device.
> +
>  config USB_DWC3_ST
>  	tristate "STMicroelectronics Platforms"
>  	depends on (ARCH_STI || COMPILE_TEST) && OF
> diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
> index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..ad1b0705c4d464f19e79ed0c3c63d942446e4742 100644
> --- a/drivers/usb/dwc3/Makefile
> +++ b/drivers/usb/dwc3/Makefile
> @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP)		+= dwc3-imx8mp.o
>  obj-$(CONFIG_USB_DWC3_XILINX)		+= dwc3-xilinx.o
>  obj-$(CONFIG_USB_DWC3_OCTEON)		+= dwc3-octeon.o
>  obj-$(CONFIG_USB_DWC3_RTK)		+= dwc3-rtk.o
> +obj-$(CONFIG_USB_DWC3_COMMON)		+= dwc3-common.o
> diff --git a/drivers/usb/dwc3/dwc3-common.c b/drivers/usb/dwc3/dwc3-common.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..afd9a7bec14b68dfd4f2353d714041882660a1a4
> --- /dev/null
> +++ b/drivers/usb/dwc3/dwc3-common.c
> @@ -0,0 +1,191 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * dwc3-common.c - DesignWare USB3 common driver
> + *
> + * Copyright (C) 2025 Ze Huang <huangze@whut.edu.cn>
> + *
> + * Inspired by dwc3-qcom.c and dwc3-of-simple.c
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include "glue.h"
> +
> +struct dwc3_common {
> +	struct device		*dev;
> +	struct dwc3		dwc;
> +	struct clk_bulk_data	*clks;
> +	int			num_clocks;
> +	struct reset_control	*resets;
> +};
> +
> +static int dwc3_common_probe(struct platform_device *pdev)
> +{
> +	struct dwc3_probe_data probe_data = {};
> +	struct device *dev = &pdev->dev;
> +	struct dwc3_common *dwc3c;
> +	struct resource *res;
> +	int ret;
> +
> +	dwc3c = devm_kzalloc(dev, sizeof(*dwc3c), GFP_KERNEL);
> +	if (!dwc3c)
> +		return -ENOMEM;
> +
> +	dwc3c->dev = dev;
> +
> +	platform_set_drvdata(pdev, dwc3c);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		dev_err(&pdev->dev, "missing memory resource\n");
> +		return -ENODEV;
> +	}
> +
> +	dwc3c->resets = of_reset_control_array_get_optional_exclusive(dev->of_node);
> +	if (IS_ERR(dwc3c->resets))
> +		return dev_err_probe(dev, PTR_ERR(dwc3c->resets), "failed to get reset\n");
> +
> +	ret = reset_control_assert(dwc3c->resets);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "failed to assert reset\n");
> +
> +	usleep_range(10, 1000);
> +
> +	ret = reset_control_deassert(dwc3c->resets);
> +	if (ret) {
> +		dev_err(dev, "failed to deassert reset\n");
> +		goto reset_assert;
> +	}
> +
> +	ret = clk_bulk_get_all(dwc3c->dev, &dwc3c->clks);
> +	if (ret < 0) {
> +		dev_err(dev, "failed to get clocks\n");
> +		goto reset_assert;
> +	}
> +
> +	dwc3c->num_clocks = ret;
> +
> +	ret = clk_bulk_prepare_enable(dwc3c->num_clocks, dwc3c->clks);
> +	if (ret) {
> +		dev_err(dev, "failed to enable clocks\n");
> +		goto reset_assert;
> +	}
> +
> +	dwc3c->dwc.dev = dev;
> +	probe_data.dwc = &dwc3c->dwc;
> +	probe_data.res = res;
> +	probe_data.ignore_clocks_and_resets = true;
> +	ret = dwc3_core_probe(&probe_data);
> +	if (ret)  {
> +		dev_err(dev, "failed to register DWC3 Core\n");
> +		goto clk_disable;
> +	}
> +
> +	return 0;
> +
> +clk_disable:
> +	clk_bulk_disable_unprepare(dwc3c->num_clocks, dwc3c->clks);
> +	clk_bulk_put_all(dwc3c->num_clocks, dwc3c->clks);
> +
> +reset_assert:
> +	reset_control_assert(dwc3c->resets);
> +
> +	return ret;
> +}
> +
> +static void dwc3_common_remove(struct platform_device *pdev)
> +{
> +	struct dwc3_common *dwc3c = platform_get_drvdata(pdev);
> +
> +	dwc3_core_remove(&dwc3c->dwc);
> +
> +	clk_bulk_disable_unprepare(dwc3c->num_clocks, dwc3c->clks);
> +	clk_bulk_put_all(dwc3c->num_clocks, dwc3c->clks);
> +
> +	reset_control_assert(dwc3c->resets);
> +}
> +
> +#ifdef CONFIG_PM_SLEEP

Use the new SYSTEM_SLEEP_PM_OPS macros and we can do away with these PM
guards.

> +static int dwc3_common_suspend(struct device *dev)
> +{
> +	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
> +	int ret;
> +
> +	ret = dwc3_pm_suspend(&dwc3c->dwc);
> +	if (ret)
> +		return ret;
> +
> +	clk_bulk_disable_unprepare(dwc3c->num_clocks, dwc3c->clks);
> +
> +	return 0;
> +}
> +
> +static int dwc3_common_resume(struct device *dev)
> +{
> +	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
> +	int ret;
> +
> +	ret = clk_bulk_prepare_enable(dwc3c->num_clocks, dwc3c->clks);
> +	if (ret)
> +		return ret;
> +
> +	ret = dwc3_pm_resume(&dwc3c->dwc);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static int dwc3_common_runtime_suspend(struct device *dev)
> +{
> +	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
> +
> +	return dwc3_runtime_suspend(&dwc3c->dwc);
> +}
> +
> +static int dwc3_common_runtime_resume(struct device *dev)
> +{
> +	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
> +
> +	return dwc3_runtime_resume(&dwc3c->dwc);
> +}
> +
> +static int dwc3_common_runtime_idle(struct device *dev)
> +{
> +	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
> +
> +	return dwc3_runtime_idle(&dwc3c->dwc);
> +}
> +
> +static const struct dev_pm_ops dwc3_common_dev_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(dwc3_common_suspend, dwc3_common_resume)
> +	RUNTIME_PM_OPS(dwc3_common_runtime_suspend, dwc3_common_runtime_resume,
> +		       dwc3_common_runtime_idle)
> +};
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static const struct of_device_id dwc3_common_of_match[] = {
> +	{ .compatible = "spacemit,k1-dwc3", },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, dwc3_common_of_match);
> +
> +static struct platform_driver dwc3_common_driver = {
> +	.probe		= dwc3_common_probe,
> +	.remove		= dwc3_common_remove,
> +	.driver		= {
> +		.name	= "dwc3-common",
> +		.of_match_table = dwc3_common_of_match,
> +#ifdef CONFIG_PM_SLEEP
> +		.pm	= &dwc3_common_dev_pm_ops,
> +#endif /* CONFIG_PM_SLEEP */
> +	},
> +};
> +module_platform_driver(dwc3_common_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("DesignWare USB3 common driver");
> 
> -- 
> 2.49.0
> 

Thanks for the work. Going forward, I hope more platforms will move to
this and take advantage of this new flattened model.

Thanks,
Thinh

Re: [PATCH v3 2/3] usb: dwc3: add common driver to support flattened DT

[Ze Huang]

On Mon, May 19, 2025 at 11:37:35PM +0000, Thinh Nguyen wrote:
> On Sun, May 18, 2025, Ze Huang wrote:
> > To support flattened dwc3 dt model and drop the glue layer, introduce the
> > `dwc3-common` driver. This enables direct binding of the DWC3 core driver
> > and offers an alternative to the existing glue driver `dwc3-of-simple`.
> > 
> > Signed-off-by: Ze Huang <huangze@whut.edu.cn>
> > ---
> >  drivers/usb/dwc3/Kconfig       |   9 ++
> >  drivers/usb/dwc3/Makefile      |   1 +
> >  drivers/usb/dwc3/dwc3-common.c | 191 +++++++++++++++++++++++++++++++++++++++++
> 
> Let's rename the dwc3-common to dwc3-generic-plat. I'd associate
> "common" to common code that exists in all drivers; where as this is
> mainly for generic platform driver.
> 

You're right, will do.

> >  3 files changed, 201 insertions(+)
> > 
> > diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> > index 310d182e10b50b253d7e5a51674806e6ec442a2a..852f94f906e4f339dcbb562e1ce708409ba77b76 100644
> > --- a/drivers/usb/dwc3/Kconfig
> > +++ b/drivers/usb/dwc3/Kconfig
> > @@ -118,6 +118,15 @@ config USB_DWC3_OF_SIMPLE
> >  	  Currently supports Xilinx and Qualcomm DWC USB3 IP.
> >  	  Say 'Y' or 'M' if you have one such device.
> >  
> > +config USB_DWC3_COMMON
> 
> Let's rename to USB_DWC3_GENERIC_PLAT.

Will do

> I would expect to also have USB_DWC3_GENERIC_PCI at some point in the future.
> 
> Side note: flattened driver for PCI driver will allow the dwc3
> host controllers to take advantage of MSIX interrupts going through the
> dwc3 code path.
>

Thanks for pointing that out.

I don’t have a convenient setup to test PCI-based DWC3 controllers by the time,
but I’ll definitely look into it when the opportunity arises.

> 
> > +       tristate "DWC3 Platform common Driver"
> > +       depends on OF && COMMON_CLK
> > +       default USB_DWC3
> > +       help
> > +         Support USB3 functionality in simple SoC integrations.
> > +         Currently supports SpacemiT DWC USB3 IP.
> > +         Say 'Y' or 'M' if you have one such device.
> > +
> >  config USB_DWC3_ST
> >  	tristate "STMicroelectronics Platforms"
> >  	depends on (ARCH_STI || COMPILE_TEST) && OF
> > diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
> > index 830e6c9e5fe073c1f662ce34b6a4a2da34c407a2..ad1b0705c4d464f19e79ed0c3c63d942446e4742 100644
> > --- a/drivers/usb/dwc3/Makefile
> > +++ b/drivers/usb/dwc3/Makefile
> > @@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP)		+= dwc3-imx8mp.o
> >  obj-$(CONFIG_USB_DWC3_XILINX)		+= dwc3-xilinx.o
> >  obj-$(CONFIG_USB_DWC3_OCTEON)		+= dwc3-octeon.o
> >  obj-$(CONFIG_USB_DWC3_RTK)		+= dwc3-rtk.o
> > +obj-$(CONFIG_USB_DWC3_COMMON)		+= dwc3-common.o
> > diff --git a/drivers/usb/dwc3/dwc3-common.c b/drivers/usb/dwc3/dwc3-common.c
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..afd9a7bec14b68dfd4f2353d714041882660a1a4
> > --- /dev/null
> > +++ b/drivers/usb/dwc3/dwc3-common.c
> > @@ -0,0 +1,191 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * dwc3-common.c - DesignWare USB3 common driver
> > + *
> > + * Copyright (C) 2025 Ze Huang <huangze@whut.edu.cn>
> > + *
> > + * Inspired by dwc3-qcom.c and dwc3-of-simple.c
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reset.h>
> > +#include "glue.h"
> > +
> > +struct dwc3_common {
> > +	struct device		*dev;
> > +	struct dwc3		dwc;
> > +	struct clk_bulk_data	*clks;
> > +	int			num_clocks;
> > +	struct reset_control	*resets;
> > +};
> > +
> > +static int dwc3_common_probe(struct platform_device *pdev)
> > +{
> > +	struct dwc3_probe_data probe_data = {};
> > +	struct device *dev = &pdev->dev;
> > +	struct dwc3_common *dwc3c;
> > +	struct resource *res;
> > +	int ret;
> > +
> > +	dwc3c = devm_kzalloc(dev, sizeof(*dwc3c), GFP_KERNEL);
> > +	if (!dwc3c)
> > +		return -ENOMEM;
> > +
> > +	dwc3c->dev = dev;
> > +
> > +	platform_set_drvdata(pdev, dwc3c);
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	if (!res) {
> > +		dev_err(&pdev->dev, "missing memory resource\n");
> > +		return -ENODEV;
> > +	}
> > +
> > +	dwc3c->resets = of_reset_control_array_get_optional_exclusive(dev->of_node);
> > +	if (IS_ERR(dwc3c->resets))
> > +		return dev_err_probe(dev, PTR_ERR(dwc3c->resets), "failed to get reset\n");
> > +
> > +	ret = reset_control_assert(dwc3c->resets);
> > +	if (ret)
> > +		return dev_err_probe(dev, ret, "failed to assert reset\n");
> > +
> > +	usleep_range(10, 1000);
> > +
> > +	ret = reset_control_deassert(dwc3c->resets);
> > +	if (ret) {
> > +		dev_err(dev, "failed to deassert reset\n");
> > +		goto reset_assert;
> > +	}
> > +
> > +	ret = clk_bulk_get_all(dwc3c->dev, &dwc3c->clks);
> > +	if (ret < 0) {
> > +		dev_err(dev, "failed to get clocks\n");
> > +		goto reset_assert;
> > +	}
> > +
> > +	dwc3c->num_clocks = ret;
> > +
> > +	ret = clk_bulk_prepare_enable(dwc3c->num_clocks, dwc3c->clks);
> > +	if (ret) {
> > +		dev_err(dev, "failed to enable clocks\n");
> > +		goto reset_assert;
> > +	}
> > +
> > +	dwc3c->dwc.dev = dev;
> > +	probe_data.dwc = &dwc3c->dwc;
> > +	probe_data.res = res;
> > +	probe_data.ignore_clocks_and_resets = true;
> > +	ret = dwc3_core_probe(&probe_data);
> > +	if (ret)  {
> > +		dev_err(dev, "failed to register DWC3 Core\n");
> > +		goto clk_disable;
> > +	}
> > +
> > +	return 0;
> > +
> > +clk_disable:
> > +	clk_bulk_disable_unprepare(dwc3c->num_clocks, dwc3c->clks);
> > +	clk_bulk_put_all(dwc3c->num_clocks, dwc3c->clks);
> > +
> > +reset_assert:
> > +	reset_control_assert(dwc3c->resets);
> > +
> > +	return ret;
> > +}
> > +
> > +static void dwc3_common_remove(struct platform_device *pdev)
> > +{
> > +	struct dwc3_common *dwc3c = platform_get_drvdata(pdev);
> > +
> > +	dwc3_core_remove(&dwc3c->dwc);
> > +
> > +	clk_bulk_disable_unprepare(dwc3c->num_clocks, dwc3c->clks);
> > +	clk_bulk_put_all(dwc3c->num_clocks, dwc3c->clks);
> > +
> > +	reset_control_assert(dwc3c->resets);
> > +}
> > +
> > +#ifdef CONFIG_PM_SLEEP
> 
> Use the new SYSTEM_SLEEP_PM_OPS macros and we can do away with these PM
> guards.
> 

Will follow, thanks

> > +static int dwc3_common_suspend(struct device *dev)
> > +{
> > +	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
> > +	int ret;
> > +
> > +	ret = dwc3_pm_suspend(&dwc3c->dwc);
> > +	if (ret)
> > +		return ret;
> > +
> > +	clk_bulk_disable_unprepare(dwc3c->num_clocks, dwc3c->clks);
> > +
> > +	return 0;
> > +}
> > +
> > +static int dwc3_common_resume(struct device *dev)
> > +{
> > +	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
> > +	int ret;
> > +
> > +	ret = clk_bulk_prepare_enable(dwc3c->num_clocks, dwc3c->clks);
> > +	if (ret)
> > +		return ret;
> > +
> > +	ret = dwc3_pm_resume(&dwc3c->dwc);
> > +	if (ret)
> > +		return ret;
> > +
> > +	return 0;
> > +}
> > +
> > +static int dwc3_common_runtime_suspend(struct device *dev)
> > +{
> > +	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
> > +
> > +	return dwc3_runtime_suspend(&dwc3c->dwc);
> > +}
> > +
> > +static int dwc3_common_runtime_resume(struct device *dev)
> > +{
> > +	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
> > +
> > +	return dwc3_runtime_resume(&dwc3c->dwc);
> > +}
> > +
> > +static int dwc3_common_runtime_idle(struct device *dev)
> > +{
> > +	struct dwc3_common *dwc3c = dev_get_drvdata(dev);
> > +
> > +	return dwc3_runtime_idle(&dwc3c->dwc);
> > +}
> > +
> > +static const struct dev_pm_ops dwc3_common_dev_pm_ops = {
> > +	SET_SYSTEM_SLEEP_PM_OPS(dwc3_common_suspend, dwc3_common_resume)
> > +	RUNTIME_PM_OPS(dwc3_common_runtime_suspend, dwc3_common_runtime_resume,
> > +		       dwc3_common_runtime_idle)
> > +};
> > +#endif /* CONFIG_PM_SLEEP */
> > +
> > +static const struct of_device_id dwc3_common_of_match[] = {
> > +	{ .compatible = "spacemit,k1-dwc3", },
> > +	{ /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, dwc3_common_of_match);
> > +
> > +static struct platform_driver dwc3_common_driver = {
> > +	.probe		= dwc3_common_probe,
> > +	.remove		= dwc3_common_remove,
> > +	.driver		= {
> > +		.name	= "dwc3-common",
> > +		.of_match_table = dwc3_common_of_match,
> > +#ifdef CONFIG_PM_SLEEP
> > +		.pm	= &dwc3_common_dev_pm_ops,
> > +#endif /* CONFIG_PM_SLEEP */
> > +	},
> > +};
> > +module_platform_driver(dwc3_common_driver);
> > +
> > +MODULE_LICENSE("GPL");
> > +MODULE_DESCRIPTION("DesignWare USB3 common driver");
> > 
> > -- 
> > 2.49.0
> > 
> 
> Thanks for the work. Going forward, I hope more platforms will move to
> this and take advantage of this new flattened model.
> 

Thanks for the feedback! Looking forward to seeing it adopted more widely :-)

> Thanks,
> Thinh

[PATCH v3 3/3] riscv: dts: spacemit: add usb3.0 support for K1

[Ze Huang]

Add USB 3.0 support for the SpacemiT K1 SoC, including the
following components:

- USB 2.0 PHY nodes
- USB 3.0 combo PHY node
- USB 3.0 host controller
- USB 3.0 hub and vbus regulator (usb3_vhub, usb3_vbus)
- DRAM interconnect node for USB DMA ("dma-mem")

The `usb3_vbus` and `usb3_vhub` regulator node provides a fixed 5V
supply to power the onboard USB 3.0 hub and usb vbus.

On K1, some DMA transfers from devices to memory use separate buses with
different DMA address translation rules from the parent node. We express
this relationship through the interconnects node "dma-mem", similar to [1].

Link: https://lore.kernel.org/all/09e5e29a4c54ec7337e4e62e5d6001b69d92b103.1554108995.git-series.maxime.ripard@bootlin.com [1]

Signed-off-by: Ze Huang <huangze@whut.edu.cn>
---
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 50 ++++++++++++++++++
 arch/riscv/boot/dts/spacemit/k1.dtsi            | 69 +++++++++++++++++++++++++
 2 files changed, 119 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 816ef1bc358ec490aff184d5915d680dbd9f00cb..c5832b399f96b6bbede02fbb019c7b616cedff77 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -28,6 +28,25 @@ led1 {
 			default-state = "on";
 		};
 	};
+
+	usb3_vhub: regulator-vhub-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "USB30_VHUB";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	usb3_vbus: regulator-vbus-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "USB30_VBUS";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 };
 
 &uart0 {
@@ -35,3 +54,34 @@ &uart0 {
 	pinctrl-0 = <&uart0_2_cfg>;
 	status = "okay";
 };
+
+&usbphy2 {
+	status = "okay";
+};
+
+&combphy {
+	status = "okay";
+};
+
+&usb_dwc3 {
+	vbus-supply = <&usb3_vbus>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	hub_2_0: hub@1 {
+		compatible = "usb2109,2817";
+		reg = <0x1>;
+		vdd-supply = <&usb3_vhub>;
+		peer-hub = <&hub_3_0>;
+		reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
+	};
+
+	hub_3_0: hub@2 {
+		compatible = "usb2109,817";
+		reg = <0x1>;
+		vdd-supply = <&usb3_vhub>;
+		peer-hub = <&hub_2_0>;
+		reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
+	};
+};
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 61f5ca250ded0da7b91cd4bbd55a5574a89c6ab0..164244fdb49f5d50a8abadb7b7e478cccc828087 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -4,6 +4,8 @@
  */
 
 #include <dt-bindings/clock/spacemit,k1-syscon.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
 
 /dts-v1/;
 / {
@@ -346,6 +348,15 @@ soc {
 		dma-noncoherent;
 		ranges;
 
+		mbus0: dram-controller@0 {
+			reg = <0x0 0x00000000 0x0 0x80000000>;
+			reg-names = "dram";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
+			#interconnect-cells = <0>;
+		};
+
 		syscon_rcpu: system-controller@c0880000 {
 			compatible = "spacemit,k1-syscon-rcpu";
 			reg = <0x0 0xc0880000 0x0 0x2048>;
@@ -358,6 +369,64 @@ syscon_rcpu2: system-controller@c0888000 {
 			#reset-cells = <1>;
 		};
 
+		usb_dwc3: usb@c0a00000 {
+			compatible = "spacemit,k1-dwc3";
+			reg = <0x0 0xc0a00000 0x0 0x10000>;
+			clocks = <&syscon_apmu CLK_USB30>;
+			clock-names = "usbdrd30";
+			resets = <&syscon_apmu RESET_USB3_0>;
+			interrupt-parent = <&plic>;
+			interrupts = <125>;
+			interconnects = <&mbus0>;
+			interconnect-names = "dma-mem";
+			phys = <&usbphy2>, <&combphy PHY_TYPE_USB3>;
+			phy-names = "usb2-phy", "usb3-phy";
+			dr_mode = "host";
+			phy_type = "utmi";
+			snps,hsphy_interface = "utmi";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+			snps,dis_rxdet_inp3_quirk;
+			status = "disabled";
+		};
+
+		usbphy0: phy@c0940000 {
+			compatible = "spacemit,k1-usb2-phy";
+			reg = <0x0 0xc0940000 0x0 0x200>;
+			clocks = <&syscon_apmu CLK_USB_AXI>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usbphy1: phy@c09c0000 {
+			compatible = "spacemit,k1-usb2-phy";
+			reg = <0x0 0xc09c0000 0x0 0x200>;
+			clocks = <&syscon_apmu CLK_USB_P1>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usbphy2: phy@c0a30000 {
+			compatible = "spacemit,k1-usb2-phy";
+			reg = <0x0 0xc0a30000 0x0 0x200>;
+			clocks = <&syscon_apmu CLK_USB30>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		combphy: phy@c0b10000 {
+			compatible = "spacemit,k1-combphy";
+			reg = <0x0 0xc0b10000 0x0 0x800>,
+			      <0x0 0xd4282910 0x0 0x400>;
+			reg-names = "ctrl", "sel";
+			resets = <&syscon_apmu RESET_PCIE0>;
+			#phy-cells = <1>;
+			status = "disabled";
+		};
+
 		syscon_apbc: system-control@d4015000 {
 			compatible = "spacemit,k1-syscon-apbc";
 			reg = <0x0 0xd4015000 0x0 0x1000>;

-- 
2.49.0

Re: [PATCH v3 3/3] riscv: dts: spacemit: add usb3.0 support for K1

[Krzysztof Kozlowski]

On Sun, May 18, 2025 at 03:19:21AM GMT, Ze Huang wrote:
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index 61f5ca250ded0da7b91cd4bbd55a5574a89c6ab0..164244fdb49f5d50a8abadb7b7e478cccc828087 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -4,6 +4,8 @@
>   */
>  
>  #include <dt-bindings/clock/spacemit,k1-syscon.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/phy/phy.h>
>  
>  /dts-v1/;
>  / {
> @@ -346,6 +348,15 @@ soc {
>  		dma-noncoherent;
>  		ranges;
>  
> +		mbus0: dram-controller@0 {

Missing compatible.

> +			reg = <0x0 0x00000000 0x0 0x80000000>;
> +			reg-names = "dram";

Where are the bindings for this?

> +			#address-cells = <2>;
> +			#size-cells = <2>;

Why are these needed?

> +			dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
> +			#interconnect-cells = <0>;

No, you cannot just add any properties to any custom node. You need ABI
for all this.

> +		};
> +
>  		syscon_rcpu: system-controller@c0880000 {
>  			compatible = "spacemit,k1-syscon-rcpu";
>  			reg = <0x0 0xc0880000 0x0 0x2048>;
> @@ -358,6 +369,64 @@ syscon_rcpu2: system-controller@c0888000 {
>  			#reset-cells = <1>;
>  		};
>  
> +		usb_dwc3: usb@c0a00000 {
> +			compatible = "spacemit,k1-dwc3";
> +			reg = <0x0 0xc0a00000 0x0 0x10000>;
> +			clocks = <&syscon_apmu CLK_USB30>;
> +			clock-names = "usbdrd30";
> +			resets = <&syscon_apmu RESET_USB3_0>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <125>;
> +			interconnects = <&mbus0>;
> +			interconnect-names = "dma-mem";
> +			phys = <&usbphy2>, <&combphy PHY_TYPE_USB3>;
> +			phy-names = "usb2-phy", "usb3-phy";
> +			dr_mode = "host";

This does not look like property of the soc.

> +			phy_type = "utmi";
> +			snps,hsphy_interface = "utmi";
> +			snps,dis_enblslpm_quirk;
> +			snps,dis-u2-freeclk-exists-quirk;
> +			snps,dis-del-phy-power-chg-quirk;
> +			snps,dis_u2_susphy_quirk;
> +			snps,dis_u3_susphy_quirk;
> +			snps,dis_rxdet_inp3_quirk;
> +			status = "disabled";
> +		};
> +
> +		usbphy0: phy@c0940000 {
> +			compatible = "spacemit,k1-usb2-phy";
> +			reg = <0x0 0xc0940000 0x0 0x200>;
> +			clocks = <&syscon_apmu CLK_USB_AXI>;
> +			#phy-cells = <0>;
> +			status = "disabled";

What is missing here? Why is this node disabled?

Best regards,
Krzysztof

Re: [PATCH v3 3/3] riscv: dts: spacemit: add usb3.0 support for K1

[Ze Huang]

On Mon, May 19, 2025 at 11:37:30AM +0200, Krzysztof Kozlowski wrote:
> On Sun, May 18, 2025 at 03:19:21AM GMT, Ze Huang wrote:
> > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > index 61f5ca250ded0da7b91cd4bbd55a5574a89c6ab0..164244fdb49f5d50a8abadb7b7e478cccc828087 100644
> > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> > @@ -4,6 +4,8 @@
> >   */
> >  
> >  #include <dt-bindings/clock/spacemit,k1-syscon.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/phy/phy.h>
> >  
> >  /dts-v1/;
> >  / {
> > @@ -346,6 +348,15 @@ soc {
> >  		dma-noncoherent;
> >  		ranges;
> >  
> > +		mbus0: dram-controller@0 {
> 
> Missing compatible.
> 
> > +			reg = <0x0 0x00000000 0x0 0x80000000>;
> > +			reg-names = "dram";
> 
> Where are the bindings for this?
> 
> > +			#address-cells = <2>;
> > +			#size-cells = <2>;
> 
> Why are these needed?
> 

Will drop them

> > +			dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
> > +			#interconnect-cells = <0>;
> 
> No, you cannot just add any properties to any custom node. You need ABI
> for all this.
> 

Thanks for correcting, will create a binding for it.

> > +		};
> > +
> >  		syscon_rcpu: system-controller@c0880000 {
> >  			compatible = "spacemit,k1-syscon-rcpu";
> >  			reg = <0x0 0xc0880000 0x0 0x2048>;
> > @@ -358,6 +369,64 @@ syscon_rcpu2: system-controller@c0888000 {
> >  			#reset-cells = <1>;
> >  		};
> >  
> > +		usb_dwc3: usb@c0a00000 {
> > +			compatible = "spacemit,k1-dwc3";
> > +			reg = <0x0 0xc0a00000 0x0 0x10000>;
> > +			clocks = <&syscon_apmu CLK_USB30>;
> > +			clock-names = "usbdrd30";
> > +			resets = <&syscon_apmu RESET_USB3_0>;
> > +			interrupt-parent = <&plic>;
> > +			interrupts = <125>;
> > +			interconnects = <&mbus0>;
> > +			interconnect-names = "dma-mem";
> > +			phys = <&usbphy2>, <&combphy PHY_TYPE_USB3>;
> > +			phy-names = "usb2-phy", "usb3-phy";
> > +			dr_mode = "host";
> 
> This does not look like property of the soc.
> 

Will move `dr_mode` to board level

> > +			phy_type = "utmi";
> > +			snps,hsphy_interface = "utmi";
> > +			snps,dis_enblslpm_quirk;
> > +			snps,dis-u2-freeclk-exists-quirk;
> > +			snps,dis-del-phy-power-chg-quirk;
> > +			snps,dis_u2_susphy_quirk;
> > +			snps,dis_u3_susphy_quirk;
> > +			snps,dis_rxdet_inp3_quirk;
> > +			status = "disabled";
> > +		};
> > +
> > +		usbphy0: phy@c0940000 {
> > +			compatible = "spacemit,k1-usb2-phy";
> > +			reg = <0x0 0xc0940000 0x0 0x200>;
> > +			clocks = <&syscon_apmu CLK_USB_AXI>;
> > +			#phy-cells = <0>;
> > +			status = "disabled";
> 
> What is missing here? Why is this node disabled?
> 

There're three USB controllers on K1 [1]:
- A USB2.0 OTG
- A USB2.0 Host Only
- A USB3.0 with a USB2.0 DRD interface

usbphy0 is for USB2.0 OTG, and ushphy1 is for USB2.0 Host Only.
They're not supported yet.

Link: https://developer.spacemit.com/documentation?token=AjHDwrW78igAAEkiHracBI9HnTb#part5 [1]

> Best regards,
> Krzysztof
> 
> 
> 
>