[PATCH v3 0/9] Add support for i.MX94 DCIF

[PATCH v3 0/9] Add support for i.MX94 DCIF

[Laurentiu Palcu]

Hi,

This patch-set adds support for the i.MX94 Display Control Interface.
It depends on Peng Fan's DTS patch [1] that was not yet merged. Also, it
needs the BLK CTL changes [2] that I spinned off from v2 in a different
patchset.

Also, included in the patch-set are a few extra patches that the DCIF
driver depends on for functioning properly:
 * 1/9 - 3/9 : add support for i.MX94 to fsl-ldb driver. It also
			   contains a patch (2/9) from Liu Ying that was already reviewed
			   and was part of another patch-set ([3]), but was never merged;

v3:
 * Removed the BLK CTL patches and created a separate patch set [2] for them;
 * Collected r-b tags for 1/9, 2/9, 3/9 and 9/9;
 * Removed the DCIF QoS functionality until I find a better way to
   implement it through syscon. QoS functionality will be added in
   subsequent patches. Also, used devm_clk_bulk_get_all() and used
   dev_err_probe() as suggested;
 * Addressed Frank's and Krzysztof's comments on the DCIF bindings;
 * Addressed Frank's comments on dtsi and dts files;
 * Added a new binding patch, 6/9, for adding 'ldb' optional property to
   nxp,imx95-blk-ctl.yaml;

v2:
 * reworked the BLK_CTL patch and split in 2 to make it easier for
   review;
 * split the dts and dtsi patch in 2 separate ones;
 * addressed Frank's comments in DCIF driver;
 * addressed Rob's comments for the bindings files;
 * addressed a couple of checkpatch issues;

Thanks,
Laurentiu

[1] https://lkml.org/lkml/2025/7/7/84
[2] https://www.spinics.net/lists/kernel/msg5791546.html
[3] https://lkml.org/lkml/2024/11/14/262

Laurentiu Palcu (7):
  dt-bindings: display: fsl,ldb: Add i.MX94 LDB
  drm/bridge: fsl-ldb: Add support for i.MX94
  dt-bindings: display: imx: Add bindings for i.MX94 DCIF
  dt-bindings: clock: nxp,imx95-blk-ctl: Add optional ldb property
  arm64: dts: imx943: Add display pipeline nodes
  arm64: dts: imx943-evk: Add display support using IT6263
  MAINTAINERS: Add entry for i.MX94 DCIF driver

Liu Ying (1):
  drm/bridge: fsl-ldb: Get the next non-panel bridge

Sandor Yu (1):
  drm/imx: Add support for i.MX94 DCIF

 .../bindings/clock/nxp,imx95-blk-ctl.yaml     |   5 +
 .../bindings/display/bridge/fsl,ldb.yaml      |   2 +
 .../bindings/display/imx/nxp,imx94-dcif.yaml  |  82 +++
 MAINTAINERS                                   |   9 +
 arch/arm64/boot/dts/freescale/imx943-evk.dts  | 121 +++
 arch/arm64/boot/dts/freescale/imx943.dtsi     |  55 +-
 drivers/gpu/drm/bridge/fsl-ldb.c              |  47 +-
 drivers/gpu/drm/imx/Kconfig                   |   1 +
 drivers/gpu/drm/imx/Makefile                  |   1 +
 drivers/gpu/drm/imx/dcif/Kconfig              |  15 +
 drivers/gpu/drm/imx/dcif/Makefile             |   5 +
 drivers/gpu/drm/imx/dcif/dcif-crc.c           | 211 ++++++
 drivers/gpu/drm/imx/dcif/dcif-crc.h           |  52 ++
 drivers/gpu/drm/imx/dcif/dcif-crtc.c          | 694 ++++++++++++++++++
 drivers/gpu/drm/imx/dcif/dcif-drv.c           | 226 ++++++
 drivers/gpu/drm/imx/dcif/dcif-drv.h           |  84 +++
 drivers/gpu/drm/imx/dcif/dcif-kms.c           | 100 +++
 drivers/gpu/drm/imx/dcif/dcif-plane.c         | 269 +++++++
 drivers/gpu/drm/imx/dcif/dcif-reg.h           | 266 +++++++
 19 files changed, 2223 insertions(+), 22 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
 create mode 100644 drivers/gpu/drm/imx/dcif/Kconfig
 create mode 100644 drivers/gpu/drm/imx/dcif/Makefile
 create mode 100644 drivers/gpu/drm/imx/dcif/dcif-crc.c
 create mode 100644 drivers/gpu/drm/imx/dcif/dcif-crc.h
 create mode 100644 drivers/gpu/drm/imx/dcif/dcif-crtc.c
 create mode 100644 drivers/gpu/drm/imx/dcif/dcif-drv.c
 create mode 100644 drivers/gpu/drm/imx/dcif/dcif-drv.h
 create mode 100644 drivers/gpu/drm/imx/dcif/dcif-kms.c
 create mode 100644 drivers/gpu/drm/imx/dcif/dcif-plane.c
 create mode 100644 drivers/gpu/drm/imx/dcif/dcif-reg.h

-- 
2.49.0

[PATCH v3 1/9] dt-bindings: display: fsl,ldb: Add i.MX94 LDB

[Laurentiu Palcu]

i.MX94 has a single LVDS port and share similar LDB and LVDS control
registers as i.MX8MP and i.MX93.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
index 07388bf2b90df..a54b8f1478049 100644
--- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
@@ -20,6 +20,7 @@ properties:
       - fsl,imx6sx-ldb
       - fsl,imx8mp-ldb
       - fsl,imx93-ldb
+      - fsl,imx94-ldb
 
   clocks:
     maxItems: 1
@@ -68,6 +69,7 @@ allOf:
             enum:
               - fsl,imx6sx-ldb
               - fsl,imx93-ldb
+              - fsl,imx94-ldb
     then:
       properties:
         ports:
-- 
2.49.0

[PATCH v3 4/9] dt-bindings: display: imx: Add bindings for i.MX94 DCIF

[Laurentiu Palcu]

DCIF is the i.MX94 Display Controller Interface which is used to
drive a TFT LCD panel or connects to a display interface depending
on the chip configuration.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
 .../bindings/display/imx/nxp,imx94-dcif.yaml  | 82 +++++++++++++++++++
 1 file changed, 82 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml

diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
new file mode 100644
index 0000000000000..54419c589ef74
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2025 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/nxp,imx94-dcif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX94 Display Control Interface (DCIF)
+
+maintainers:
+  - Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
+
+description:
+  The Display Control Interface(DCIF) is a system master that fetches graphics
+  stored in memory and displays them on a TFT LCD panel or connects to a
+  display interface depending on the chip configuration.
+
+properties:
+  compatible:
+    const: nxp,imx94-dcif
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: CPU domain 0 (controlled by common registers group).
+      - description: CPU domain 1 (controlled by background layer registers group).
+      - description: CPU domain 2 (controlled by foreground layer registers group).
+
+  interrupt-names:
+    items:
+      - const: common
+      - const: bg_layer
+      - const: fg_layer
+
+  clocks:
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: apb
+      - const: axi
+      - const: pix
+
+  power-domains:
+    maxItems: 1
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    description: Display Pixel Interface(DPI) output port
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        display-controller@4b120000 {
+            compatible = "nxp,imx94-dcif";
+            reg = <0x0 0x4b120000 0x0 0x300000>;
+            interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+            interrupt-names = "common", "bg_layer", "fg_layer";
+            clocks = <&scmi_clk 69>, <&scmi_clk 70>, <&dispmix_csr 0>;
+            clock-names = "apb", "axi", "pix";
+            assigned-clocks = <&dispmix_csr 0>;
+            assigned-clock-parents = <&ldb_pll_pixel>;
+            power-domains = <&scmi_devpd 11>;
+
+            port {
+                dcif_out: endpoint {
+                    remote-endpoint = <&ldb_in>;
+                };
+            };
+        };
+    };
-- 
2.49.0

[PATCH v3 6/9] dt-bindings: clock: nxp,imx95-blk-ctl: Add optional ldb property

[Laurentiu Palcu]

Since the BLK CTL registers, like the LVDS CSR, can be used to control the
LVDS Display Bridge controllers, add optional 'ldb' property to handle
these use cases.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
 .../devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml         | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
index 27403b4c52d62..836004de4460f 100644
--- a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
+++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
@@ -39,6 +39,11 @@ properties:
       ID in its "clocks" phandle cell. See
       include/dt-bindings/clock/nxp,imx95-clock.h
 
+patternProperties:
+  "^ldb@[0-9a-f]+$":
+    type: object
+    $ref: /schemas/display/bridge/fsl,ldb.yaml#
+
 required:
   - compatible
   - reg
-- 
2.49.0

[PATCH v3 7/9] arm64: dts: imx943: Add display pipeline nodes

[Laurentiu Palcu]

Add display controller and LDB support in imx943.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
 arch/arm64/boot/dts/freescale/imx943.dtsi | 55 ++++++++++++++++++++++-
 1 file changed, 54 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
index 657c81b6016f2..70dec03c5608e 100644
--- a/arch/arm64/boot/dts/freescale/imx943.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
@@ -148,7 +148,7 @@ l3_cache: l3-cache {
 		};
 	};
 
-	clock-ldb-pll-div7 {
+	clock_ldb_pll_div7: clock-ldb-pll-div7 {
 		compatible = "fixed-factor-clock";
 		#clock-cells = <0>;
 		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
@@ -174,9 +174,62 @@ dispmix_csr: syscon@4b010000 {
 		lvds_csr: syscon@4b0c0000 {
 			compatible = "nxp,imx94-lvds-csr", "syscon";
 			reg = <0x0 0x4b0c0000 0x0 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
 			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
 			#clock-cells = <1>;
 			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
+
+			ldb: ldb@4 {
+				compatible = "fsl,imx94-ldb";
+				reg = <0x4 0x4>, <0x8 0x4>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg-names = "ldb", "lvds";
+				clocks = <&lvds_csr IMX94_CLK_DISPMIX_LVDS_CLK_GATE>;
+				clock-names = "ldb";
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						lvds_in: endpoint {
+							remote-endpoint = <&dcif_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+					};
+				};
+			};
+		};
+
+		dcif: display-controller@4b120000 {
+			compatible = "nxp,imx94-dcif";
+			reg = <0x0 0x4b120000 0x0 0x300000>;
+			interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "common", "bg_layer", "fg_layer";
+			clocks = <&scmi_clk IMX94_CLK_DISPAPB>,
+				 <&scmi_clk IMX94_CLK_DISPAXI>,
+				 <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
+			clock-names = "apb", "axi", "pix";
+			assigned-clocks = <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
+			assigned-clock-parents = <&clock_ldb_pll_div7>;
+			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
+			status = "disabled";
+
+			port {
+				dcif_out: endpoint {
+					remote-endpoint = <&lvds_in>;
+				};
+			};
 		};
 	};
 };
-- 
2.49.0

[PATCH v3 8/9] arm64: dts: imx943-evk: Add display support using IT6263

[Laurentiu Palcu]

The ITE IT6263 based NXP LVDS to HDMI converter can be attached to the
i.MX943 EVK board LVDS port using the mini-SAS connector. Since this is
the default configuration for the EVK, add support for it here.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
 arch/arm64/boot/dts/freescale/imx943-evk.dts | 121 +++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
index c8c3eff9df1a2..5900ff355abc2 100644
--- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
@@ -34,6 +34,18 @@ dmic: dmic {
 		#sound-dai-cells = <0>;
 	};
 
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		label = "hdmi";
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&it6263_out>;
+			};
+		};
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
 		off-on-delay-us = <12000>;
@@ -127,6 +139,115 @@ memory@80000000 {
 	};
 };
 
+&dcif {
+	status = "okay";
+};
+
+&ldb {
+	assigned-clocks = <&scmi_clk IMX94_CLK_LDBPLL_VCO>,
+			  <&scmi_clk IMX94_CLK_LDBPLL>;
+	assigned-clock-rates = <4158000000>, <1039500000>;
+	status = "okay";
+
+	ports {
+		port@1 {
+			lvds_out: endpoint {
+				remote-endpoint = <&it6263_in>;
+			};
+		};
+	};
+};
+
+&lpi2c3 {
+	clock-frequency = <400000>;
+	pinctrl-0 = <&pinctrl_lpi2c3>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	pca9548_i2c3: i2c-mux@77 {
+		compatible = "nxp,pca9548";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@2 {
+			reg = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@3 {
+			reg = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			lvds-to-hdmi-bridge@4c {
+				compatible = "ite,it6263";
+				reg = <0x4c>;
+				data-mapping = "jeida-24";
+				reset-gpios = <&pcal6416_i2c3_u171 8 GPIO_ACTIVE_HIGH>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						it6263_in: endpoint {
+							remote-endpoint = <&lvds_out>;
+						};
+					};
+
+					port@2 {
+						reg = <2>;
+
+						it6263_out: endpoint {
+							remote-endpoint = <&hdmi_connector_in>;
+						};
+					};
+				};
+			};
+		};
+
+		i2c@4 {
+			reg = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@5 {
+			reg = <5>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@6 {
+			reg = <6>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c@7 {
+			reg = <7>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
 &lpi2c3 {
 	clock-frequency = <400000>;
 	pinctrl-0 = <&pinctrl_lpi2c3>;
-- 
2.49.0

Re: [PATCH v3 4/9] dt-bindings: display: imx: Add bindings for i.MX94 DCIF

[Frank Li]

On Wed, Aug 06, 2025 at 06:05:11PM +0300, Laurentiu Palcu wrote:
> DCIF is the i.MX94 Display Controller Interface which is used to
> drive a TFT LCD panel or connects to a display interface depending
> on the chip configuration.

nit: wrap at 75 chars

>
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> ---
>  .../bindings/display/imx/nxp,imx94-dcif.yaml  | 82 +++++++++++++++++++
>  1 file changed, 82 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
> new file mode 100644
> index 0000000000000..54419c589ef74
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2025 NXP
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/nxp,imx94-dcif.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: i.MX94 Display Control Interface (DCIF)
> +
> +maintainers:
> +  - Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> +
> +description:
> +  The Display Control Interface(DCIF) is a system master that fetches graphics
> +  stored in memory and displays them on a TFT LCD panel or connects to a
> +  display interface depending on the chip configuration.
> +
> +properties:
> +  compatible:
> +    const: nxp,imx94-dcif
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    items:
> +      - description: CPU domain 0 (controlled by common registers group).
> +      - description: CPU domain 1 (controlled by background layer registers group).
> +      - description: CPU domain 2 (controlled by foreground layer registers group).
> +
> +  interrupt-names:
> +    items:
> +      - const: common
> +      - const: bg_layer
> +      - const: fg_layer
> +
> +  clocks:
> +    maxItems: 3
> +
> +  clock-names:
> +    items:
> +      - const: apb
> +      - const: axi
> +      - const: pix
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  port:
> +    $ref: /schemas/graph.yaml#/properties/port
> +    description: Display Pixel Interface(DPI) output port

I think need

    properties:
      endpoint:
        $ref: video-interfaces.yaml#
        unevaluatedProperties: false

Most likely need set

bus-width, hsync-active, vsync-active

Frank
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        display-controller@4b120000 {
> +            compatible = "nxp,imx94-dcif";
> +            reg = <0x0 0x4b120000 0x0 0x300000>;
> +            interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
> +            interrupt-names = "common", "bg_layer", "fg_layer";
> +            clocks = <&scmi_clk 69>, <&scmi_clk 70>, <&dispmix_csr 0>;
> +            clock-names = "apb", "axi", "pix";
> +            assigned-clocks = <&dispmix_csr 0>;
> +            assigned-clock-parents = <&ldb_pll_pixel>;
> +            power-domains = <&scmi_devpd 11>;
> +
> +            port {
> +                dcif_out: endpoint {
> +                    remote-endpoint = <&ldb_in>;
> +                };
> +            };
> +        };
> +    };
> --
> 2.49.0
>

Re: [PATCH v3 7/9] arm64: dts: imx943: Add display pipeline nodes

[Frank Li]

On Wed, Aug 06, 2025 at 06:05:14PM +0300, Laurentiu Palcu wrote:
> Add display controller and LDB support in imx943.
>
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  arch/arm64/boot/dts/freescale/imx943.dtsi | 55 ++++++++++++++++++++++-
>  1 file changed, 54 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> index 657c81b6016f2..70dec03c5608e 100644
> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
> @@ -148,7 +148,7 @@ l3_cache: l3-cache {
>  		};
>  	};
>
> -	clock-ldb-pll-div7 {
> +	clock_ldb_pll_div7: clock-ldb-pll-div7 {
>  		compatible = "fixed-factor-clock";
>  		#clock-cells = <0>;
>  		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
> @@ -174,9 +174,62 @@ dispmix_csr: syscon@4b010000 {
>  		lvds_csr: syscon@4b0c0000 {
>  			compatible = "nxp,imx94-lvds-csr", "syscon";
>  			reg = <0x0 0x4b0c0000 0x0 0x10000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
>  			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
>  			#clock-cells = <1>;
>  			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> +
> +			ldb: ldb@4 {
> +				compatible = "fsl,imx94-ldb";
> +				reg = <0x4 0x4>, <0x8 0x4>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg-names = "ldb", "lvds";
> +				clocks = <&lvds_csr IMX94_CLK_DISPMIX_LVDS_CLK_GATE>;
> +				clock-names = "ldb";
> +				status = "disabled";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						lvds_in: endpoint {
> +							remote-endpoint = <&dcif_out>;
> +						};
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +					};
> +				};
> +			};
> +		};
> +
> +		dcif: display-controller@4b120000 {
> +			compatible = "nxp,imx94-dcif";
> +			reg = <0x0 0x4b120000 0x0 0x300000>;
> +			interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "common", "bg_layer", "fg_layer";
> +			clocks = <&scmi_clk IMX94_CLK_DISPAPB>,
> +				 <&scmi_clk IMX94_CLK_DISPAXI>,
> +				 <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
> +			clock-names = "apb", "axi", "pix";
> +			assigned-clocks = <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
> +			assigned-clock-parents = <&clock_ldb_pll_div7>;
> +			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> +			status = "disabled";
> +
> +			port {
> +				dcif_out: endpoint {
> +					remote-endpoint = <&lvds_in>;
> +				};
> +			};
>  		};
>  	};
>  };
> --
> 2.49.0
>

Re: [PATCH v3 8/9] arm64: dts: imx943-evk: Add display support using IT6263

[Frank Li]

On Wed, Aug 06, 2025 at 06:05:15PM +0300, Laurentiu Palcu wrote:
> The ITE IT6263 based NXP LVDS to HDMI converter can be attached to the
> i.MX943 EVK board LVDS port using the mini-SAS connector. Since this is
> the default configuration for the EVK, add support for it here.
>
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
>  arch/arm64/boot/dts/freescale/imx943-evk.dts | 121 +++++++++++++++++++
>  1 file changed, 121 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> index c8c3eff9df1a2..5900ff355abc2 100644
> --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> @@ -34,6 +34,18 @@ dmic: dmic {
>  		#sound-dai-cells = <0>;
>  	};
>
> +	hdmi-connector {
> +		compatible = "hdmi-connector";
> +		label = "hdmi";
> +		type = "a";
> +
> +		port {
> +			hdmi_connector_in: endpoint {
> +				remote-endpoint = <&it6263_out>;
> +			};
> +		};
> +	};
> +
>  	reg_usdhc2_vmmc: regulator-usdhc2 {
>  		compatible = "regulator-fixed";
>  		off-on-delay-us = <12000>;
> @@ -127,6 +139,115 @@ memory@80000000 {
>  	};
>  };
>
> +&dcif {
> +	status = "okay";
> +};
> +
> +&ldb {
> +	assigned-clocks = <&scmi_clk IMX94_CLK_LDBPLL_VCO>,
> +			  <&scmi_clk IMX94_CLK_LDBPLL>;
> +	assigned-clock-rates = <4158000000>, <1039500000>;
> +	status = "okay";
> +
> +	ports {
> +		port@1 {
> +			lvds_out: endpoint {
> +				remote-endpoint = <&it6263_in>;
> +			};
> +		};
> +	};
> +};
> +
> +&lpi2c3 {
> +	clock-frequency = <400000>;
> +	pinctrl-0 = <&pinctrl_lpi2c3>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +
> +	pca9548_i2c3: i2c-mux@77 {
> +		compatible = "nxp,pca9548";
> +		reg = <0x77>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		i2c@0 {
> +			reg = <0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c@1 {
> +			reg = <1>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c@2 {
> +			reg = <2>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c@3 {
> +			reg = <3>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			lvds-to-hdmi-bridge@4c {
> +				compatible = "ite,it6263";
> +				reg = <0x4c>;
> +				data-mapping = "jeida-24";
> +				reset-gpios = <&pcal6416_i2c3_u171 8 GPIO_ACTIVE_HIGH>;
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						it6263_in: endpoint {
> +							remote-endpoint = <&lvds_out>;
> +						};
> +					};
> +
> +					port@2 {
> +						reg = <2>;
> +
> +						it6263_out: endpoint {
> +							remote-endpoint = <&hdmi_connector_in>;
> +						};
> +					};
> +				};
> +			};
> +		};
> +
> +		i2c@4 {
> +			reg = <4>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c@5 {
> +			reg = <5>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c@6 {
> +			reg = <6>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		i2c@7 {
> +			reg = <7>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +};
> +
>  &lpi2c3 {
>  	clock-frequency = <400000>;
>  	pinctrl-0 = <&pinctrl_lpi2c3>;
> --
> 2.49.0
>

Re: [PATCH v3 6/9] dt-bindings: clock: nxp,imx95-blk-ctl: Add optional ldb property

[Frank Li]

On Wed, Aug 06, 2025 at 06:05:13PM +0300, Laurentiu Palcu wrote:
> Since the BLK CTL registers, like the LVDS CSR, can be used to control the
> LVDS Display Bridge controllers, add optional 'ldb' property to handle
> these use cases.
>
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
>  .../devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml         | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> index 27403b4c52d62..836004de4460f 100644
> --- a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> @@ -39,6 +39,11 @@ properties:
>        ID in its "clocks" phandle cell. See
>        include/dt-bindings/clock/nxp,imx95-clock.h
>
> +patternProperties:
> +  "^ldb@[0-9a-f]+$":
> +    type: object
> +    $ref: /schemas/display/bridge/fsl,ldb.yaml#
> +
>  required:
>    - compatible
>    - reg
> --
> 2.49.0
>

Re: [PATCH v3 0/9] Add support for i.MX94 DCIF

[Krzysztof Kozlowski]

On Wed, Aug 06, 2025 at 06:05:07PM +0300, Laurentiu Palcu wrote:
> Hi,
> 
> This patch-set adds support for the i.MX94 Display Control Interface.
> It depends on Peng Fan's DTS patch [1] that was not yet merged. Also, it
> needs the BLK CTL changes [2] that I spinned off from v2 in a different
> patchset.
> 
> Also, included in the patch-set are a few extra patches that the DCIF
> driver depends on for functioning properly:
>  * 1/9 - 3/9 : add support for i.MX94 to fsl-ldb driver. It also
> 			   contains a patch (2/9) from Liu Ying that was already reviewed
> 			   and was part of another patch-set ([3]), but was never merged;
> 
> v3:
>  * Removed the BLK CTL patches and created a separate patch set [2] for them;
>  * Collected r-b tags for 1/9, 2/9, 3/9 and 9/9;
>  * Removed the DCIF QoS functionality until I find a better way to
>    implement it through syscon. QoS functionality will be added in
>    subsequent patches. Also, used devm_clk_bulk_get_all() and used
>    dev_err_probe() as suggested;
>  * Addressed Frank's and Krzysztof's comments on the DCIF bindings;

What exactly changed? I cannot find v2 of one of the patches, no lore
links here, so with incomplete changelog I say you make it difficult for
me to review it.

Best regards,
Krzysztof

Re: [PATCH v3 6/9] dt-bindings: clock: nxp,imx95-blk-ctl: Add optional ldb property

[Krzysztof Kozlowski]

On Wed, Aug 06, 2025 at 06:05:13PM +0300, Laurentiu Palcu wrote:
> Since the BLK CTL registers, like the LVDS CSR, can be used to control the
> LVDS Display Bridge controllers, add optional 'ldb' property to handle
> these use cases.

You did not add property here. You added child node.

I don't understand the rationale at all. How the registers could appear
in this hardware? What changed that registers were not there?

Why every device here has ldb child? Why camera has ldb?

Best regards,
Krzysztof

Re: [PATCH v3 7/9] arm64: dts: imx943: Add display pipeline nodes

[Krzysztof Kozlowski]

On Wed, Aug 06, 2025 at 06:05:14PM +0300, Laurentiu Palcu wrote:
> Add display controller and LDB support in imx943.
> 
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx943.dtsi | 55 ++++++++++++++++++++++-
>  1 file changed, 54 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> index 657c81b6016f2..70dec03c5608e 100644
> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
> @@ -148,7 +148,7 @@ l3_cache: l3-cache {
>  		};
>  	};
>  
> -	clock-ldb-pll-div7 {
> +	clock_ldb_pll_div7: clock-ldb-pll-div7 {
>  		compatible = "fixed-factor-clock";
>  		#clock-cells = <0>;
>  		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
> @@ -174,9 +174,62 @@ dispmix_csr: syscon@4b010000 {
>  		lvds_csr: syscon@4b0c0000 {
>  			compatible = "nxp,imx94-lvds-csr", "syscon";
>  			reg = <0x0 0x4b0c0000 0x0 0x10000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
>  			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
>  			#clock-cells = <1>;
>  			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> +
> +			ldb: ldb@4 {
> +				compatible = "fsl,imx94-ldb";
> +				reg = <0x4 0x4>, <0x8 0x4>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;

Why? There are no children with addressing. You never tested it because
this would easily be flagged by tools.

> +				reg-names = "ldb", "lvds";

Follow DTS coding style.

Best regards,
Krzysztof

Re: [PATCH v3 4/9] dt-bindings: display: imx: Add bindings for i.MX94 DCIF

[Laurentiu Palcu]

On Wed, Aug 06, 2025 at 11:27:44AM -0400, Frank Li wrote:
> On Wed, Aug 06, 2025 at 06:05:11PM +0300, Laurentiu Palcu wrote:
> > DCIF is the i.MX94 Display Controller Interface which is used to
> > drive a TFT LCD panel or connects to a display interface depending
> > on the chip configuration.
> 
> nit: wrap at 75 chars
> 
> >
> > Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> > ---
> >  .../bindings/display/imx/nxp,imx94-dcif.yaml  | 82 +++++++++++++++++++
> >  1 file changed, 82 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
> > new file mode 100644
> > index 0000000000000..54419c589ef74
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
> > @@ -0,0 +1,82 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +# Copyright 2025 NXP
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/imx/nxp,imx94-dcif.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: i.MX94 Display Control Interface (DCIF)
> > +
> > +maintainers:
> > +  - Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> > +
> > +description:
> > +  The Display Control Interface(DCIF) is a system master that fetches graphics
> > +  stored in memory and displays them on a TFT LCD panel or connects to a
> > +  display interface depending on the chip configuration.
> > +
> > +properties:
> > +  compatible:
> > +    const: nxp,imx94-dcif
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    items:
> > +      - description: CPU domain 0 (controlled by common registers group).
> > +      - description: CPU domain 1 (controlled by background layer registers group).
> > +      - description: CPU domain 2 (controlled by foreground layer registers group).
> > +
> > +  interrupt-names:
> > +    items:
> > +      - const: common
> > +      - const: bg_layer
> > +      - const: fg_layer
> > +
> > +  clocks:
> > +    maxItems: 3
> > +
> > +  clock-names:
> > +    items:
> > +      - const: apb
> > +      - const: axi
> > +      - const: pix
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  port:
> > +    $ref: /schemas/graph.yaml#/properties/port
> > +    description: Display Pixel Interface(DPI) output port
> 
> I think need
> 
>     properties:
>       endpoint:
>         $ref: video-interfaces.yaml#
>         unevaluatedProperties: false
> 
> Most likely need set
> 
> bus-width, hsync-active, vsync-active

We don't set these in DTS for DCIF. Hence, we don't need a specialiazed
binding for the endpoint. 

Laurentiu

> 
> Frank
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        display-controller@4b120000 {
> > +            compatible = "nxp,imx94-dcif";
> > +            reg = <0x0 0x4b120000 0x0 0x300000>;
> > +            interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
> > +                         <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
> > +                         <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
> > +            interrupt-names = "common", "bg_layer", "fg_layer";
> > +            clocks = <&scmi_clk 69>, <&scmi_clk 70>, <&dispmix_csr 0>;
> > +            clock-names = "apb", "axi", "pix";
> > +            assigned-clocks = <&dispmix_csr 0>;
> > +            assigned-clock-parents = <&ldb_pll_pixel>;
> > +            power-domains = <&scmi_devpd 11>;
> > +
> > +            port {
> > +                dcif_out: endpoint {
> > +                    remote-endpoint = <&ldb_in>;
> > +                };
> > +            };
> > +        };
> > +    };
> > --
> > 2.49.0
> >

Re: [PATCH v3 0/9] Add support for i.MX94 DCIF

[Laurentiu Palcu]

On Thu, Aug 07, 2025 at 09:26:55AM +0200, Krzysztof Kozlowski wrote:
> On Wed, Aug 06, 2025 at 06:05:07PM +0300, Laurentiu Palcu wrote:
> > Hi,
> > 
> > This patch-set adds support for the i.MX94 Display Control Interface.
> > It depends on Peng Fan's DTS patch [1] that was not yet merged. Also, it
> > needs the BLK CTL changes [2] that I spinned off from v2 in a different
> > patchset.
> > 
> > Also, included in the patch-set are a few extra patches that the DCIF
> > driver depends on for functioning properly:
> >  * 1/9 - 3/9 : add support for i.MX94 to fsl-ldb driver. It also
> > 			   contains a patch (2/9) from Liu Ying that was already reviewed
> > 			   and was part of another patch-set ([3]), but was never merged;
> > 
> > v3:
> >  * Removed the BLK CTL patches and created a separate patch set [2] for them;
> >  * Collected r-b tags for 1/9, 2/9, 3/9 and 9/9;
> >  * Removed the DCIF QoS functionality until I find a better way to
> >    implement it through syscon. QoS functionality will be added in
> >    subsequent patches. Also, used devm_clk_bulk_get_all() and used
> >    dev_err_probe() as suggested;
> >  * Addressed Frank's and Krzysztof's comments on the DCIF bindings;
> 
> What exactly changed?
I removed the redundant text in the description of interrupts, to make
the text fit on the same line with "description:" and, also, removed the
description items for clocks as they're pretty much explained by the
clock-names.

> I cannot find v2 of one of the patches, no lore links here, so with
> incomplete changelog I say you make it difficult for me to review it.
I'm sorry about that. :/ I am aware that removing or adding patches to
the set will most likely mess up with various tools... However, I stated
in the last line of the v3 changelog that 6/9 was new: "Added a new
binding patch, 6/9, for adding 'ldb' optional property to
nxp,imx95-blk-ctl.yaml".

Thanks,
Laurentiu

> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v3 6/9] dt-bindings: clock: nxp,imx95-blk-ctl: Add optional ldb property

[Laurentiu Palcu]

On Thu, Aug 07, 2025 at 09:29:05AM +0200, Krzysztof Kozlowski wrote:
> On Wed, Aug 06, 2025 at 06:05:13PM +0300, Laurentiu Palcu wrote:
> > Since the BLK CTL registers, like the LVDS CSR, can be used to control the
> > LVDS Display Bridge controllers, add optional 'ldb' property to handle
> > these use cases.
> 
> You did not add property here. You added child node.
Being under 'patternProperties', I thought it was appropriate to call it
a 'property'.

> 
> I don't understand the rationale at all. How the registers could appear
> in this hardware? What changed that registers were not there?
These are "configuration and status registers"(CSR). This syscon
device binding covers the CSRs for various subsystems. However, the CSR
register map is not the same for all CSR blocks.

> 
> Why every device here has ldb child? Why camera has ldb?
I guess I see what you mean... Would something like the following change
be acceptable?

---
if:
  properties:
    compatible:
      contains:
        const: nxp,imx94-lvds-csr
then:
  patternProperties:
    "^ldb@[0-9a-f]+$":
      type: object
      $ref: /schemas/display/bridge/fsl,ldb.yaml#
---

Thanks,
Laurentiu

> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v3 7/9] arm64: dts: imx943: Add display pipeline nodes

[Laurentiu Palcu]

On Thu, Aug 07, 2025 at 09:31:46AM +0200, Krzysztof Kozlowski wrote:
> On Wed, Aug 06, 2025 at 06:05:14PM +0300, Laurentiu Palcu wrote:
> > Add display controller and LDB support in imx943.
> > 
> > Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx943.dtsi | 55 ++++++++++++++++++++++-
> >  1 file changed, 54 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> > index 657c81b6016f2..70dec03c5608e 100644
> > --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
> > @@ -148,7 +148,7 @@ l3_cache: l3-cache {
> >  		};
> >  	};
> >  
> > -	clock-ldb-pll-div7 {
> > +	clock_ldb_pll_div7: clock-ldb-pll-div7 {
> >  		compatible = "fixed-factor-clock";
> >  		#clock-cells = <0>;
> >  		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
> > @@ -174,9 +174,62 @@ dispmix_csr: syscon@4b010000 {
> >  		lvds_csr: syscon@4b0c0000 {
> >  			compatible = "nxp,imx94-lvds-csr", "syscon";
> >  			reg = <0x0 0x4b0c0000 0x0 0x10000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> >  			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
> >  			#clock-cells = <1>;
> >  			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> > +
> > +			ldb: ldb@4 {
> > +				compatible = "fsl,imx94-ldb";
> > +				reg = <0x4 0x4>, <0x8 0x4>;
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> 
> Why? There are no children with addressing. You never tested it because
> this would easily be flagged by tools.
I tested it but I realized I only checked the DTB against the
nxp,imx94-dcif.yaml schema... :/ After adding the fsl,ldb.yaml, the
error popped up. Thanks for the heads-up.

> 
> > +				reg-names = "ldb", "lvds";
> 
> Follow DTS coding style.
If this is about 'reg-names' not being immediately after 'reg', then
this will be fixed since 'address-cells' and 'size-cells' will be
removed. Or is it something else?

Thanks,
Laurentiu

> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v3 6/9] dt-bindings: clock: nxp,imx95-blk-ctl: Add optional ldb property

[Krzysztof Kozlowski]

On 07/08/2025 14:35, Laurentiu Palcu wrote:
>>
>> Why every device here has ldb child? Why camera has ldb?
> I guess I see what you mean... Would something like the following change
> be acceptable?
> 
> ---
> if:
>   properties:
>     compatible:
>       contains:
>         const: nxp,imx94-lvds-csr
> then:
>   patternProperties:
>     "^ldb@[0-9a-f]+$":
>       type: object
>       $ref: /schemas/display/bridge/fsl,ldb.yaml#

In if:then: you only narrow the existence or constraints, so "if:not:
.... then: patternProperties:.... ^ldb@[0-9a-f]+$:false". The node
should still be defined in top level.

Best regards,
Krzysztof