Re: [PATCH v2 3/3] dt-bindings: mailbox: Add Renesas MFIS Mailbox

[Wolfram Sang <wsa+renesas@sang-engineering.com>]

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Hi Geert,

> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    mailbox@18842000  {
> > +        compatible = "rcar,mfis-mailbox-r8a78000", "rcar,mfis-mailbox-gen5";
> > +        reg = <0x18842000 0x8>;
> 
> This is an 8-byte block in the middle of the MFIS register space.
> Perhaps the DT bindings should describe the full MFIS block, and not
> just the mailbox part?

I think something in the middle. MFIS block also includes lock
registers. We have a BSP driver for these using the hw_spinlock
subsystem. That makes sense to me. Currently(tm), the register sets for
mailbox and spinlocks are seperated. We could make use of that or we go
anxious and start with an MFD right away.

Gen5 has 64 of these mailbox TX/RX register pairs. It has additional
message registers which should be included here IMHO. It is usually at
offset 0x40. I'd think we want to have one MFIS entry in DT and access
the mailbox we want with an index. Instead of having 64 entries in DT.
Well, actually, we would have two MFIS entries, there is one dedicated
to the SCP as well. It would add 32 more nodes if we describe every
mailbox independently.

Note: if we want Gen3/4 compatibility (I think we want that), we also
should go for one MFIS DT entry. On Gen5, every mailbox is 0x1000 apart
and has all needed registers in there. On Gen3, first the 8 communication
registers come and then the 8 message registers. So, they are not
seperated like on Gen5.

Happy hacking,

   Wolfram


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