[PATCH 0/3] arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support

[PATCH 0/3] arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support

[Sherry Sun]

This patch set adds usdhc1 support to enable M.2 SDIO WiFi on the
i.MX8MP EVK. The M.2 connector on this board can operate in both PCIe
and SDIO modes, and SDIO-based WLAN modules require proper power control
through the same M.2 WLAN enable line (W_DISABLE1 on pin 56).

The first two patches are preparation changes:
  - Patch 1 corrects the IOMUX configuration by enabling the pull-select
    bit for the M.2 regulator GPIO, ensuring that the weak pull-up is
    actually applied.
  - Patch 2 renames the regulator node from reg_pcie0 to reg_m2_wlan
    so that the same GPIO-controlled power rail can be cleanly reused by
    both PCIe- and SDIO-based WLAN modules.

The final patch enables usdhc1 and associated pinctrl settings needed
for SDIO WiFi operation on the M.2 connector.


Sherry Sun (3):
  arm64: dts: imx8mp-evk: Enable pull select bit for PCIe regulator GPIO
    (M.2 W_DISABLE1)
  arm64: dts: imx8mp-evk: Rename PCIe regulator to M.2 WLAN regulator
  arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support

 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 81 +++++++++++++++++---
 1 file changed, 70 insertions(+), 11 deletions(-)

-- 
2.37.1

[PATCH 1/3] arm64: dts: imx8mp-evk: Enable pull select bit for PCIe regulator GPIO (M.2 W_DISABLE1)

[Sherry Sun]

The current pin configuration for MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06
sets the weak pull-up but does not enable the pull select field.
Bit 8 in the IOMUX register must be set in order for the weak pull-up
to actually take effect.

Update the pinctrl setting from 0x40 to 0x140 to enable both the pull
select and the weak pull-up, ensuring the line behaves as expected.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 3f9b3fab8ac3..a1269c7a6cc2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -1069,7 +1069,7 @@ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x40
 
 	pinctrl_pcie0_reg: pcie0reggrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x40
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
 		>;
 	};
 
-- 
2.37.1

[PATCH 2/3] arm64: dts: imx8mp-evk: Rename PCIe regulator to M.2 WLAN regulator

[Sherry Sun]

The M.2 connector on the i.MX8MP EVK can support both PCIe and SDIO
modes. The existing regulator node reg_pcie0 is used to control the
pin56 W_DISABLE1 on the M.2 connector, which is also required by
SDIO-based WLAN modules.

To prepare for adding M.2 SDIO WiFi support, rename the regulator node
from reg_pcie0 to reg_m2_wlan and update its pinctrl and regulator
name accordingly. This allows the same GPIO-controlled power rail to be
reused for both PCIe and SDIO WLAN cards.

No functional behavior changes other than the rename.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 22 ++++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index a1269c7a6cc2..f86d6b428a47 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -134,11 +134,11 @@ reg_audio_pwr: regulator-audio-pwr {
 		enable-active-high;
 	};
 
-	reg_pcie0: regulator-pcie {
+	reg_m2_wlan: regulator-wlan {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_pcie0_reg>;
-		regulator-name = "MPCIE_3V3";
+		pinctrl-0 = <&pinctrl_reg_wlan>;
+		regulator-name = "WLAN_EN";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
@@ -764,8 +764,8 @@ &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	/* This property is deprecated, use reset-gpios from the Root Port node. */
 	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
-	vpcie-supply = <&reg_pcie0>;
-	vpcie3v3aux-supply = <&reg_pcie0>;
+	vpcie-supply = <&reg_m2_wlan>;
+	vpcie3v3aux-supply = <&reg_m2_wlan>;
 	supports-clkreq;
 	status = "okay";
 };
@@ -1067,12 +1067,6 @@ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x40
 		>;
 	};
 
-	pinctrl_pcie0_reg: pcie0reggrp {
-		fsl,pins = <
-			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
-		>;
-	};
-
 	pinctrl_pdm: pdmgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK		0xd6
@@ -1119,6 +1113,12 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
 		>;
 	};
 
+	pinctrl_reg_wlan: regwlangrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
-- 
2.37.1

[PATCH 3/3] arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support

[Sherry Sun]

Add usdhc1 to support M.2 SDIO WiFi on i.MX8MP EVK board.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 59 ++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index f86d6b428a47..0b45ff73a5a9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -250,6 +250,13 @@ cpu {
 		};
 	};
 
+	usdhc1_pwrseq: usdhc1_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc1_pwrseq>;
+		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+	};
+
 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -863,6 +870,19 @@ &uart3 {
 	status = "okay";
 };
 
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	keep-power-in-suspend;
+	non-removable;
+	wakeup-source;
+	mmc-pwrseq = <&usdhc1_pwrseq>;
+	vmmc-supply = <&reg_m2_wlan>;
+	status = "okay";
+};
+
 &usdhc2 {
 	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 	assigned-clock-rates = <400000000>;
@@ -1169,6 +1189,45 @@ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140
 		>;
 	};
 
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
+			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
+			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
+			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
+			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
+			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
+		>;
+	};
+
+	pinctrl_usdhc1_pwrseq: usdhc1pwrseq {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10	0x140
+		>;
+	};
+
 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
-- 
2.37.1

Re: [PATCH 1/3] arm64: dts: imx8mp-evk: Enable pull select bit for PCIe regulator GPIO (M.2 W_DISABLE1)

[Frank Li]

On Wed, Feb 04, 2026 at 10:32:02AM +0800, Sherry Sun wrote:
> The current pin configuration for MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06
> sets the weak pull-up but does not enable the pull select field.
> Bit 8 in the IOMUX register must be set in order for the weak pull-up
> to actually take effect.
>
> Update the pinctrl setting from 0x40 to 0x140 to enable both the pull
> select and the weak pull-up, ensuring the line behaves as expected.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---

Add fixes tag

Frank
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index 3f9b3fab8ac3..a1269c7a6cc2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -1069,7 +1069,7 @@ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x40
>
>  	pinctrl_pcie0_reg: pcie0reggrp {
>  		fsl,pins = <
> -			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x40
> +			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
>  		>;
>  	};
>
> --
> 2.37.1
>

Re: [PATCH 2/3] arm64: dts: imx8mp-evk: Rename PCIe regulator to M.2 WLAN regulator

[Frank Li]

On Wed, Feb 04, 2026 at 10:32:03AM +0800, Sherry Sun wrote:
> The M.2 connector on the i.MX8MP EVK can support both PCIe and SDIO
> modes. The existing regulator node reg_pcie0 is used to control the
> pin56 W_DISABLE1 on the M.2 connector, which is also required by
> SDIO-based WLAN modules.
>
> To prepare for adding M.2 SDIO WiFi support, rename the regulator node
> from reg_pcie0 to reg_m2_wlan and update its pinctrl and regulator
> name accordingly. This allows the same GPIO-controlled power rail to be
> reused for both PCIe and SDIO WLAN cards.
>
> No functional behavior changes other than the rename.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 22 ++++++++++----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index a1269c7a6cc2..f86d6b428a47 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -134,11 +134,11 @@ reg_audio_pwr: regulator-audio-pwr {
>  		enable-active-high;
>  	};
>
> -	reg_pcie0: regulator-pcie {
> +	reg_m2_wlan: regulator-wlan {

Needn't complex rename, just add second label

reg_m2_wlan: reg_pcie0: regulator-pcie {

Frank

>  		compatible = "regulator-fixed";
>  		pinctrl-names = "default";
> -		pinctrl-0 = <&pinctrl_pcie0_reg>;
> -		regulator-name = "MPCIE_3V3";
> +		pinctrl-0 = <&pinctrl_reg_wlan>;
> +		regulator-name = "WLAN_EN";
>  		regulator-min-microvolt = <3300000>;
>  		regulator-max-microvolt = <3300000>;
>  		gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
> @@ -764,8 +764,8 @@ &pcie0 {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	/* This property is deprecated, use reset-gpios from the Root Port node. */
>  	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
> -	vpcie-supply = <&reg_pcie0>;
> -	vpcie3v3aux-supply = <&reg_pcie0>;
> +	vpcie-supply = <&reg_m2_wlan>;
> +	vpcie3v3aux-supply = <&reg_m2_wlan>;
>  	supports-clkreq;
>  	status = "okay";
>  };
> @@ -1067,12 +1067,6 @@ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07	0x40
>  		>;
>  	};
>
> -	pinctrl_pcie0_reg: pcie0reggrp {
> -		fsl,pins = <
> -			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
> -		>;
> -	};
> -
>  	pinctrl_pdm: pdmgrp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK		0xd6
> @@ -1119,6 +1113,12 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
>  		>;
>  	};
>
> +	pinctrl_reg_wlan: regwlangrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
> +		>;
> +	};
> +
>  	pinctrl_uart1: uart1grp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
> --
> 2.37.1
>

Re: [PATCH 3/3] arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support

[Frank Li]

On Wed, Feb 04, 2026 at 10:32:04AM +0800, Sherry Sun wrote:
> Add usdhc1 to support M.2 SDIO WiFi on i.MX8MP EVK board.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---

If prevous patch just add label, reg_m2_wlan, you can squash to this one.

Frank
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 59 ++++++++++++++++++++
>  1 file changed, 59 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index f86d6b428a47..0b45ff73a5a9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -250,6 +250,13 @@ cpu {
>  		};
>  	};
>
> +	usdhc1_pwrseq: usdhc1_pwrseq {
> +		compatible = "mmc-pwrseq-simple";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_usdhc1_pwrseq>;
> +		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
> +	};
> +
>  	reserved-memory {
>  		#address-cells = <2>;
>  		#size-cells = <2>;
> @@ -863,6 +870,19 @@ &uart3 {
>  	status = "okay";
>  };
>
> +&usdhc1 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc1>;
> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> +	keep-power-in-suspend;
> +	non-removable;
> +	wakeup-source;
> +	mmc-pwrseq = <&usdhc1_pwrseq>;
> +	vmmc-supply = <&reg_m2_wlan>;
> +	status = "okay";
> +};
> +
>  &usdhc2 {
>  	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
>  	assigned-clock-rates = <400000000>;
> @@ -1169,6 +1189,45 @@ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140
>  		>;
>  	};
>
> +	pinctrl_usdhc1: usdhc1grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
> +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
> +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
> +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
> +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
> +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
> +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
> +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
> +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
> +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
> +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
> +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
> +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
> +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
> +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
> +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_pwrseq: usdhc1pwrseq {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10	0x140
> +		>;
> +	};
> +
>  	pinctrl_usdhc2: usdhc2grp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
> --
> 2.37.1
>

RE: [PATCH 1/3] arm64: dts: imx8mp-evk: Enable pull select bit for PCIe regulator GPIO (M.2 W_DISABLE1)

[Sherry Sun]

> On Wed, Feb 04, 2026 at 10:32:02AM +0800, Sherry Sun wrote:
> > The current pin configuration for
> MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06
> > sets the weak pull-up but does not enable the pull select field.
> > Bit 8 in the IOMUX register must be set in order for the weak pull-up
> > to actually take effect.
> >
> > Update the pinctrl setting from 0x40 to 0x140 to enable both the pull
> > select and the weak pull-up, ensuring the line behaves as expected.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> 
> Add fixes tag

Ok. Will add in V2. Thanks! 

Best Regards
Sherry
> 
> Frank
> >  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > index 3f9b3fab8ac3..a1269c7a6cc2 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > @@ -1069,7 +1069,7 @@ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07
> 	0x40
> >
> >  	pinctrl_pcie0_reg: pcie0reggrp {
> >  		fsl,pins = <
> > -			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x40
> > +			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x140
> >  		>;
> >  	};
> >
> > --
> > 2.37.1
> >

RE: [PATCH 3/3] arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support

[Sherry Sun]

> On Wed, Feb 04, 2026 at 10:32:04AM +0800, Sherry Sun wrote:
> > Add usdhc1 to support M.2 SDIO WiFi on i.MX8MP EVK board.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> 
> If prevous patch just add label, reg_m2_wlan, you can squash to this one.

Thanks, will try this method.

Best Regards
Sherry

> 
> Frank
> >  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 59
> ++++++++++++++++++++
> >  1 file changed, 59 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > index f86d6b428a47..0b45ff73a5a9 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > @@ -250,6 +250,13 @@ cpu {
> >  		};
> >  	};
> >
> > +	usdhc1_pwrseq: usdhc1_pwrseq {
> > +		compatible = "mmc-pwrseq-simple";
> > +		pinctrl-names = "default";
> > +		pinctrl-0 = <&pinctrl_usdhc1_pwrseq>;
> > +		reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
> > +	};
> > +
> >  	reserved-memory {
> >  		#address-cells = <2>;
> >  		#size-cells = <2>;
> > @@ -863,6 +870,19 @@ &uart3 {
> >  	status = "okay";
> >  };
> >
> > +&usdhc1 {
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +	pinctrl-0 = <&pinctrl_usdhc1>;
> > +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> > +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> > +	keep-power-in-suspend;
> > +	non-removable;
> > +	wakeup-source;
> > +	mmc-pwrseq = <&usdhc1_pwrseq>;
> > +	vmmc-supply = <&reg_m2_wlan>;
> > +	status = "okay";
> > +};
> > +
> >  &usdhc2 {
> >  	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
> >  	assigned-clock-rates = <400000000>;
> > @@ -1169,6 +1189,45 @@
> MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140
> >  		>;
> >  	};
> >
> > +	pinctrl_usdhc1: usdhc1grp {
> > +		fsl,pins = <
> > +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
> > +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
> > +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0
> 	0x1d0
> > +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1
> 	0x1d0
> > +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2
> 	0x1d0
> > +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3
> 	0x1d0
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> > +		fsl,pins = <
> > +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
> > +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
> > +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0
> 	0x1d4
> > +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1
> 	0x1d4
> > +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2
> 	0x1d4
> > +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3
> 	0x1d4
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> > +		fsl,pins = <
> > +			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
> > +			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
> > +			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0
> 	0x1d6
> > +			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1
> 	0x1d6
> > +			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2
> 	0x1d6
> > +			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3
> 	0x1d6
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1_pwrseq: usdhc1pwrseq {
> > +		fsl,pins = <
> > +			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10	0x140
> > +		>;
> > +	};
> > +
> >  	pinctrl_usdhc2: usdhc2grp {
> >  		fsl,pins = <
> >  			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
> > --
> > 2.37.1
> >