[PATCH v2 08/28] dt-bindings: gpu: mali-gen5-am: Add Mali 5th-Gen AM schema

[PATCH v2 08/28] dt-bindings: gpu: mali-gen5-am: Add Mali 5th-Gen AM schema

[Karunika Choo]

Add a separate device-tree schema for Mali 5th-Gen AM GPUs.

AM_GOVERNOR controls GPU frequency. The GPU node does not accept OPP,
cooling or GPU supply properties.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v2:
- Move arm,mali-gen5-am support from arm,mali-valhall-csf.yaml to a
  separate arm,mali-gen5-am.yaml schema.
- Move the AM GPU example to the new schema and add the interrupt
  binding headers.
- Add the new schema to the Panthor MAINTAINERS entry.

 .../bindings/gpu/arm,mali-gen5-am.yaml        | 90 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 91 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
new file mode 100644
index 0000000000000..6349888e1ae2a
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali 5th Gen AM GPU
+
+maintainers:
+  - Liviu Dudau <liviu.dudau@arm.com>
+  - Boris Brezillon <boris.brezillon@collabora.com>
+
+properties:
+  $nodename:
+    pattern: '^gpu@[a-f0-9]+$'
+
+  compatible:
+    const: arm,mali-gen5-am
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Job interrupt
+      - description: MMU interrupt
+      - description: GPU interrupt
+
+  interrupt-names:
+    items:
+      - const: job
+      - const: mmu
+      - const: gpu
+
+  clocks:
+    minItems: 1
+    maxItems: 3
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: core
+      - enum:
+          - coregroup
+          - stacks
+      - const: stacks
+
+  nvmem-cells:
+    items:
+      - description: bitmask of functional shader cores
+
+  nvmem-cell-names:
+    items:
+      - const: shader-present
+
+  power-domains:
+    minItems: 1
+    maxItems: 5
+
+  power-domain-names:
+    minItems: 1
+    maxItems: 5
+
+  dma-coherent: true
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    gpu@100000 {
+        compatible = "arm,mali-gen5-am";
+        reg = <0x100000 0x480000>;
+        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>,
+                     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>,
+                     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>;
+        interrupt-names = "job", "mmu", "gpu";
+        clocks = <&gpu_clock 0>, <&gpu_clock 1>, <&gpu_clock 2>;
+        clock-names = "core", "coregroup", "stacks";
+    };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 1c3aec082b0ab..bdf3cc1044c3e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2400,6 +2400,7 @@ M:	Liviu Dudau <liviu.dudau@arm.com>
 L:	dri-devel@lists.freedesktop.org
 S:	Supported
 T:	git https://gitlab.freedesktop.org/drm/misc/kernel.git
+F:	Documentation/devicetree/bindings/gpu/arm,mali-gen5-am*.yaml
 F:	Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
 F:	drivers/gpu/drm/ci/xfails/panthor*
 F:	drivers/gpu/drm/panthor/
-- 
2.43.0

Re: [PATCH v2 08/28] dt-bindings: gpu: mali-gen5-am: Add Mali 5th-Gen AM schema

[Krzysztof Kozlowski]

On Tue, Nov 10, 2026 at 03:38:29PM +0000, Karunika Choo wrote:
> Add a separate device-tree schema for Mali 5th-Gen AM GPUs.
> 
> AM_GOVERNOR controls GPU frequency. The GPU node does not accept OPP,
> cooling or GPU supply properties.
> 
> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
> ---
> v2:
> - Move arm,mali-gen5-am support from arm,mali-valhall-csf.yaml to a
>   separate arm,mali-gen5-am.yaml schema.
> - Move the AM GPU example to the new schema and add the interrupt
>   binding headers.
> - Add the new schema to the Panthor MAINTAINERS entry.
> 
>  .../bindings/gpu/arm,mali-gen5-am.yaml        | 90 +++++++++++++++++++
>  MAINTAINERS                                   |  1 +
>  2 files changed, 91 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
> 
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
> new file mode 100644
> index 0000000000000..6349888e1ae2a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARM Mali 5th Gen AM GPU
> +
> +maintainers:
> +  - Liviu Dudau <liviu.dudau@arm.com>
> +  - Boris Brezillon <boris.brezillon@collabora.com>
> +
> +properties:
> +  $nodename:
> +    pattern: '^gpu@[a-f0-9]+$'

Same comments as last time.

> +
> +  compatible:
> +    const: arm,mali-gen5-am

Same comments as last time. Seems like you just ignore review, so I will
finish here.

Respond to review. Dropping from DT patchwork.

Best regards,
Krzysztof

Re: [PATCH v2 08/28] dt-bindings: gpu: mali-gen5-am: Add Mali 5th-Gen AM schema

[Karunika Choo]

On 11/11/2026 08:33, Krzysztof Kozlowski wrote:
> On Tue, Nov 10, 2026 at 03:38:29PM +0000, Karunika Choo wrote:
>> Add a separate device-tree schema for Mali 5th-Gen AM GPUs.
>>
>> AM_GOVERNOR controls GPU frequency. The GPU node does not accept OPP,
>> cooling or GPU supply properties.
>>
>> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
>> ---
>> v2:
>> - Move arm,mali-gen5-am support from arm,mali-valhall-csf.yaml to a
>>   separate arm,mali-gen5-am.yaml schema.
>> - Move the AM GPU example to the new schema and add the interrupt
>>   binding headers.
>> - Add the new schema to the Panthor MAINTAINERS entry.
>>
>>  .../bindings/gpu/arm,mali-gen5-am.yaml        | 90 +++++++++++++++++++
>>  MAINTAINERS                                   |  1 +
>>  2 files changed, 91 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
>> new file mode 100644
>> index 0000000000000..6349888e1ae2a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
>> @@ -0,0 +1,90 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: ARM Mali 5th Gen AM GPU
>> +
>> +maintainers:
>> +  - Liviu Dudau <liviu.dudau@arm.com>
>> +  - Boris Brezillon <boris.brezillon@collabora.com>
>> +
>> +properties:
>> +  $nodename:
>> +    pattern: '^gpu@[a-f0-9]+$'
> 
> Same comments as last time.

Sorry, do you mean that 'gpu' not generic enough?

>> +
>> +  compatible:
>> +    const: arm,mali-gen5-am
> 
> Same comments as last time. Seems like you just ignore review, so I will
> finish here.
> 

Hi, we are trying to provide initial support for v15. The vendor 
identifiers will be added once there is an available device.

> Respond to review. Dropping from DT patchwork.
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v2 08/28] dt-bindings: gpu: mali-gen5-am: Add Mali 5th-Gen AM schema

[Krzysztof Kozlowski]

On 11/11/2026 11:32, Karunika Choo wrote:
> On 11/11/2026 08:33, Krzysztof Kozlowski wrote:
>> On Tue, Nov 10, 2026 at 03:38:29PM +0000, Karunika Choo wrote:
>>> Add a separate device-tree schema for Mali 5th-Gen AM GPUs.
>>>
>>> AM_GOVERNOR controls GPU frequency. The GPU node does not accept OPP,
>>> cooling or GPU supply properties.
>>>
>>> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
>>> ---
>>> v2:
>>> - Move arm,mali-gen5-am support from arm,mali-valhall-csf.yaml to a
>>>   separate arm,mali-gen5-am.yaml schema.
>>> - Move the AM GPU example to the new schema and add the interrupt
>>>   binding headers.
>>> - Add the new schema to the Panthor MAINTAINERS entry.
>>>
>>>  .../bindings/gpu/arm,mali-gen5-am.yaml        | 90 +++++++++++++++++++
>>>  MAINTAINERS                                   |  1 +
>>>  2 files changed, 91 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
>>> new file mode 100644
>>> index 0000000000000..6349888e1ae2a
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
>>> @@ -0,0 +1,90 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: ARM Mali 5th Gen AM GPU
>>> +
>>> +maintainers:
>>> +  - Liviu Dudau <liviu.dudau@arm.com>
>>> +  - Boris Brezillon <boris.brezillon@collabora.com>
>>> +
>>> +properties:
>>> +  $nodename:
>>> +    pattern: '^gpu@[a-f0-9]+$'
>>
>> Same comments as last time.
> 
> Sorry, do you mean that 'gpu' not generic enough?

I asked to drop the node name completely.

> 
>>> +
>>> +  compatible:
>>> +    const: arm,mali-gen5-am
>>
>> Same comments as last time. Seems like you just ignore review, so I will
>> finish here.
>>
> 
> Hi, we are trying to provide initial support for v15. The vendor 
> identifiers will be added once there is an available device.
> 

So how can this initial support be run? Which board has it? I received
only three patches of entire thread, but if there was DTS I would be
cc-ed. I can't find such patch.

Best regards,
Krzysztof

Re: [PATCH v2 08/28] dt-bindings: gpu: mali-gen5-am: Add Mali 5th-Gen AM schema

[Karunika Choo]

On 11/11/2026 10:41, Krzysztof Kozlowski wrote:
> On 11/11/2026 11:32, Karunika Choo wrote:
>> On 11/11/2026 08:33, Krzysztof Kozlowski wrote:
>>> On Tue, Nov 10, 2026 at 03:38:29PM +0000, Karunika Choo wrote:
>>>> Add a separate device-tree schema for Mali 5th-Gen AM GPUs.
>>>>
>>>> AM_GOVERNOR controls GPU frequency. The GPU node does not accept OPP,
>>>> cooling or GPU supply properties.
>>>>
>>>> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
>>>> ---
>>>> v2:
>>>> - Move arm,mali-gen5-am support from arm,mali-valhall-csf.yaml to a
>>>>   separate arm,mali-gen5-am.yaml schema.
>>>> - Move the AM GPU example to the new schema and add the interrupt
>>>>   binding headers.
>>>> - Add the new schema to the Panthor MAINTAINERS entry.
>>>>
>>>>  .../bindings/gpu/arm,mali-gen5-am.yaml        | 90 +++++++++++++++++++
>>>>  MAINTAINERS                                   |  1 +
>>>>  2 files changed, 91 insertions(+)
>>>>  create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
>>>> new file mode 100644
>>>> index 0000000000000..6349888e1ae2a
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
>>>> @@ -0,0 +1,90 @@
>>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: ARM Mali 5th Gen AM GPU
>>>> +
>>>> +maintainers:
>>>> +  - Liviu Dudau <liviu.dudau@arm.com>
>>>> +  - Boris Brezillon <boris.brezillon@collabora.com>
>>>> +
>>>> +properties:
>>>> +  $nodename:
>>>> +    pattern: '^gpu@[a-f0-9]+$'
>>>
>>> Same comments as last time.
>>
>> Sorry, do you mean that 'gpu' not generic enough?
> 
> I asked to drop the node name completely.
> 

ah! Understood. Will do that in v3.

>>
>>>> +
>>>> +  compatible:
>>>> +    const: arm,mali-gen5-am
>>>
>>> Same comments as last time. Seems like you just ignore review, so I will
>>> finish here.
>>>
>>
>> Hi, we are trying to provide initial support for v15. The vendor 
>> identifiers will be added once there is an available device.
>>
> 
> So how can this initial support be run? Which board has it? I received
> only three patches of entire thread, but if there was DTS I would be
> cc-ed. I can't find such patch.

Apologies for the trouble. This was tested on internal FPGAs, but let
me try to see if I can add a representative DTS for one of our publicly
available FVP platforms in v3.

> 
> Best regards,
> Krzysztof

Re: [PATCH v2 08/28] dt-bindings: gpu: mali-gen5-am: Add Mali 5th-Gen AM schema

[Krzysztof Kozlowski]

On 11/11/2026 12:04, Karunika Choo wrote:
> On 11/11/2026 10:41, Krzysztof Kozlowski wrote:
>> On 11/11/2026 11:32, Karunika Choo wrote:
>>> On 11/11/2026 08:33, Krzysztof Kozlowski wrote:
>>>> On Tue, Nov 10, 2026 at 03:38:29PM +0000, Karunika Choo wrote:
>>>>> Add a separate device-tree schema for Mali 5th-Gen AM GPUs.
>>>>>
>>>>> AM_GOVERNOR controls GPU frequency. The GPU node does not accept OPP,
>>>>> cooling or GPU supply properties.
>>>>>
>>>>> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
>>>>> ---
>>>>> v2:
>>>>> - Move arm,mali-gen5-am support from arm,mali-valhall-csf.yaml to a
>>>>>   separate arm,mali-gen5-am.yaml schema.
>>>>> - Move the AM GPU example to the new schema and add the interrupt
>>>>>   binding headers.
>>>>> - Add the new schema to the Panthor MAINTAINERS entry.
>>>>>
>>>>>  .../bindings/gpu/arm,mali-gen5-am.yaml        | 90 +++++++++++++++++++
>>>>>  MAINTAINERS                                   |  1 +
>>>>>  2 files changed, 91 insertions(+)
>>>>>  create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
>>>>> new file mode 100644
>>>>> index 0000000000000..6349888e1ae2a
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am.yaml
>>>>> @@ -0,0 +1,90 @@
>>>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: ARM Mali 5th Gen AM GPU
>>>>> +
>>>>> +maintainers:
>>>>> +  - Liviu Dudau <liviu.dudau@arm.com>
>>>>> +  - Boris Brezillon <boris.brezillon@collabora.com>
>>>>> +
>>>>> +properties:
>>>>> +  $nodename:
>>>>> +    pattern: '^gpu@[a-f0-9]+$'
>>>>
>>>> Same comments as last time.
>>>
>>> Sorry, do you mean that 'gpu' not generic enough?
>>
>> I asked to drop the node name completely.
>>
> 
> ah! Understood. Will do that in v3.
> 
>>>
>>>>> +
>>>>> +  compatible:
>>>>> +    const: arm,mali-gen5-am
>>>>
>>>> Same comments as last time. Seems like you just ignore review, so I will
>>>> finish here.
>>>>
>>>
>>> Hi, we are trying to provide initial support for v15. The vendor 
>>> identifiers will be added once there is an available device.
>>>
>>
>> So how can this initial support be run? Which board has it? I received
>> only three patches of entire thread, but if there was DTS I would be
>> cc-ed. I can't find such patch.
> 
> Apologies for the trouble. This was tested on internal FPGAs, but let
> me try to see if I can add a representative DTS for one of our publicly
> available FVP platforms in v3.

So it cannot run on its own, because internal FPGA is a not a complete
and final system. I assume you need some SoC integration, so you need a
front compatible. If it is unknown, then it has to be {} (see other
cases how we represented unknown integration).

Best regards,
Krzysztof

[PATCH v2 11/28] dt-bindings: gpu: panthor: Document AM system bindings

[Karunika Choo]

Mali 5th-Gen AM GPUs expose an AM_SYSTEM block for GPU-wide control and
the AM_ASSIGN block for HW resource assignment outside the GPU
job submission register window.

Document the system node compatible, register and interrupt resources,
GPU clock, and assignment properties for HW resource assignment.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v2:
- Add an optional AM_ASSIGN register range. Require this range when the
  assignments node is present.
- Describe resource-group assignments for AXI buses, partitions, slices
  and access windows on partition-capable GPUs.
- Allow gpu-arbitration child nodes and the #address-cells, #size-cells
  and ranges properties.
- Remove the panthor-system node-name restriction.
- Remove gpu-supply from the schema and example.
- Add an example with assignments for partition-capable GPU with four
  resource groups.
- Move the MAINTAINERS update to the GPU schema patch.

 .../bindings/gpu/arm,mali-gen5-am-system.yaml | 196 ++++++++++++++++++
 1 file changed, 196 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
new file mode 100644
index 0000000000000..9e0477b8b723a
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
@@ -0,0 +1,196 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright 2026 ARM Limited. All rights reserved.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am-system.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali 5th-Gen GPU System Device
+
+maintainers:
+  - Liviu Dudau <liviu.dudau@arm.com>
+  - Boris Brezillon <boris.brezillon@collabora.com>
+
+properties:
+  compatible:
+    items:
+      - const: arm,mali-gen5-am-system
+
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  reg-names:
+    minItems: 1
+    items:
+      - const: system
+      - const: assign
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  dma-coherent: true
+
+  "#address-cells": true
+
+  "#size-cells": true
+
+  ranges: true
+
+  assignments:
+    type: object
+    additionalProperties: false
+    description:
+      Resource group HW resource assignment. Only valid for partition-capable
+      GPUs.
+
+    properties:
+      "#address-cells":
+        const: 1
+      "#size-cells":
+        const: 0
+
+    required:
+      - "#address-cells"
+      - "#size-cells"
+
+    patternProperties:
+      "^resource-group@[0-3]$":
+        type: object
+        additionalProperties: false
+
+        properties:
+          reg:
+            items:
+              - maximum: 3
+            description: Resource group number.
+
+          arm,axi-bus:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            maximum: 1
+            default: 0
+            description:
+              Static resource-group to AXI bus assignment. Valid field values
+              are 0 for AXI_A and 1 for AXI_B.
+
+          arm,partition-mask:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            maximum: 0xf
+            default: 0
+            description:
+              Static partition-control to resource-group assignment. Bit N
+              selects partition control ID N. Mask must be disjoint across
+              resource groups. Unassigned partitions will be assigned to
+              resource group 0 by default.
+
+          arm,slice-mask:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            maximum: 0xff
+            default: 0
+            description:
+              Static slice to resource-group assignment. Bit N selects slice ID
+              N. Mask must be disjoint across resource groups. Unassigned slices
+              will be assigned to resource group 0 by default.
+
+          arm,access-window-mask:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            maximum: 0xffff
+            default: 0
+            description:
+              Static access-window to resource-group assignment.  Bit N selects
+              access window ID N. Masks must be disjoint across resource groups.
+              Unassigned access-windows will be assigned to resource group 0 by
+              default.
+
+        required:
+          - reg
+
+patternProperties:
+  '^gpu-arbitration@[a-f0-9]+$':
+    $ref: arm,mali-gen5-am-arbitration.yaml#
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - clocks
+
+additionalProperties: false
+
+allOf:
+  - if:
+      required:
+        - assignments
+    then:
+      properties:
+        reg:
+          minItems: 2
+        reg-names:
+          minItems: 2
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    gpu-system@68000000 {
+      compatible = "arm,mali-gen5-am-system";
+      reg = <0x68000000 0x10000>;
+      reg-names = "system";
+      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+      clocks = <&mali_gpu_clk>;
+    };
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    gpu-system@68000000 {
+      compatible = "arm,mali-gen5-am-system";
+      reg = <0x68000000 0x10000>, <0x68010000 0x10000>;
+      reg-names = "system", "assign";
+      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+      clocks = <&mali_gpu_clk>;
+
+      assignments {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        resource-group@0 {
+          reg = <0>;
+          arm,axi-bus = <0>;
+          arm,partition-mask = <0x1>;
+          arm,slice-mask = <0x3>;
+          arm,access-window-mask = <0xf>;
+        };
+
+        resource-group@1 {
+          reg = <1>;
+          arm,axi-bus = <0>;
+          arm,partition-mask = <0x2>;
+          arm,slice-mask = <0xc>;
+          arm,access-window-mask = <0xf0>;
+        };
+
+        resource-group@2 {
+          reg = <2>;
+          arm,axi-bus = <1>;
+          arm,partition-mask = <0x4>;
+          arm,slice-mask = <0x30>;
+          arm,access-window-mask = <0xf00>;
+        };
+
+        resource-group@3 {
+          reg = <3>;
+          arm,axi-bus = <1>;
+          arm,partition-mask = <0x8>;
+          arm,slice-mask = <0xc0>;
+          arm,access-window-mask = <0xf000>;
+        };
+      };
+    };
+
+...
-- 
2.43.0

Re: [PATCH v2 11/28] dt-bindings: gpu: panthor: Document AM system bindings

[Krzysztof Kozlowski]

On Tue, Nov 10, 2026 at 03:38:32PM +0000, Karunika Choo wrote:
> Mali 5th-Gen AM GPUs expose an AM_SYSTEM block for GPU-wide control and
> the AM_ASSIGN block for HW resource assignment outside the GPU
> job submission register window.
> 
> Document the system node compatible, register and interrupt resources,
> GPU clock, and assignment properties for HW resource assignment.
> 
> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
> ---
> v2:
> - Add an optional AM_ASSIGN register range. Require this range when the
>   assignments node is present.
> - Describe resource-group assignments for AXI buses, partitions, slices
>   and access windows on partition-capable GPUs.
> - Allow gpu-arbitration child nodes and the #address-cells, #size-cells
>   and ranges properties.
> - Remove the panthor-system node-name restriction.
> - Remove gpu-supply from the schema and example.
> - Add an example with assignments for partition-capable GPU with four
>   resource groups.
> - Move the MAINTAINERS update to the GPU schema patch.
> 
>  .../bindings/gpu/arm,mali-gen5-am-system.yaml | 196 ++++++++++++++++++
>  1 file changed, 196 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
> 
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
> new file mode 100644
> index 0000000000000..9e0477b8b723a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
> @@ -0,0 +1,196 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +# Copyright 2026 ARM Limited. All rights reserved.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am-system.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARM Mali 5th-Gen GPU System Device
> +
> +maintainers:
> +  - Liviu Dudau <liviu.dudau@arm.com>
> +  - Boris Brezillon <boris.brezillon@collabora.com>
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: arm,mali-gen5-am-system
> +
> +  reg:
> +    minItems: 1
> +    maxItems: 2

Why is this flexible? There is no description in the binding which would
explain oddities in choices of hardware representation.

> +
> +  reg-names:
> +    minItems: 1
> +    items:
> +      - const: system
> +      - const: assign
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  dma-coherent: true
> +
> +  "#address-cells": true
> +
> +  "#size-cells": true

Both need to be const or enum.

> +
> +  ranges: true
> +
> +  assignments:

Do not mix nodes with and without bus addressing. That's mess.

> +    type: object
> +    additionalProperties: false
> +    description:
> +      Resource group HW resource assignment. Only valid for partition-capable
> +      GPUs.
> +
> +    properties:
> +      "#address-cells":
> +        const: 1
> +      "#size-cells":
> +        const: 0
> +
> +    required:
> +      - "#address-cells"
> +      - "#size-cells"
> +
> +    patternProperties:
> +      "^resource-group@[0-3]$":
> +        type: object
> +        additionalProperties: false
> +
> +        properties:
> +          reg:
> +            items:
> +              - maximum: 3
> +            description: Resource group number.
> +
> +          arm,axi-bus:
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            maximum: 1
> +            default: 0
> +            description:
> +              Static resource-group to AXI bus assignment. Valid field values
> +              are 0 for AXI_A and 1 for AXI_B.
> +
> +          arm,partition-mask:
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            maximum: 0xf
> +            default: 0
> +            description:
> +              Static partition-control to resource-group assignment. Bit N
> +              selects partition control ID N. Mask must be disjoint across
> +              resource groups. Unassigned partitions will be assigned to
> +              resource group 0 by default.
> +
> +          arm,slice-mask:
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            maximum: 0xff
> +            default: 0
> +            description:
> +              Static slice to resource-group assignment. Bit N selects slice ID
> +              N. Mask must be disjoint across resource groups. Unassigned slices
> +              will be assigned to resource group 0 by default.
> +
> +          arm,access-window-mask:
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            maximum: 0xffff
> +            default: 0
> +            description:
> +              Static access-window to resource-group assignment.  Bit N selects
> +              access window ID N. Masks must be disjoint across resource groups.
> +              Unassigned access-windows will be assigned to resource group 0 by
> +              default.
> +
> +        required:
> +          - reg
> +
> +patternProperties:
> +  '^gpu-arbitration@[a-f0-9]+$':
> +    $ref: arm,mali-gen5-am-arbitration.yaml#

There is no such file. You did not really test it.

> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - clocks
> +
> +additionalProperties: false

This goes after allOf: block.

> +
> +allOf:
> +  - if:
> +      required:
> +        - assignments
> +    then:
> +      properties:
> +        reg:
> +          minItems: 2
> +        reg-names:
> +          minItems: 2
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    gpu-system@68000000 {
> +      compatible = "arm,mali-gen5-am-system";
> +      reg = <0x68000000 0x10000>;
> +      reg-names = "system";
> +      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
> +      clocks = <&mali_gpu_clk>;
> +    };
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    gpu-system@68000000 {
> +      compatible = "arm,mali-gen5-am-system";
> +      reg = <0x68000000 0x10000>, <0x68010000 0x10000>;
> +      reg-names = "system", "assign";
> +      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
> +      clocks = <&mali_gpu_clk>;
> +
> +      assignments {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        resource-group@0 {
> +          reg = <0>;
> +          arm,axi-bus = <0>;
> +          arm,partition-mask = <0x1>;
> +          arm,slice-mask = <0x3>;
> +          arm,access-window-mask = <0xf>;
> +        };
> +
> +        resource-group@1 {
> +          reg = <1>;
> +          arm,axi-bus = <0>;
> +          arm,partition-mask = <0x2>;
> +          arm,slice-mask = <0xc>;
> +          arm,access-window-mask = <0xf0>;
> +        };
> +
> +        resource-group@2 {
> +          reg = <2>;
> +          arm,axi-bus = <1>;
> +          arm,partition-mask = <0x4>;
> +          arm,slice-mask = <0x30>;
> +          arm,access-window-mask = <0xf00>;
> +        };
> +
> +        resource-group@3 {
> +          reg = <3>;
> +          arm,axi-bus = <1>;
> +          arm,partition-mask = <0x8>;
> +          arm,slice-mask = <0xc0>;
> +          arm,access-window-mask = <0xf000>;
> +        };

Your example is incomplete.

Best regards,
Krzysztof

Re: [PATCH v2 11/28] dt-bindings: gpu: panthor: Document AM system bindings

[Karunika Choo]

On 11/11/2026 08:29, Krzysztof Kozlowski wrote:
> On Tue, Nov 10, 2026 at 03:38:32PM +0000, Karunika Choo wrote:
>> Mali 5th-Gen AM GPUs expose an AM_SYSTEM block for GPU-wide control and
>> the AM_ASSIGN block for HW resource assignment outside the GPU
>> job submission register window.
>>
>> Document the system node compatible, register and interrupt resources,
>> GPU clock, and assignment properties for HW resource assignment.
>>
>> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
>> ---
>> v2:
>> - Add an optional AM_ASSIGN register range. Require this range when the
>>   assignments node is present.
>> - Describe resource-group assignments for AXI buses, partitions, slices
>>   and access windows on partition-capable GPUs.
>> - Allow gpu-arbitration child nodes and the #address-cells, #size-cells
>>   and ranges properties.
>> - Remove the panthor-system node-name restriction.
>> - Remove gpu-supply from the schema and example.
>> - Add an example with assignments for partition-capable GPU with four
>>   resource groups.
>> - Move the MAINTAINERS update to the GPU schema patch.
>>
>>  .../bindings/gpu/arm,mali-gen5-am-system.yaml | 196 ++++++++++++++++++
>>  1 file changed, 196 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
>> new file mode 100644
>> index 0000000000000..9e0477b8b723a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
>> @@ -0,0 +1,196 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +# Copyright 2026 ARM Limited. All rights reserved.
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am-system.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: ARM Mali 5th-Gen GPU System Device
>> +
>> +maintainers:
>> +  - Liviu Dudau <liviu.dudau@arm.com>
>> +  - Boris Brezillon <boris.brezillon@collabora.com>
>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - const: arm,mali-gen5-am-system
>> +
>> +  reg:
>> +    minItems: 1
>> +    maxItems: 2
> 
> Why is this flexible? There is no description in the binding which would
> explain oddities in choices of hardware representation.

I will restore the description that was previously asked to be dropped.

>> +
>> +  reg-names:
>> +    minItems: 1
>> +    items:
>> +      - const: system
>> +      - const: assign
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +  clocks:
>> +    maxItems: 1
>> +
>> +  dma-coherent: true
>> +
>> +  "#address-cells": true
>> +
>> +  "#size-cells": true
> 
> Both need to be const or enum.
> 
>> +
>> +  ranges: true
>> +
>> +  assignments:
> 
> Do not mix nodes with and without bus addressing. That's mess.

Hi, I was asked to use a more generic DT such that should the
hardware registers change in the future we can still retain
some compatibility. Is it necessarily a problem?

> 
>> +    type: object
>> +    additionalProperties: false
>> +    description:
>> +      Resource group HW resource assignment. Only valid for partition-capable
>> +      GPUs.
>> +
>> +    properties:
>> +      "#address-cells":
>> +        const: 1
>> +      "#size-cells":
>> +        const: 0
>> +
>> +    required:
>> +      - "#address-cells"
>> +      - "#size-cells"
>> +
>> +    patternProperties:
>> +      "^resource-group@[0-3]$":
>> +        type: object
>> +        additionalProperties: false
>> +
>> +        properties:
>> +          reg:
>> +            items:
>> +              - maximum: 3
>> +            description: Resource group number.
>> +
>> +          arm,axi-bus:
>> +            $ref: /schemas/types.yaml#/definitions/uint32
>> +            maximum: 1
>> +            default: 0
>> +            description:
>> +              Static resource-group to AXI bus assignment. Valid field values
>> +              are 0 for AXI_A and 1 for AXI_B.
>> +
>> +          arm,partition-mask:
>> +            $ref: /schemas/types.yaml#/definitions/uint32
>> +            maximum: 0xf
>> +            default: 0
>> +            description:
>> +              Static partition-control to resource-group assignment. Bit N
>> +              selects partition control ID N. Mask must be disjoint across
>> +              resource groups. Unassigned partitions will be assigned to
>> +              resource group 0 by default.
>> +
>> +          arm,slice-mask:
>> +            $ref: /schemas/types.yaml#/definitions/uint32
>> +            maximum: 0xff
>> +            default: 0
>> +            description:
>> +              Static slice to resource-group assignment. Bit N selects slice ID
>> +              N. Mask must be disjoint across resource groups. Unassigned slices
>> +              will be assigned to resource group 0 by default.
>> +
>> +          arm,access-window-mask:
>> +            $ref: /schemas/types.yaml#/definitions/uint32
>> +            maximum: 0xffff
>> +            default: 0
>> +            description:
>> +              Static access-window to resource-group assignment.  Bit N selects
>> +              access window ID N. Masks must be disjoint across resource groups.
>> +              Unassigned access-windows will be assigned to resource group 0 by
>> +              default.
>> +
>> +        required:
>> +          - reg
>> +
>> +patternProperties:
>> +  '^gpu-arbitration@[a-f0-9]+$':
>> +    $ref: arm,mali-gen5-am-arbitration.yaml#
> 
> There is no such file. You did not really test it.

Sorry, this was included from a later patch that
introduces this file. I will move it there in v3.

> 
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - reg-names
>> +  - interrupts
>> +  - clocks
>> +
>> +additionalProperties: false
> 
> This goes after allOf: block.
> 
>> +
>> +allOf:
>> +  - if:
>> +      required:
>> +        - assignments
>> +    then:
>> +      properties:
>> +        reg:
>> +          minItems: 2
>> +        reg-names:
>> +          minItems: 2
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +    gpu-system@68000000 {
>> +      compatible = "arm,mali-gen5-am-system";
>> +      reg = <0x68000000 0x10000>;
>> +      reg-names = "system";
>> +      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
>> +      clocks = <&mali_gpu_clk>;
>> +    };
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +    gpu-system@68000000 {
>> +      compatible = "arm,mali-gen5-am-system";
>> +      reg = <0x68000000 0x10000>, <0x68010000 0x10000>;
>> +      reg-names = "system", "assign";
>> +      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
>> +      clocks = <&mali_gpu_clk>;
>> +
>> +      assignments {
>> +        #address-cells = <1>;
>> +        #size-cells = <0>;
>> +
>> +        resource-group@0 {
>> +          reg = <0>;
>> +          arm,axi-bus = <0>;
>> +          arm,partition-mask = <0x1>;
>> +          arm,slice-mask = <0x3>;
>> +          arm,access-window-mask = <0xf>;
>> +        };
>> +
>> +        resource-group@1 {
>> +          reg = <1>;
>> +          arm,axi-bus = <0>;
>> +          arm,partition-mask = <0x2>;
>> +          arm,slice-mask = <0xc>;
>> +          arm,access-window-mask = <0xf0>;
>> +        };
>> +
>> +        resource-group@2 {
>> +          reg = <2>;
>> +          arm,axi-bus = <1>;
>> +          arm,partition-mask = <0x4>;
>> +          arm,slice-mask = <0x30>;
>> +          arm,access-window-mask = <0xf00>;
>> +        };
>> +
>> +        resource-group@3 {
>> +          reg = <3>;
>> +          arm,axi-bus = <1>;
>> +          arm,partition-mask = <0x8>;
>> +          arm,slice-mask = <0xc0>;
>> +          arm,access-window-mask = <0xf000>;
>> +        };
> 
> Your example is incomplete.

Could you clarify what specifically is missing?

> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v2 11/28] dt-bindings: gpu: panthor: Document AM system bindings

[Krzysztof Kozlowski]

On 11/11/2026 11:43, Karunika Choo wrote:
> On 11/11/2026 08:29, Krzysztof Kozlowski wrote:
>> On Tue, Nov 10, 2026 at 03:38:32PM +0000, Karunika Choo wrote:
>>> Mali 5th-Gen AM GPUs expose an AM_SYSTEM block for GPU-wide control and
>>> the AM_ASSIGN block for HW resource assignment outside the GPU
>>> job submission register window.
>>>
>>> Document the system node compatible, register and interrupt resources,
>>> GPU clock, and assignment properties for HW resource assignment.
>>>
>>> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
>>> ---
>>> v2:
>>> - Add an optional AM_ASSIGN register range. Require this range when the
>>>   assignments node is present.
>>> - Describe resource-group assignments for AXI buses, partitions, slices
>>>   and access windows on partition-capable GPUs.
>>> - Allow gpu-arbitration child nodes and the #address-cells, #size-cells
>>>   and ranges properties.
>>> - Remove the panthor-system node-name restriction.
>>> - Remove gpu-supply from the schema and example.
>>> - Add an example with assignments for partition-capable GPU with four
>>>   resource groups.
>>> - Move the MAINTAINERS update to the GPU schema patch.
>>>
>>>  .../bindings/gpu/arm,mali-gen5-am-system.yaml | 196 ++++++++++++++++++
>>>  1 file changed, 196 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
>>> new file mode 100644
>>> index 0000000000000..9e0477b8b723a
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
>>> @@ -0,0 +1,196 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +# Copyright 2026 ARM Limited. All rights reserved.
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am-system.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: ARM Mali 5th-Gen GPU System Device
>>> +
>>> +maintainers:
>>> +  - Liviu Dudau <liviu.dudau@arm.com>
>>> +  - Boris Brezillon <boris.brezillon@collabora.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    items:
>>> +      - const: arm,mali-gen5-am-system
>>> +
>>> +  reg:
>>> +    minItems: 1
>>> +    maxItems: 2
>>
>> Why is this flexible? There is no description in the binding which would
>> explain oddities in choices of hardware representation.
> 
> I will restore the description that was previously asked to be dropped.

Hm, let me open the cover letter to find lore link to previous
discussion and check... ah wait, no cover letter!

> 
>>> +
>>> +  reg-names:
>>> +    minItems: 1
>>> +    items:
>>> +      - const: system
>>> +      - const: assign
>>> +
>>> +  interrupts:
>>> +    maxItems: 1
>>> +
>>> +  clocks:
>>> +    maxItems: 1
>>> +
>>> +  dma-coherent: true
>>> +
>>> +  "#address-cells": true
>>> +
>>> +  "#size-cells": true
>>
>> Both need to be const or enum.
>>
>>> +
>>> +  ranges: true
>>> +
>>> +  assignments:
>>
>> Do not mix nodes with and without bus addressing. That's mess.
> 
> Hi, I was asked to use a more generic DT such that should the

By whom?

> hardware registers change in the future we can still retain
> some compatibility. Is it necessarily a problem?

Bindings are not generic, but specific.

...

>>> +patternProperties:
>>> +  '^gpu-arbitration@[a-f0-9]+$':
>>> +    $ref: arm,mali-gen5-am-arbitration.yaml#
>>
>> There is no such file. You did not really test it.
> 
> Sorry, this was included from a later patch that
> introduces this file. I will move it there in v3.
> 
>>
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - reg-names
>>> +  - interrupts
>>> +  - clocks
>>> +
>>> +additionalProperties: false
>>
>> This goes after allOf: block.
>>
>>> +
>>> +allOf:
>>> +  - if:
>>> +      required:
>>> +        - assignments
>>> +    then:
>>> +      properties:
>>> +        reg:
>>> +          minItems: 2
>>> +        reg-names:
>>> +          minItems: 2
>>> +
>>> +examples:
>>> +  - |
>>> +    #include <dt-bindings/interrupt-controller/irq.h>
>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +    gpu-system@68000000 {
>>> +      compatible = "arm,mali-gen5-am-system";
>>> +      reg = <0x68000000 0x10000>;
>>> +      reg-names = "system";
>>> +      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
>>> +      clocks = <&mali_gpu_clk>;
>>> +    };
>>> +  - |
>>> +    #include <dt-bindings/interrupt-controller/irq.h>
>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +    gpu-system@68000000 {
>>> +      compatible = "arm,mali-gen5-am-system";
>>> +      reg = <0x68000000 0x10000>, <0x68010000 0x10000>;
>>> +      reg-names = "system", "assign";
>>> +      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
>>> +      clocks = <&mali_gpu_clk>;
>>> +
>>> +      assignments {
>>> +        #address-cells = <1>;
>>> +        #size-cells = <0>;
>>> +
>>> +        resource-group@0 {
>>> +          reg = <0>;
>>> +          arm,axi-bus = <0>;
>>> +          arm,partition-mask = <0x1>;
>>> +          arm,slice-mask = <0x3>;
>>> +          arm,access-window-mask = <0xf>;
>>> +        };
>>> +
>>> +        resource-group@1 {
>>> +          reg = <1>;
>>> +          arm,axi-bus = <0>;
>>> +          arm,partition-mask = <0x2>;
>>> +          arm,slice-mask = <0xc>;
>>> +          arm,access-window-mask = <0xf0>;
>>> +        };
>>> +
>>> +        resource-group@2 {
>>> +          reg = <2>;
>>> +          arm,axi-bus = <1>;
>>> +          arm,partition-mask = <0x4>;
>>> +          arm,slice-mask = <0x30>;
>>> +          arm,access-window-mask = <0xf00>;
>>> +        };
>>> +
>>> +        resource-group@3 {
>>> +          reg = <3>;
>>> +          arm,axi-bus = <1>;
>>> +          arm,partition-mask = <0x8>;
>>> +          arm,slice-mask = <0xc0>;
>>> +          arm,access-window-mask = <0xf000>;
>>> +        };
>>
>> Your example is incomplete.
> 
> Could you clarify what specifically is missing?

ll the properties you added in the binding.

Best regards,
Krzysztof

[PATCH v2 13/28] dt-bindings: gpu: panthor: Document panthor-arbitration bindings

[Karunika Choo]

Mali 5th-Gen AM GPUs expose partition-control and resource-group
registers outside the GPU node.

Document named register and interrupt resources in the arbitration node.
The pcN and rgN names identify the hardware blocks.

Document initial access-window and slice assignments in partition child
nodes. The reg property identifies the partition-control index.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v2:
- Return to using named register and interrupt arrays instead of
  individual entries in child nodes.
- Added register and interrupt entries for partition-capable GPUs
  (rg[0-3], pc[0-3]).
- Introduce partition nodes to define default access-window and slice
  masks.
- Point child Panthor device node to new arm,mali-gen5-am.yaml
- Added partition-capable GPU example entry.

v2:
- Introduce assignment_lock to protect assignments allowing serialized
  lookup without the need for READ_ONCE or WRITE_ONCE.
- Add pending_aw_request_mask to track and replay pending requests
  arriving before AW assignments are initialized.

 .../gpu/arm,mali-gen5-am-arbitration.yaml     | 198 ++++++++++++++++++
 1 file changed, 198 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
new file mode 100644
index 0000000000000..633dd823bd3d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
@@ -0,0 +1,198 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright 2026 ARM Limited. All rights reserved.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am-arbitration.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali 5th-Gen GPU Arbitration Device
+
+maintainers:
+  - Liviu Dudau <liviu.dudau@arm.com>
+  - Boris Brezillon <boris.brezillon@collabora.com>
+
+description:
+  The arbitration device manages GPU partition-control and resource-group
+  blocks. Register and interrupt names pcN and rgN identify their hardware
+  indices. Partition child nodes describe initial resource assignments,
+  with reg identifying the partition-control index. Access-window and slice
+  indices are global to the GPU, each resource may be assigned to at most one
+  partition.
+
+properties:
+  compatible:
+    const: arm,mali-gen5-am-arbitration
+
+  reg:
+    minItems: 2
+    maxItems: 8
+
+  reg-names:
+    minItems: 2
+    maxItems: 8
+    items:
+      enum: [pc0, pc1, pc2, pc3, rg0, rg1, rg2, rg3]
+
+  interrupts:
+    minItems: 2
+    maxItems: 8
+
+  interrupt-names:
+    minItems: 2
+    maxItems: 8
+    items:
+      enum: [pc0, pc1, pc2, pc3, rg0, rg1, rg2, rg3]
+
+  "#address-cells": true
+  "#size-cells": true
+  ranges: true
+
+  partitions:
+    type: object
+    additionalProperties: false
+
+    properties:
+      "#address-cells":
+        const: 1
+      "#size-cells":
+        const: 0
+
+    required:
+      - "#address-cells"
+      - "#size-cells"
+
+    patternProperties:
+      "^partition@[0-3]$":
+        type: object
+        additionalProperties: false
+        description:
+          Initial partition resource assignments.
+
+        properties:
+          reg:
+            items:
+              - maximum: 3
+            description: Partition control number.
+
+          arm,access-window-mask:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            maximum: 0xffff
+            default: 0
+            description:
+              Initial access window assignment mask. Bit N selects global
+              access window ID N. Masks must be disjoint across partitions.
+              If omitted on partitioning-capable GPUs, no access windows are
+              assigned by default. Non-partitioning GPUs will have all AWs
+              assigned to pc0 if value is 0 or not defined.
+
+          arm,slice-mask:
+            $ref: /schemas/types.yaml#/definitions/uint32
+            maximum: 0xff
+            default: 0
+            description:
+              Initial slice assignment mask. Bit N selects global slice ID N.
+              Masks must be disjoint across partitions. If omitted, no
+              partitions are created by default. This property is only valid for
+              partition-capable GPUs.
+
+        required:
+          - reg
+
+patternProperties:
+  "^gpu@[0-9a-f]+$":
+    $ref: arm,mali-gen5-am.yaml#
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    gpu-arbitration@50000 {
+      compatible = "arm,mali-gen5-am-arbitration";
+      reg = <0x50000 0x10000>,
+            <0xC0000 0x10000>;
+      reg-names = "pc0", "rg0";
+      interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
+                    <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>;
+      interrupt-names = "pc0", "rg0";
+
+      partitions {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        partition@0 {
+            reg = <0x0>;
+            arm,access-window-mask = <0xffff>;
+        };
+      };
+    };
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    gpu-arbitration@40000 {
+      compatible = "arm,mali-gen5-am-arbitration";
+      reg = <0x40000 0x10000>,
+            <0x50000 0x10000>,
+            <0xC0000 0x10000>;
+      reg-names = "pc0", "pc1", "rg0";
+      interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
+                    <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
+                    <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
+      interrupt-names = "pc0", "pc1", "rg0";
+
+      partitions {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        partition@0 {
+            reg = <0x0>;
+            arm,access-window-mask = <0xf>;
+            arm,slice-mask = <0x3>;
+        };
+        partition@1 {
+            reg = <0x1>;
+            arm,access-window-mask = <0xf0>;
+            arm,slice-mask = <0xc>;
+        };
+      };
+    };
+
+    gpu-arbitration@60000 {
+      compatible = "arm,mali-gen5-am-arbitration";
+      reg = <0x60000 0x10000>,
+            <0x70000 0x10000>,
+            <0xD0000 0x10000>;
+      reg-names = "pc2", "pc3", "rg1";
+      interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>,
+                    <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>,
+                    <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+      interrupt-names = "pc2", "pc3", "rg1";
+
+      partitions {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        partition@2 {
+            reg = <0x2>;
+            arm,access-window-mask = <0xf00>;
+            arm,slice-mask = <0x30>;
+        };
+        partition@3 {
+            reg = <0x3>;
+            arm,access-window-mask = <0xf000>;
+            arm,slice-mask = <0xc0>;
+        };
+      };
+    };
+
+...
-- 
2.43.0