From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
To: "devnull+aleksa.paunovic.htecgroup.com@kernel.org"
<devnull+aleksa.paunovic.htecgroup.com@kernel.org>
Cc: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>,
"alex@ghiti.fr" <alex@ghiti.fr>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
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Djordje Todorovic <Djordje.Todorovic@htecgroup.com>,
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Subject: Re: [PATCH v7 0/3] riscv: Use GCR.U timer device as clocksource
Date: Wed, 8 Apr 2026 11:53:30 +0000 [thread overview]
Message-ID: <ac1c7966-6db1-4e00-aad5-4650d7b8c11a@htecgroup.com> (raw)
In-Reply-To: <20260311-riscv-time-mmio-v7-0-016845a0f808@htecgroup.com>
On 3/11/26 14:26, Aleksa Paunovic via B4 Relay wrote:
> This series adds bindings for the GCR.U timer device and corresponding
> driver support. Accessing the memory mapped shadow of the mtime register
> in the GCR.U region should be faster
> than trapping to M mode each time the timer needs to be read.
> The timer device does not implement any interrupts, therefore the
> timer-riscv clockevent implementation should suffice.
>
> We tested the patchset both on QEMU and the Boston board with the P8700 bitfile:
> - Coremark and timer kselftests on QEMU emulating an 8 core CPU
> - Coremark and timer kselftests on the Boston board with a single core CPU.
Gentle ping.
next prev parent reply other threads:[~2026-04-08 11:53 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-11 13:26 [PATCH v7 0/3] riscv: Use GCR.U timer device as clocksource Aleksa Paunovic via B4 Relay
2026-03-11 13:26 ` [PATCH v7 1/3] dt-bindings: timer: mips,p8700-gcru Aleksa Paunovic via B4 Relay
2026-03-11 13:26 ` [PATCH v7 2/3] riscv: clocksource: Add readq options to clocksource mmio Aleksa Paunovic via B4 Relay
2026-03-11 13:26 ` [PATCH v7 3/3] riscv: clocksource: Add p8700-gcru driver Aleksa Paunovic via B4 Relay
2026-04-08 11:53 ` Aleksa Paunovic [this message]
2026-04-29 15:13 ` [PATCH v7 0/3] riscv: Use GCR.U timer device as clocksource Aleksa Paunovic
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