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From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
To: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
Cc: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>,
	"alex@ghiti.fr" <alex@ghiti.fr>,
	"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
	"cfu@mips.com" <cfu@mips.com>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"conor.dooley@microchip.com" <conor.dooley@microchip.com>,
	"daniel.lezcano@linaro.org" <daniel.lezcano@linaro.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"devnull+aleksa.paunovic.htecgroup.com@kernel.org"
	<devnull+aleksa.paunovic.htecgroup.com@kernel.org>,
	"jstultz@google.com" <jstultz@google.com>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"palmer@dabbelt.com" <palmer@dabbelt.com>,
	"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
	"pjw@kernel.org" <pjw@kernel.org>,
	"robh@kernel.org" <robh@kernel.org>,
	"sboyd@kernel.org" <sboyd@kernel.org>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"wangruikang@iscas.ac.cn" <wangruikang@iscas.ac.cn>
Subject: Re: [PATCH v7 0/3] riscv: Use GCR.U timer device as clocksource
Date: Wed, 29 Apr 2026 15:13:08 +0000	[thread overview]
Message-ID: <d9b8ab57-7fdb-4cd0-84fc-b1cd9f04e5d6@htecgroup.com> (raw)
In-Reply-To: <ac1c7966-6db1-4e00-aad5-4650d7b8c11a@htecgroup.com>

On 4/8/26 13:53, Aleksa Paunovic wrote:
> On 3/11/26 14:26, Aleksa Paunovic via B4 Relay wrote:
>> This series adds bindings for the GCR.U timer device and corresponding
>> driver support. Accessing the memory mapped shadow of the mtime register
>> in the GCR.U region should be faster
>> than trapping to M mode each time the timer needs to be read.
>> The timer device does not implement any interrupts, therefore the
>> timer-riscv clockevent implementation should suffice.
>>
>> We tested the patchset both on QEMU and the Boston board with the P8700 bitfile:
>> - Coremark and timer kselftests on QEMU emulating an 8 core CPU
>> - Coremark and timer kselftests on the Boston board with a single core CPU.
> Gentle ping.
Pinging this.

      reply	other threads:[~2026-04-29 15:13 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-11 13:26 [PATCH v7 0/3] riscv: Use GCR.U timer device as clocksource Aleksa Paunovic via B4 Relay
2026-03-11 13:26 ` [PATCH v7 1/3] dt-bindings: timer: mips,p8700-gcru Aleksa Paunovic via B4 Relay
2026-03-11 13:26 ` [PATCH v7 2/3] riscv: clocksource: Add readq options to clocksource mmio Aleksa Paunovic via B4 Relay
2026-03-11 13:26 ` [PATCH v7 3/3] riscv: clocksource: Add p8700-gcru driver Aleksa Paunovic via B4 Relay
2026-04-08 11:53 ` [PATCH v7 0/3] riscv: Use GCR.U timer device as clocksource Aleksa Paunovic
2026-04-29 15:13   ` Aleksa Paunovic [this message]

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