[PATCH v2 0/3] Add support and enable the debug UART in the Pixel 3a and Pixel 3a XL

[PATCH v2 0/3] Add support and enable the debug UART in the Pixel 3a and Pixel 3a XL

[Pablo Correa Gómez via B4 Relay]

In order to get logs through the SBU pins in Google Pixel devices, it is
necessary to add support to the devicetree, and enable the corresponding
UART. With this code and an USB-Cereal board, I was able to get full kernel
logs through serial.

This series depends on the patch adding a sdm670-google-common dtsi for
dealing with both the Pixel 3a and Pixel 3a XL:
https://lore.kernel.org/all/20260310002606.16413-5-mailingradian@gmail.com/

This is my first patch sent to the kernel mailing list, so apologies ahead
if I missed something in the documentation.

Signed-off-by: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
---
Changes in v2:
- Fix typo in (3/3) commit message
- Link to v1: https://patch.msgid.link/20260328-pabloyoyoista-debug-uart-on-rdacayan-next-v1-0-0babf584acdb@postmarketos.org

---
Pablo Correa Gómez (3):
      arm64: dts: qcom: sdm670: add default uart pinctrl nodes
      arm64: dts: qcom: sdm670: add debug uart soc node
      arm64: dts: qcom: sdm670-google-common: enable debug uart

 arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi |  18 +-
 arch/arm64/boot/dts/qcom/sdm670.dtsi               | 207 +++++++++++++++++++++
 2 files changed, 224 insertions(+), 1 deletion(-)
---
base-commit: 54f966f63b379d0c62bb044b7903319776443a4a
change-id: 20260328-pabloyoyoista-debug-uart-on-rdacayan-next-69274358cef4
prerequisite-message-id: <20260217002738.133534-1-mailingradian@gmail.com>
prerequisite-patch-id: aeaea0c438bff770d0c4c33d937db5706d642daf
prerequisite-patch-id: 11ce654ef61d48fdebf1c4e1d9d184cfb7bcaa59
prerequisite-patch-id: c6203c8a71fe103b983b6ba5fc99a22948118fb4
prerequisite-patch-id: f9ff17c7e4b4396850f51e45249d2f6e35df3725
prerequisite-patch-id: faab09f9fe421a6358e5512c6050dd70d3271273
prerequisite-patch-id: adb88e3ddcbe33db1e3fc60ea4cb195dac18a8b4
prerequisite-patch-id: 0c8f7fc0835cdda72529fcfa7b654bb97109fae4
prerequisite-message-id: <20260310002606.16413-1-mailingradian@gmail.com>
prerequisite-patch-id: eb2d2be6edae3d09973b49f3ff6c48fa0845e7e0
prerequisite-patch-id: e6d9e56eaeceddee68d56e2ec8ac20997bff52c9
prerequisite-patch-id: d5e2975adf904bf656827100df7989218ac9e963
prerequisite-patch-id: 04478351b1304dfe1357d176c8d0c235346ca40f
prerequisite-patch-id: a54db56ccdf1491c46158a84ac1cae70f74bb36c

Best regards,
--  
Pablo Correa Gómez <pabloyoyoista@postmarketos.org>

[PATCH v2 1/3] arm64: dts: qcom: sdm670: add default uart pinctrl nodes

[Pablo Correa Gómez via B4 Relay]

From: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>

This is a pre-requisite to enable UART in sargo and bonito. Values for
the pins have been taken from sdm845, and cross-checking dowstream,
where available.

Signed-off-by: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
---
 arch/arm64/boot/dts/qcom/sdm670.dtsi | 192 +++++++++++++++++++++++++++++++++++
 1 file changed, 192 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 6b296ceaebc2..3e60ab527a42 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -1352,6 +1352,198 @@ qup_i2c15_default: qup-i2c15-default-state {
 				function = "qup15";
 			};
 
+			qup_uart0_default: qup-uart0-default-state {
+				qup_uart0_tx: tx-pins {
+					pins = "gpio2";
+					function = "qup0";
+				};
+
+				qup_uart0_rx: rx-pins {
+					pins = "gpio3";
+					function = "qup0";
+				};
+			};
+
+			qup_uart1_default: qup-uart1-default-state {
+				qup_uart1_tx: tx-pins {
+					pins = "gpio19";
+					function = "qup1";
+				};
+
+				qup_uart1_rx: rx-pins {
+					pins = "gpio20";
+					function = "qup1";
+				};
+			};
+
+			qup_uart2_default: qup-uart2-default-state {
+				qup_uart2_tx: tx-pins {
+					pins = "gpio29";
+					function = "qup2";
+				};
+
+				qup_uart2_rx: rx-pins {
+					pins = "gpio30";
+					function = "qup2";
+				};
+			};
+
+			qup_uart3_default: qup-uart3-default-state {
+				qup_uart3_tx: tx-pins {
+					pins = "gpio43";
+					function = "qup3";
+				};
+
+				qup_uart3_rx: rx-pins {
+					pins = "gpio44";
+					function = "qup3";
+				};
+			};
+
+			qup_uart4_default: qup-uart4-default-state {
+				qup_uart4_tx: tx-pins {
+					pins = "gpio91";
+					function = "qup4";
+				};
+
+				qup_uart4_rx: rx-pins {
+					pins = "gpio92";
+					function = "qup4";
+				};
+			};
+
+			qup_uart5_default: qup-uart5-default-state {
+				qup_uart5_tx: tx-pins {
+					pins = "gpio87";
+					function = "qup5";
+				};
+
+				qup_uart5_rx: rx-pins {
+					pins = "gpio88";
+					function = "qup5";
+				};
+			};
+
+			qup_uart6_default: qup-uart6-default-state {
+				qup_uart6_tx: tx-pins {
+					pins = "gpio47";
+					function = "qup6";
+				};
+
+				qup_uart6_rx: rx-pins {
+					pins = "gpio48";
+					function = "qup6";
+				};
+			};
+
+			qup_uart7_default: qup-uart7-default-state {
+				qup_uart7_tx: tx-pins {
+					pins = "gpio95";
+					function = "qup7";
+				};
+
+				qup_uart7_rx: rx-pins {
+					pins = "gpio96";
+					function = "qup7";
+				};
+			};
+
+			qup_uart8_default: qup-uart8-default-state {
+				qup_uart8_tx: tx-pins {
+					pins = "gpio67";
+					function = "qup8";
+				};
+
+				qup_uart8_rx: rx-pins {
+					pins = "gpio68";
+					function = "qup8";
+				};
+			};
+
+			qup_uart9_default: qup-uart9-default-state {
+				qup_uart9_tx: tx-pins {
+					pins = "gpio4";
+					function = "qup9";
+				};
+
+				qup_uart9_rx: rx-pins {
+					pins = "gpio5";
+					function = "qup9";
+				};
+			};
+
+			qup_uart10_default: qup-uart10-default-state {
+				qup_uart10_tx: tx-pins {
+					pins = "gpio53";
+					function = "qup10";
+				};
+
+				qup_uart10_rx: rx-pins {
+					pins = "gpio54";
+					function = "qup10";
+				};
+			};
+
+			qup_uart11_default: qup-uart11-default-state {
+				qup_uart11_tx: tx-pins {
+					pins = "gpio33";
+					function = "qup11";
+				};
+
+				qup_uart11_rx: rx-pins {
+					pins = "gpio34";
+					function = "qup11";
+				};
+			};
+
+			qup_uart12_default: qup-uart12-default-state {
+				qup_uart12_tx: tx-pins {
+					pins = "gpio51";
+					function = "qup12";
+				};
+
+				qup_uart12_rx: rx-pins {
+					pins = "gpio52";
+					function = "qup12";
+				};
+			};
+
+			qup_uart13_default: qup-uart13-default-state {
+				qup_uart13_tx: tx-pins {
+					pins = "gpio107";
+					function = "qup13";
+				};
+
+				qup_uart13_rx: rx-pins {
+					pins = "gpio108";
+					function = "qup13";
+				};
+			};
+
+			qup_uart14_default: qup-uart14-default-state {
+				qup_uart14_tx: tx-pins {
+					pins = "gpio31";
+					function = "qup14";
+				};
+
+				qup_uart14_rx: rx-pins {
+					pins = "gpio32";
+					function = "qup14";
+				};
+			};
+
+			qup_uart15_default: qup-uart15-default-state {
+				qup_uart15_tx: tx-pins {
+					pins = "gpio83";
+					function = "qup15";
+				};
+
+				qup_uart15_rx: rx-pins {
+					pins = "gpio84";
+					function = "qup15";
+				};
+			};
+
 			sdc1_state_on: sdc1-on-state {
 				clk-pins {
 					pins = "sdc1_clk";

-- 
2.53.0

[PATCH v2 2/3] arm64: dts: qcom: sdm670: add debug uart soc node

[Pablo Correa Gómez via B4 Relay]

From: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>

Values are taken from the other geni nodes

Signed-off-by: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
---
 arch/arm64/boot/dts/qcom/sdm670.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 3e60ab527a42..25cf21c57b7d 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -1069,6 +1069,21 @@ i2c12: i2c@a90000 {
 				status = "disabled";
 			};
 
+			uart12: serial@a90000 {
+				compatible = "qcom,geni-debug-uart";
+				reg = <0 0x00a90000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart12_default>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SDM670_CX>;
+				interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
+						<&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
 			i2c13: i2c@a94000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0 0x00a94000 0 0x4000>;

-- 
2.53.0

[PATCH v2 3/3] arm64: dts: qcom: sdm670-google-common: enable debug uart

[Pablo Correa Gómez via B4 Relay]

From: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>

This has been tested on the Pixel 3a with USB Cereal board

Depends on
https://lore.kernel.org/all/20260310002606.16413-5-mailingradian@gmail.com/

Signed-off-by: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
---
 arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi
index 32dce1cfdf6f..e8bd5f3861e4 100644
--- a/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi
@@ -27,7 +27,9 @@
 /delete-node/ &gpu_mem;
 
 / {
-	aliases { };
+	aliases {
+		serial0 = &uart12;
+	};
 
 	battery: battery {
 		compatible = "simple-battery";
@@ -683,6 +685,16 @@ &qupv3_id_1 {
 	status = "okay";
 };
 
+&qup_uart12_rx {
+	drive-strength = <2>;
+	bias-pull-up;
+};
+
+&qup_uart12_tx {
+	drive-strength = <2>;
+	bias-disable;
+};
+
 &sdhc_1 {
 	supports-cqe;
 	mmc-hs200-1_8v;
@@ -749,6 +761,10 @@ ts-switch-pins {
 	};
 };
 
+&uart12 {
+	status = "okay";
+};
+
 &usb_1_hsphy {
 	vdd-supply = <&vreg_l1b_0p925>;
 	vdda-pll-supply = <&vreg_l10a_1p8>;

-- 
2.53.0

Re: [PATCH v2 3/3] arm64: dts: qcom: sdm670-google-common: enable debug uart

[Dmitry Baryshkov]

On Sat, Mar 28, 2026 at 11:58:42PM +0100, Pablo Correa Gómez via B4 Relay wrote:
> From: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
> 
> This has been tested on the Pixel 3a with USB Cereal board
> 
> Depends on
> https://lore.kernel.org/all/20260310002606.16413-5-mailingradian@gmail.com/
> 
> Signed-off-by: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
> ---
>  arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH v2 2/3] arm64: dts: qcom: sdm670: add debug uart soc node

[Dmitry Baryshkov]

On Sat, Mar 28, 2026 at 11:58:41PM +0100, Pablo Correa Gómez via B4 Relay wrote:
> From: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
> 
> Values are taken from the other geni nodes
> 
> Signed-off-by: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
> ---
>  arch/arm64/boot/dts/qcom/sdm670.dtsi | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH v2 2/3] arm64: dts: qcom: sdm670: add debug uart soc node

[Konrad Dybcio]

On 3/28/26 11:58 PM, Pablo Correa Gómez via B4 Relay wrote:
> From: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
> 
> Values are taken from the other geni nodes
> 
> Signed-off-by: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 3/3] arm64: dts: qcom: sdm670-google-common: enable debug uart

[Konrad Dybcio]

On 3/28/26 11:58 PM, Pablo Correa Gómez via B4 Relay wrote:
> From: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
> 
> This has been tested on the Pixel 3a with USB Cereal board
> 
> Depends on
> https://lore.kernel.org/all/20260310002606.16413-5-mailingradian@gmail.com/
> 
> Signed-off-by: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 0/3] Add support and enable the debug UART in the Pixel 3a and Pixel 3a XL

[Bjorn Andersson]

On Sat, Mar 28, 2026 at 11:58:39PM +0100, Pablo Correa Gómez via B4 Relay wrote:
> In order to get logs through the SBU pins in Google Pixel devices, it is
> necessary to add support to the devicetree, and enable the corresponding
> UART. With this code and an USB-Cereal board, I was able to get full kernel
> logs through serial.
> 
> This series depends on the patch adding a sdm670-google-common dtsi for
> dealing with both the Pixel 3a and Pixel 3a XL:
> https://lore.kernel.org/all/20260310002606.16413-5-mailingradian@gmail.com/

Please resubmit when this dependency has been accepted, or perhaps work
together with Richard to send the two series together, if possible.

> 
> This is my first patch sent to the kernel mailing list, so apologies ahead
> if I missed something in the documentation.
> 

Once the patches are applied, the "Depends on" statement in patch 3
doesn't carry any value, so please drop that.

Other than that, I think this looks good.

Thank,
Bjorn

> Signed-off-by: Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
> ---
> Changes in v2:
> - Fix typo in (3/3) commit message
> - Link to v1: https://patch.msgid.link/20260328-pabloyoyoista-debug-uart-on-rdacayan-next-v1-0-0babf584acdb@postmarketos.org
> 
> ---
> Pablo Correa Gómez (3):
>       arm64: dts: qcom: sdm670: add default uart pinctrl nodes
>       arm64: dts: qcom: sdm670: add debug uart soc node
>       arm64: dts: qcom: sdm670-google-common: enable debug uart
> 
>  arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi |  18 +-
>  arch/arm64/boot/dts/qcom/sdm670.dtsi               | 207 +++++++++++++++++++++
>  2 files changed, 224 insertions(+), 1 deletion(-)
> ---
> base-commit: 54f966f63b379d0c62bb044b7903319776443a4a
> change-id: 20260328-pabloyoyoista-debug-uart-on-rdacayan-next-69274358cef4
> prerequisite-message-id: <20260217002738.133534-1-mailingradian@gmail.com>
> prerequisite-patch-id: aeaea0c438bff770d0c4c33d937db5706d642daf
> prerequisite-patch-id: 11ce654ef61d48fdebf1c4e1d9d184cfb7bcaa59
> prerequisite-patch-id: c6203c8a71fe103b983b6ba5fc99a22948118fb4
> prerequisite-patch-id: f9ff17c7e4b4396850f51e45249d2f6e35df3725
> prerequisite-patch-id: faab09f9fe421a6358e5512c6050dd70d3271273
> prerequisite-patch-id: adb88e3ddcbe33db1e3fc60ea4cb195dac18a8b4
> prerequisite-patch-id: 0c8f7fc0835cdda72529fcfa7b654bb97109fae4
> prerequisite-message-id: <20260310002606.16413-1-mailingradian@gmail.com>
> prerequisite-patch-id: eb2d2be6edae3d09973b49f3ff6c48fa0845e7e0
> prerequisite-patch-id: e6d9e56eaeceddee68d56e2ec8ac20997bff52c9
> prerequisite-patch-id: d5e2975adf904bf656827100df7989218ac9e963
> prerequisite-patch-id: 04478351b1304dfe1357d176c8d0c235346ca40f
> prerequisite-patch-id: a54db56ccdf1491c46158a84ac1cae70f74bb36c
> 
> Best regards,
> --  
> Pablo Correa Gómez <pabloyoyoista@postmarketos.org>
> 
>