Re: [PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes

Re: [PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes

[Pengyu Luo]

On Thu, Mar 5, 2026 6:40 PM Taniya Das <taniya.das@oss.qualcomm.com> wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this
> is simply a separate block housing the GX GDSC) nodes, required to
> power up the graphics-related hardware.
>
> Make use of it by enabling the associated IOMMU as well. The GPU itself
> needs some more work and will be enabled later.
>
> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---
>

Hi Taniya and Konrad, GX GDSC stuck at 'on' on my device
the raw register values are

0x3d68024: 0x00000000
0x3d68028: 0x00000000

[    0.593882] msm_dpu ae01000.display-controller: bound 3d00000.gpu
(ops a3xx_ops)
[    0.594237] [drm:dpu_kms_hw_init:1173] dpu hardware revision:0xc0000000
[    0.598140] [drm] Initialized msm 1.13.0 for
ae01000.display-controller on minor 0
[    0.598213] msm_dpu ae01000.display-controller:
[drm:adreno_request_fw] loaded qcom/gen80000_sqe.fw from new location
[    0.598267] msm_dpu ae01000.display-controller:
[drm:adreno_request_fw] loaded qcom/gen80000_gmu.bin from new location
[    0.598288] msm_dpu ae01000.display-controller:
[drm:adreno_request_fw] loaded qcom/gen80000_aqe.fw from new location
[    0.600620] [drm] Loaded GMU firmware v5.1.25
[    0.698366] ------------[ cut here ]------------
[    0.698368] gx_clkctl_gx_gdsc status stuck at 'on'
[    0.698385] WARNING: drivers/clk/qcom/gdsc.c:178 at
gdsc_toggle_logic+0x140/0x160, CPU#3: kworker/u33:3/84
[    0.698394] Modules linked in: fastrpc qrtr_smd rpmsg_ctrl
panel_nt36536(+) joydev mousedev qcom_pd_mapper ucsi_glink
pmic_glink_altmode typec_ucsi aux_hpd_bridge qcom_battmgr aw99706
nvmem_qcom_spmi_sdam nt36532_ts qcom_spmi_temp_alarm fsa4480
regmap_i2c phy_nxp_ptn3222 industrialio rtc_pm8xxx qcom_stats
phy_qcom_qmp_combo aux_bridge typec qcom_q6v5_pas qcom_pil_info
qcom_common phy_qcom_m31_eusb2 qcom_q6v5 qcom_sysmon icc_bwmon
qcom_rng sm3_ce qrtr nvmem_reboot_mode arm_smccc_trng pmic_glink
rng_core
[    0.698445] CPU: 3 UID: 0 PID: 84 Comm: kworker/u33:3 Not tainted
6.19.6-sm8750+ #5 PREEMPT
[    0.698450] Hardware name: LENOVO TB322FC (DT)
[    0.698452] Workqueue: pm pm_runtime_work
[    0.698457] pstate: 61400005 (nZCv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--)
[    0.698462] pc : gdsc_toggle_logic+0x140/0x160
[    0.698466] lr : gdsc_toggle_logic+0x140/0x160
[    0.698469] sp : ffff8000810bb920
[    0.698471] x29: ffff8000810bb920 x28: 0000000000000000 x27: 0000000000000000
[    0.698477] x26: ffff000800065428 x25: 0000000000000008 x24: 0000000000000000
[    0.698482] x23: 0000000000000000 x22: 0000000000000000 x21: 0000000000000001
[    0.698487] x20: 0000000000000000 x19: ffffa3c20a6abb98 x18: ffff5c4963eb2000
[    0.698492] x17: ffff000800a062c0 x16: ffffa3c20a71a510 x15: ffffa3c20a56d230
[    0.698497] x14: 0000000000000000 x13: 6f27207461206b63 x12: 7574732073757461
[    0.698502] x11: 0000000000000058 x10: 0000000000000027 x9 : ffffa3c208f81e50
[    0.698507] x8 : 0000000000000027 x7 : 7461206b63757473 x6 : 0000000000000000
[    0.698512] x5 : 0000000000000001 x4 : 00000000fffc025b x3 : 00000000ffffffff
[    0.698517] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000802511f80
[    0.698522] Call trace:
[    0.698524]  gdsc_toggle_logic+0x140/0x160 (P)
[    0.698528]  gdsc_disable+0x4c/0x190
[    0.698533]  _genpd_power_off+0xa4/0x1a8
[    0.698538]  genpd_power_off.part.0+0x170/0x270
[    0.698543]  genpd_power_off+0x50/0x68
[    0.698548]  genpd_runtime_suspend+0x1e4/0x2e8
[    0.698553]  __rpm_callback+0x50/0x220
[    0.698560]  rpm_callback+0x7c/0x90
[    0.698567]  rpm_suspend+0xe8/0x590
[    0.698573]  rpm_idle+0x128/0x3c0
[    0.698580]  __pm_runtime_idle+0x58/0x100
[    0.698587]  a6xx_gmu_stop+0x74/0x3e0
[    0.698592]  a6xx_gmu_pm_suspend+0x48/0x118
[    0.698597]  adreno_runtime_suspend+0x38/0x68
[    0.698604]  pm_generic_runtime_suspend+0x34/0x60
[    0.698609]  __rpm_callback+0x50/0x220
[    0.698616]  rpm_callback+0x7c/0x90
[    0.698622]  rpm_suspend+0xe8/0x590
[    0.698629]  pm_runtime_work+0xcc/0xe0
[    0.698632]  process_one_work+0x15c/0x3c0
[    0.698638]  worker_thread+0x18c/0x320
[    0.698642]  kthread+0x148/0x208
[    0.698646]  ret_from_fork+0x10/0x20
[    0.698653] ---[ end trace 0000000000000000 ]---

[    6.710781] ------------[ cut here ]------------
[    6.710786] gx_clkctl_gx_gdsc status stuck at 'on'
[    6.710793] WARNING: drivers/clk/qcom/gdsc.c:178 at
gdsc_toggle_logic+0x140/0x160, CPU#5: kworker/u33:5/143
[    6.710799] Modules linked in: snd_q6apm snd_soc_core snd_compress
snd_pcm snd_timer snd soundcore fastrpc qrtr_smd rpmsg_ctrl
panel_nt36536 joydev mousedev qcom_pd_mapper ucsi_glink
pmic_glink_altmode typec_ucsi aux_hpd_bridge qcom_battmgr aw99706
nvmem_qcom_spmi_sdam nt36532_ts qcom_spmi_temp_alarm fsa4480
regmap_i2c phy_nxp_ptn3222 industrialio rtc_pm8xxx qcom_stats
phy_qcom_qmp_combo aux_bridge typec qcom_q6v5_pas qcom_pil_info
qcom_common phy_qcom_m31_eusb2 qcom_q6v5 qcom_sysmon icc_bwmon
qcom_rng sm3_ce qrtr nvmem_reboot_mode arm_smccc_trng pmic_glink
rng_core
[    6.710831] CPU: 5 UID: 0 PID: 143 Comm: kworker/u33:5 Tainted: G
     W           6.19.6-sm8750+ #5 PREEMPT
[    6.710833] Tainted: [W]=WARN
[    6.710834] Hardware name: LENOVO TB322FC (DT)
[    6.710835] Workqueue: pm pm_runtime_work
[    6.710837] pstate: 61400005 (nZCv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--)
[    6.710839] pc : gdsc_toggle_logic+0x140/0x160
[    6.710840] lr : gdsc_toggle_logic+0x140/0x160
[    6.710842] sp : ffff80008205b920
[    6.710842] x29: ffff80008205b920 x28: 0000000000000000 x27: 0000000000000000
[    6.710845] x26: ffff000800065428 x25: 0000000000000008 x24: 0000000000000000
[    6.710847] x23: 0000000000000000 x22: 0000000000000000 x21: 0000000000000001
[    6.710849] x20: 0000000000000000 x19: ffffa3c20a6abb98 x18: 000000000000000a
[    6.710851] x17: 0000000006000000 x16: 0000000000000000 x15: 0000000000000000
[    6.710853] x14: 0000000000000000 x13: 6f27207461206b63 x12: 7574732073757461
[    6.710856] x11: 0000000000000058 x10: 0000000000000018 x9 : ffffa3c208f81e50
[    6.710858] x8 : 00000000015fffa8 x7 : 0000000000000316 x6 : 0000000000000001
[    6.710860] x5 : ffff000b6e3a17c8 x4 : ffff5c4963ef2000 x3 : ffff000807c95e80
[    6.710862] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000807c95e80
[    6.710864] Call trace:
[    6.710865]  gdsc_toggle_logic+0x140/0x160 (P)
[    6.710867]  gdsc_disable+0x4c/0x190
[    6.710869]  _genpd_power_off+0xa4/0x1a8
[    6.710871]  genpd_power_off.part.0+0x170/0x270
[    6.710873]  genpd_power_off+0x50/0x68
[    6.710874]  genpd_runtime_suspend+0x1e4/0x2e8
[    6.710876]  __rpm_callback+0x50/0x220
[    6.710879]  rpm_callback+0x7c/0x90
[    6.710881]  rpm_suspend+0xe8/0x590
[    6.710883]  rpm_idle+0x128/0x3c0
[    6.710885]  __pm_runtime_idle+0x58/0x100
[    6.710887]  a6xx_gmu_stop+0x74/0x3e0
[    6.710890]  a6xx_gmu_pm_suspend+0x48/0x118
[    6.710892]  adreno_runtime_suspend+0x38/0x68
[    6.710894]  pm_generic_runtime_suspend+0x34/0x60
[    6.710896]  __rpm_callback+0x50/0x220
[    6.710898]  rpm_callback+0x7c/0x90
[    6.710900]  rpm_suspend+0xe8/0x590
[    6.710902]  pm_runtime_work+0xcc/0xe0
[    6.710903]  process_one_work+0x15c/0x3c0
[    6.710906]  worker_thread+0x18c/0x320
[    6.710908]  kthread+0x148/0x208
[    6.710909]  ret_from_fork+0x10/0x20
[    6.710912] ---[ end trace 0000000000000000 ]---
[    6.726652] adreno 3d00000.gpu: CP Fault Global INT status: 0x10000
[    6.726659] adreno 3d00000.gpu: CP SW FAULT pipe: 1 status: 0x400
[    6.726661] adreno 3d00000.gpu: CP REG PROTECT error, status=0x608212
[    6.726736] msm_dpu ae01000.display-controller:
[drm:recover_worker] *ERROR* 68.5.0.1: hangcheck recover!
[    6.726748] msm_dpu ae01000.display-controller:
[drm:recover_worker] *ERROR* 68.5.0.1: offending task: kwin_wayland
(/usr/bin/kwin_wayland --wayland-fd 7 --socket wayland-0 --xwayland-fd
8 --xwayland-fd 9 --xwayland-display :0 --xwayland-xauthority
/run/user/1000/xauth_UWXqvr --xwayland)
[    6.726754] revision: 0 (68.5.0.1)
[    6.726756] rb 0: fence:    -255/-254
[    6.726757] rptr:     64
[    6.726758] rb wptr:  168
[    6.728919] ------------[ cut here ]------------
[    6.728921] gx_clkctl_gx_gdsc status stuck at 'on'
[    6.728927] WARNING: drivers/clk/qcom/gdsc.c:178 at
gdsc_toggle_logic+0x140/0x160, CPU#2: gpu-worker/230
[    6.728931] Modules linked in: snd_q6apm snd_soc_core snd_compress
snd_pcm snd_timer snd soundcore fastrpc qrtr_smd rpmsg_ctrl
panel_nt36536 joydev mousedev qcom_pd_mapper ucsi_glink
pmic_glink_altmode typec_ucsi aux_hpd_bridge qcom_battmgr aw99706
nvmem_qcom_spmi_sdam nt36532_ts qcom_spmi_temp_alarm fsa4480
regmap_i2c phy_nxp_ptn3222 industrialio rtc_pm8xxx qcom_stats
phy_qcom_qmp_combo aux_bridge typec qcom_q6v5_pas qcom_pil_info
qcom_common phy_qcom_m31_eusb2 qcom_q6v5 qcom_sysmon icc_bwmon
qcom_rng sm3_ce qrtr nvmem_reboot_mode arm_smccc_trng pmic_glink
rng_core
[    6.728963] CPU: 2 UID: 0 PID: 230 Comm: gpu-worker Tainted: G
  W           6.19.6-sm8750+ #5 PREEMPT
[    6.728965] Tainted: [W]=WARN
[    6.728966] Hardware name: LENOVO TB322FC (DT)
[    6.728967] pstate: 61400005 (nZCv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--)
[    6.728969] pc : gdsc_toggle_logic+0x140/0x160
[    6.728970] lr : gdsc_toggle_logic+0x140/0x160
[    6.728971] sp : ffff800080f7b880
[    6.728972] x29: ffff800080f7b880 x28: 0000000000000000 x27: ffff000802674b70
[    6.728975] x26: ffff00080db71080 x25: 0000000000000008 x24: 0000000000000000
[    6.728977] x23: 0000000000000000 x22: 0000000000000000 x21: 0000000000000001
[    6.728979] x20: 0000000000000000 x19: ffffa3c20a6abb98 x18: 000000000000000a
[    6.728981] x17: 0005004800000000 x16: 0000000000050040 x15: 0000000000000000
[    6.728983] x14: 0000000000000000 x13: 6f27207461206b63 x12: 7574732073757461
[    6.728985] x11: 0000000000000058 x10: 0000000000000018 x9 : ffffa3c208f81e50
[    6.728988] x8 : 00000000015fffa8 x7 : 000000000000034e x6 : 0000000000000001
[    6.728990] x5 : ffff000b6e3417c8 x4 : ffff5c4963e92000 x3 : ffff0008089a2f40
[    6.728992] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0008089a2f40
[    6.728994] Call trace:
[    6.728995]  gdsc_toggle_logic+0x140/0x160 (P)
[    6.728997]  gdsc_disable+0x4c/0x190
[    6.728999]  _genpd_power_off+0xa4/0x1a8
[    6.729001]  genpd_power_off.part.0+0x170/0x270
[    6.729003]  genpd_power_off+0x50/0x68
[    6.729005]  genpd_runtime_suspend+0x1e4/0x2e8
[    6.729007]  __rpm_callback+0x50/0x220
[    6.729009]  rpm_callback+0x7c/0x90
[    6.729011]  rpm_suspend+0xe8/0x590
[    6.729014]  rpm_idle+0x128/0x3c0
[    6.729016]  __pm_runtime_idle+0x58/0x100
[    6.729018]  a6xx_gmu_stop+0x74/0x3e0
[    6.729020]  a6xx_gmu_pm_suspend+0x48/0x118
[    6.729022]  adreno_runtime_suspend+0x38/0x68
[    6.729024]  pm_generic_runtime_suspend+0x34/0x60
[    6.729026]  __rpm_callback+0x50/0x220
[    6.729028]  rpm_callback+0x7c/0x90
[    6.729030]  rpm_suspend+0xe8/0x590
[    6.729032]  rpm_idle+0x128/0x3c0
[    6.729034]  __pm_runtime_idle+0x58/0x100
[    6.729037]  a8xx_recover+0x1a0/0x2c0
[    6.729039]  recover_worker+0x244/0x390
[    6.729041]  kthread_worker_fn+0xe0/0x2a0
[    6.729044]  kthread+0x148/0x208
[    6.729045]  ret_from_fork+0x10/0x20
[    6.729047] ---[ end trace 0000000000000000 ]---

Best wishes,
Pengyu

Re: [PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes

[Konrad Dybcio]

On 3/9/26 11:27 AM, Pengyu Luo wrote:
> On Thu, Mar 5, 2026 6:40 PM Taniya Das <taniya.das@oss.qualcomm.com> wrote:
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this
>> is simply a separate block housing the GX GDSC) nodes, required to
>> power up the graphics-related hardware.
>>
>> Make use of it by enabling the associated IOMMU as well. The GPU itself
>> needs some more work and will be enabled later.
>>
>> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> ---
>>
> 
> Hi Taniya and Konrad, GX GDSC stuck at 'on' on my device
> the raw register values are
> 
> 0x3d68024: 0x00000000
> 0x3d68028: 0x00000000

These likely indicate that some clock or voltage rail is not accessible
at the very moment you're reading them back

GPU support for 8750 is not yet upstream (and A830 is somewhat different
vs the supported A840) - there may be something wrong in that sequence.

I heard it's in the works though, so you may be better off waiting a bit.

Konrad

Re: [PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes

[Taniya Das]

On 3/10/2026 7:02 PM, Konrad Dybcio wrote:
> On 3/9/26 11:27 AM, Pengyu Luo wrote:
>> On Thu, Mar 5, 2026 6:40 PM Taniya Das <taniya.das@oss.qualcomm.com> wrote:
>>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>
>>> Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this
>>> is simply a separate block housing the GX GDSC) nodes, required to
>>> power up the graphics-related hardware.
>>>
>>> Make use of it by enabling the associated IOMMU as well. The GPU itself
>>> needs some more work and will be enabled later.
>>>
>>> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>> ---
>>>
>>
>> Hi Taniya and Konrad, GX GDSC stuck at 'on' on my device
>> the raw register values are
>>
>> 0x3d68024: 0x00000000
>> 0x3d68028: 0x00000000
> 
> These likely indicate that some clock or voltage rail is not accessible
> at the very moment you're reading them back
> 
> GPU support for 8750 is not yet upstream (and A830 is somewhat different
> vs the supported A840) - there may be something wrong in that sequence.
> 
> I heard it's in the works though, so you may be better off waiting a bit.
> 

I am checking internally if any required clock is getting turned off and
causing this.

-- 
Thanks,
Taniya Das

Re: [PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes

[Pengyu Luo]

On Tue, Mar 10, 2026 at 9:32 PM Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 3/9/26 11:27 AM, Pengyu Luo wrote:
> > On Thu, Mar 5, 2026 6:40 PM Taniya Das <taniya.das@oss.qualcomm.com> wrote:
> >> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >>
> >> Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this
> >> is simply a separate block housing the GX GDSC) nodes, required to
> >> power up the graphics-related hardware.
> >>
> >> Make use of it by enabling the associated IOMMU as well. The GPU itself
> >> needs some more work and will be enabled later.
> >>
> >> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> >> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> >> ---
> >>
> >
> > Hi Taniya and Konrad, GX GDSC stuck at 'on' on my device
> > the raw register values are
> >
> > 0x3d68024: 0x00000000
> > 0x3d68028: 0x00000000
>
> These likely indicate that some clock or voltage rail is not accessible
> at the very moment you're reading them back
>

It seems to be harmless. In the downstream, they are always zero too.
TB322FC:/ # devmem 0x3d68024
0x00000000
TB322FC:/ # devmem 0x3d68028
0x00000000

In [1], the commit log mentioned
The GX GDSC is modelled to aid the GMU in powering down the GPU in the
event that the GPU crashes.

> GPU support for 8750 is not yet upstream (and A830 is somewhat different
> vs the supported A840) - there may be something wrong in that sequence.
>

Indeed. Chances are that I can't enable gpu. I must reboot again and again to
match the sequence by luck, then I can enable it[2], and I must
disable register protection.(I just noticed the hack from here[3])

> I heard it's in the works though, so you may be better off waiting a bit.
>

Glad to hear that. I am looking forward to it.

Slightly off-topic, do you know if anyone is working on wcn786x/wcn7880,
sm8750 QRD SKU2 V8 Power Grid uses this.

[1]: https://lkml.org/lkml/2024/1/23/1408
[2]: https://postimg.cc/xJr11DK5
[3]: https://github.com/gio3k/linux/commit/f96512ab05a1bcc6b7e82b27f44d907238fc64fb

Best wishes,
Pengyu

Re: [PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes

[Konrad Dybcio]

On 3/12/26 7:40 AM, Pengyu Luo wrote:
> On Tue, Mar 10, 2026 at 9:32 PM Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>>
>> On 3/9/26 11:27 AM, Pengyu Luo wrote:
>>> On Thu, Mar 5, 2026 6:40 PM Taniya Das <taniya.das@oss.qualcomm.com> wrote:
>>>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>>
>>>> Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this
>>>> is simply a separate block housing the GX GDSC) nodes, required to
>>>> power up the graphics-related hardware.
>>>>
>>>> Make use of it by enabling the associated IOMMU as well. The GPU itself
>>>> needs some more work and will be enabled later.
>>>>
>>>> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>>> ---
>>>>
>>>
>>> Hi Taniya and Konrad, GX GDSC stuck at 'on' on my device
>>> the raw register values are
>>>
>>> 0x3d68024: 0x00000000
>>> 0x3d68028: 0x00000000
>>
>> These likely indicate that some clock or voltage rail is not accessible
>> at the very moment you're reading them back
>>
> 
> It seems to be harmless. In the downstream, they are always zero too.
> TB322FC:/ # devmem 0x3d68024
> 0x00000000
> TB322FC:/ # devmem 0x3d68028
> 0x00000000
> 
> In [1], the commit log mentioned
> The GX GDSC is modelled to aid the GMU in powering down the GPU in the
> event that the GPU crashes.
> 
>> GPU support for 8750 is not yet upstream (and A830 is somewhat different
>> vs the supported A840) - there may be something wrong in that sequence.
>>
> 
> Indeed. Chances are that I can't enable gpu. I must reboot again and again to
> match the sequence by luck, then I can enable it[2], and I must
> disable register protection.(I just noticed the hack from here[3])
> 
>> I heard it's in the works though, so you may be better off waiting a bit.
>>
> 
> Glad to hear that. I am looking forward to it.
> 
> Slightly off-topic, do you know if anyone is working on wcn786x/wcn7880,
> sm8750 QRD SKU2 V8 Power Grid uses this.

I don't know. You can try asking on ath12k@lists.infradead.org

Konrad

[PATCH v5 0/3] Add support for GPUCC and GXCLK for SM8750

[Taniya Das]

Support the graphics clock controller for SM8750 for Graphics SW
driver to use the clocks. GXCLKCTL (Graphics GX Clock Controller) is a
block dedicated to managing clocks for the GPU subsystem on GX power
domain. The GX clock controller driver manages only the GX GDSC and the
rest of the resources of the controller are managed by the firmware.

The Graphics GX clock controller is a reuse of the Kaanapali SW driver.

Changes in v5:
- Update 'fw_name' to index for GPUCC driver [Dmitry].
- Add RB-by [Abel] for code and DT changes.
- Link to v4: https://lore.kernel.org/r/20260303-gpucc_sm8750_v2-v4-0-2f28562db7c9@oss.qualcomm.com

Changes in v4:
- Add RB-by [Krzysztof] for GPUCC bindings.
- There was a documentation errata update for GPUCC and updated the
  bindings to capture the MX and CX power-domains and required-opps.
- Update the compatible[qcom,sm8750-gxclkctl] in code which was missed in earlier patch.
- Add the 'use_rpm' for GPUCC.
- Update the power-domain/required-opp handles in GPUCC device node.
- Link to v3: https://lore.kernel.org/r/20260220-gpucc_sm8750_v2-v3-0-6c5408564c3c@oss.qualcomm.com

Changes in v3:
- SM8750 GX controller is reuse of Kaanapali SW driver, update the
  bindings.
- Remove 'qcom,sm8750-gxcc.yaml' as it reuses the driver.
- Cleanup the 'gpucc-sm8750.c' to remove the GX clock controller
  reference.
- Add the corresponding changes in Makefile for gxclkctl-kaanapali.o
- Update the device node for GX clock controller.
- Link to v2: https://lore.kernel.org/all/20250723-topic-8750_gpucc-v2-0-56c93b84c390@oss.qualcomm.com/

Changes in v2:
- gxcc bindings: remove double colon & list the names for power-domains
- Link to v1: https://lore.kernel.org/r/20250708-topic-8750_gpucc-v1-0-86c86a504d47@oss.qualcomm.com

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
Konrad Dybcio (3):
      dt-bindings: clock: qcom: Add SM8750 GPU clocks
      clk: qcom: Add a driver for SM8750 GPU clocks
      arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes

 .../bindings/clock/qcom,kaanapali-gxclkctl.yaml    |   1 +
 .../bindings/clock/qcom,sm8450-gpucc.yaml          |  23 +
 arch/arm64/boot/dts/qcom/sm8750.dtsi               |  68 +++
 drivers/clk/qcom/Kconfig                           |   9 +
 drivers/clk/qcom/Makefile                          |   1 +
 drivers/clk/qcom/gpucc-sm8750.c                    | 473 +++++++++++++++++++++
 drivers/clk/qcom/gxclkctl-kaanapali.c              |   1 +
 include/dt-bindings/clock/qcom,sm8750-gpucc.h      |  50 +++
 8 files changed, 626 insertions(+)
---
base-commit: 350adaf7fde9fdbd9aeed6d442a9ae90c6a3ab97
change-id: 20260217-gpucc_sm8750_v2-866576675fa0

Best regards,
-- 
Taniya Das <taniya.das@oss.qualcomm.com>

[PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes

[Taniya Das]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this
is simply a separate block housing the GX GDSC) nodes, required to
power up the graphics-related hardware.

Make use of it by enabling the associated IOMMU as well. The GPU itself
needs some more work and will be enabled later.

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 68 ++++++++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index f56b1f889b857a28859910f5c4465c8ce3473b00..0e7a343297e3f5d7a8189f50726dc6279078c21c 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -4,7 +4,9 @@
  */
 
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h>
 #include <dt-bindings/clock/qcom,sm8750-gcc.h>
+#include <dt-bindings/clock/qcom,sm8750-gpucc.h>
 #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
 #include <dt-bindings/clock/qcom,sm8750-videocc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
@@ -3001,6 +3003,34 @@ videocc: clock-controller@aaf0000 {
 			#power-domain-cells = <1>;
 		};
 
+		gxclkctl: clock-controller@3d64000 {
+			compatible = "qcom,sm8750-gxclkctl";
+			reg = <0x0 0x03d64000 0x0 0x6000>;
+
+			power-domains = <&rpmhpd RPMHPD_GFX>,
+					<&rpmhpd RPMHPD_GMXC>,
+					<&gpucc GPU_CC_CX_GDSC>;
+
+			#power-domain-cells = <1>;
+		};
+
+		gpucc: clock-controller@3d90000 {
+			compatible = "qcom,sm8750-gpucc";
+			reg = <0x0 0x03d90000 0x0 0x9800>;
+
+			clocks = <&bi_tcxo_div2>,
+				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+
+			power-domains = <&rpmhpd RPMHPD_MX>,
+					<&rpmhpd RPMHPD_CX>;
+			required-opps = <&rpmhpd_opp_low_svs>,
+					<&rpmhpd_opp_low_svs>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
 		pdc: interrupt-controller@b220000 {
 			compatible = "qcom,sm8750-pdc", "qcom,pdc";
 			reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
@@ -4515,6 +4545,44 @@ tpdm_swao_out: endpoint {
 			};
 		};
 
+		adreno_smmu: iommu@3da0000 {
+			compatible = "qcom,sm8750-smmu-500", "qcom,adreno-smmu",
+				     "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x03da0000 0x0 0x40000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+			clock-names = "hlos";
+			power-domains = <&gpucc GPU_CC_CX_GDSC>;
+			dma-coherent;
+		};
+
 		apps_smmu: iommu@15000000 {
 			compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
 			reg = <0x0 0x15000000 0x0 0x100000>;

-- 
2.34.1

Re: [PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes

[Akhil P Oommen]

On 3/5/2026 4:10 PM, Taniya Das wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this
> is simply a separate block housing the GX GDSC) nodes, required to
> power up the graphics-related hardware.
> 
> Make use of it by enabling the associated IOMMU as well. The GPU itself
> needs some more work and will be enabled later.
> 
> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8750.dtsi | 68 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 68 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index f56b1f889b857a28859910f5c4465c8ce3473b00..0e7a343297e3f5d7a8189f50726dc6279078c21c 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -4,7 +4,9 @@
>   */
>  
>  #include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h>
>  #include <dt-bindings/clock/qcom,sm8750-gcc.h>
> +#include <dt-bindings/clock/qcom,sm8750-gpucc.h>
>  #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
>  #include <dt-bindings/clock/qcom,sm8750-videocc.h>
>  #include <dt-bindings/dma/qcom-gpi.h>
> @@ -3001,6 +3003,34 @@ videocc: clock-controller@aaf0000 {
>  			#power-domain-cells = <1>;
>  		};
>  
> +		gxclkctl: clock-controller@3d64000 {
> +			compatible = "qcom,sm8750-gxclkctl";
> +			reg = <0x0 0x03d64000 0x0 0x6000>;
> +
> +			power-domains = <&rpmhpd RPMHPD_GFX>,
> +					<&rpmhpd RPMHPD_GMXC>,
> +					<&gpucc GPU_CC_CX_GDSC>;
> +
> +			#power-domain-cells = <1>;
> +		};
> +
> +		gpucc: clock-controller@3d90000 {
> +			compatible = "qcom,sm8750-gpucc";
> +			reg = <0x0 0x03d90000 0x0 0x9800>;
> +
> +			clocks = <&bi_tcxo_div2>,
> +				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> +				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> +
> +			power-domains = <&rpmhpd RPMHPD_MX>,
> +					<&rpmhpd RPMHPD_CX>;
> +			required-opps = <&rpmhpd_opp_low_svs>,
> +					<&rpmhpd_opp_low_svs>;
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
>  		pdc: interrupt-controller@b220000 {
>  			compatible = "qcom,sm8750-pdc", "qcom,pdc";
>  			reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
> @@ -4515,6 +4545,44 @@ tpdm_swao_out: endpoint {
>  			};
>  		};
>  
> +		adreno_smmu: iommu@3da0000 {

Should we move this node right after the gpucc node to sort based on
address?

-Akhil.

> +			compatible = "qcom,sm8750-smmu-500", "qcom,adreno-smmu",
> +				     "qcom,smmu-500", "arm,mmu-500";
> +			reg = <0x0 0x03da0000 0x0 0x40000>;
> +			#iommu-cells = <2>;
> +			#global-interrupts = <1>;
> +			interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
> +			clock-names = "hlos";
> +			power-domains = <&gpucc GPU_CC_CX_GDSC>;
> +			dma-coherent;
> +		};
> +
>  		apps_smmu: iommu@15000000 {
>  			compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>  			reg = <0x0 0x15000000 0x0 0x100000>;
> 

Re: [PATCH v5 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes

[Konrad Dybcio]

On 3/6/26 10:40 AM, Akhil P Oommen wrote:
> On 3/5/2026 4:10 PM, Taniya Das wrote:
>> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>>
>> Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this
>> is simply a separate block housing the GX GDSC) nodes, required to
>> power up the graphics-related hardware.
>>
>> Make use of it by enabling the associated IOMMU as well. The GPU itself
>> needs some more work and will be enabled later.
>>
>> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> ---
>>  arch/arm64/boot/dts/qcom/sm8750.dtsi | 68 ++++++++++++++++++++++++++++++++++++
>>  1 file changed, 68 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> index f56b1f889b857a28859910f5c4465c8ce3473b00..0e7a343297e3f5d7a8189f50726dc6279078c21c 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> @@ -4,7 +4,9 @@
>>   */
>>  
>>  #include <dt-bindings/clock/qcom,rpmh.h>
>> +#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h>
>>  #include <dt-bindings/clock/qcom,sm8750-gcc.h>
>> +#include <dt-bindings/clock/qcom,sm8750-gpucc.h>
>>  #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
>>  #include <dt-bindings/clock/qcom,sm8750-videocc.h>
>>  #include <dt-bindings/dma/qcom-gpi.h>
>> @@ -3001,6 +3003,34 @@ videocc: clock-controller@aaf0000 {
>>  			#power-domain-cells = <1>;
>>  		};
>>  
>> +		gxclkctl: clock-controller@3d64000 {
>> +			compatible = "qcom,sm8750-gxclkctl";
>> +			reg = <0x0 0x03d64000 0x0 0x6000>;
>> +
>> +			power-domains = <&rpmhpd RPMHPD_GFX>,
>> +					<&rpmhpd RPMHPD_GMXC>,
>> +					<&gpucc GPU_CC_CX_GDSC>;
>> +
>> +			#power-domain-cells = <1>;
>> +		};
>> +
>> +		gpucc: clock-controller@3d90000 {
>> +			compatible = "qcom,sm8750-gpucc";
>> +			reg = <0x0 0x03d90000 0x0 0x9800>;
>> +
>> +			clocks = <&bi_tcxo_div2>,
>> +				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
>> +				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
>> +
>> +			power-domains = <&rpmhpd RPMHPD_MX>,
>> +					<&rpmhpd RPMHPD_CX>;
>> +			required-opps = <&rpmhpd_opp_low_svs>,
>> +					<&rpmhpd_opp_low_svs>;
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +			#power-domain-cells = <1>;
>> +		};
>> +
>>  		pdc: interrupt-controller@b220000 {
>>  			compatible = "qcom,sm8750-pdc", "qcom,pdc";
>>  			reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
>> @@ -4515,6 +4545,44 @@ tpdm_swao_out: endpoint {
>>  			};
>>  		};
>>  
>> +		adreno_smmu: iommu@3da0000 {
> 
> Should we move this node right after the gpucc node to sort based on
> address?

Yes, this might have been a rebase artifact

Konrad