* [PATCH v2] arm64: renesas: r8a779g0: add MFIS node
@ 2026-05-30 8:02 Wolfram Sang
2026-06-02 10:45 ` Geert Uytterhoeven
0 siblings, 1 reply; 5+ messages in thread
From: Wolfram Sang @ 2026-05-30 8:02 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Wolfram Sang, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree
Describe the MFIS core which is used for various tasks including
inter-processor communication. Interrupt numbers look irregular but they
all work as expected on a Renesas R-Car V4H SparrowHawk board.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
Change since v1:
* fixed sorting (Sashiko)
arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 82a7278836e5..08d7210629e5 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -589,6 +589,23 @@ tmu4: timer@ffc00000 {
status = "disabled";
};
+ mfis: system-controller@e6260000 {
+ compatible = "renesas,r8a779g0-mfis";
+ reg = <0 0xe6260000 0 0xf000>;
+ reg-names = "common";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0e", "ch1e", "ch2e", "ch3e", "ch4e", "ch5e", "ch6e", "ch7e", "ch8e", "ch9e",
+ "ch10e", "ch11e";
+ #hwlock-cells = <1>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
tsn0: ethernet@e6460000 {
compatible = "renesas,r8a779g0-ethertsn", "renesas,rcar-gen4-ethertsn";
reg = <0 0xe6460000 0 0x7000>,
--
2.51.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v2] arm64: renesas: r8a779g0: add MFIS node
2026-05-30 8:02 [PATCH v2] arm64: renesas: r8a779g0: add MFIS node Wolfram Sang
@ 2026-06-02 10:45 ` Geert Uytterhoeven
2026-06-02 11:02 ` Wolfram Sang
0 siblings, 1 reply; 5+ messages in thread
From: Geert Uytterhoeven @ 2026-06-02 10:45 UTC (permalink / raw)
To: Wolfram Sang
Cc: linux-renesas-soc, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree
Hi Wolfram,
On Sat, 30 May 2026 at 10:03, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Describe the MFIS core which is used for various tasks including
> inter-processor communication. Interrupt numbers look irregular but they
> all work as expected on a Renesas R-Car V4H SparrowHawk board.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> @@ -589,6 +589,23 @@ tmu4: timer@ffc00000 {
> status = "disabled";
> };
>
> + mfis: system-controller@e6260000 {
> + compatible = "renesas,r8a779g0-mfis";
> + reg = <0 0xe6260000 0 0xf000>;
Why 0xf000 and not 0x10000?
> + reg-names = "common";
> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "ch0e", "ch1e", "ch2e", "ch3e", "ch4e", "ch5e", "ch6e", "ch7e", "ch8e", "ch9e",
This is way too longer for a single line, and the double spacing
doesn't really help (yeah, it does align ch1e and ch11e...).
> + "ch10e", "ch11e";
> + #hwlock-cells = <1>;
> + #mbox-cells = <2>;
> + status = "disabled";
> + };
> +
> tsn0: ethernet@e6460000 {
> compatible = "renesas,r8a779g0-ethertsn", "renesas,rcar-gen4-ethertsn";
> reg = <0 0xe6460000 0 0x7000>,
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v2] arm64: renesas: r8a779g0: add MFIS node
2026-06-02 10:45 ` Geert Uytterhoeven
@ 2026-06-02 11:02 ` Wolfram Sang
2026-06-02 12:25 ` Geert Uytterhoeven
0 siblings, 1 reply; 5+ messages in thread
From: Wolfram Sang @ 2026-06-02 11:02 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: linux-renesas-soc, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree
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Hi Geert,
thanks for the review!
> > + mfis: system-controller@e6260000 {
> > + compatible = "renesas,r8a779g0-mfis";
> > + reg = <0 0xe6260000 0 0xf000>;
>
> Why 0xf000 and not 0x10000?
The sheet listing the memory map has a "MFI - Region 14" entry for
0xe626e000, but no region 15 for 0xe626f000. I thought I play safe.
Can change if you want...
> > + interrupt-names = "ch0e", "ch1e", "ch2e", "ch3e", "ch4e", "ch5e", "ch6e", "ch7e", "ch8e", "ch9e",
>
> This is way too longer for a single line, and the double spacing
> doesn't really help (yeah, it does align ch1e and ch11e...).
You are right, will fix this.
Happy hacking,
Wolfram
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v2] arm64: renesas: r8a779g0: add MFIS node
2026-06-02 11:02 ` Wolfram Sang
@ 2026-06-02 12:25 ` Geert Uytterhoeven
2026-06-02 15:29 ` Wolfram Sang
0 siblings, 1 reply; 5+ messages in thread
From: Geert Uytterhoeven @ 2026-06-02 12:25 UTC (permalink / raw)
To: Wolfram Sang
Cc: linux-renesas-soc, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
Hi Wolfram,
On Tue, 2 Jun 2026 at 13:03, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> > > + mfis: system-controller@e6260000 {
> > > + compatible = "renesas,r8a779g0-mfis";
> > > + reg = <0 0xe6260000 0 0xf000>;
> >
> > Why 0xf000 and not 0x10000?
>
> The sheet listing the memory map has a "MFI - Region 14" entry for
> 0xe626e000, but no region 15 for 0xe626f000. I thought I play safe.
Indeed...
However, according to attachment R-CarV4H_UM_018_AXI-bus_D_r1p30.xlsx,
MFI14 applies to MFIS H'E626_E000 - H'E626_FFFF, thus covers 8 KiB,
i.e. double of the other regions.
> Can change if you want...
Yes please.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v2] arm64: renesas: r8a779g0: add MFIS node
2026-06-02 12:25 ` Geert Uytterhoeven
@ 2026-06-02 15:29 ` Wolfram Sang
0 siblings, 0 replies; 5+ messages in thread
From: Wolfram Sang @ 2026-06-02 15:29 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: linux-renesas-soc, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree
[-- Attachment #1: Type: text/plain, Size: 414 bytes --]
Hi Geert,
> However, according to attachment R-CarV4H_UM_018_AXI-bus_D_r1p30.xlsx,
> MFI14 applies to MFIS H'E626_E000 - H'E626_FFFF, thus covers 8 KiB,
> i.e. double of the other regions.
Thank you for pointing me to that document! I did look for the size of
the memory area but could not find it.
> > Can change if you want...
>
> Yes please.
Will change it.
Happy hacking,
Wolfram
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2026-05-30 8:02 [PATCH v2] arm64: renesas: r8a779g0: add MFIS node Wolfram Sang
2026-06-02 10:45 ` Geert Uytterhoeven
2026-06-02 11:02 ` Wolfram Sang
2026-06-02 12:25 ` Geert Uytterhoeven
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