* [PATCH v9 1/5] soc: qcom: ice: Add OPP-based clock scaling support for ICE
2026-05-24 19:25 [PATCH v9 0/5] Enable ICE clock scaling Abhinaba Rakshit
@ 2026-05-24 19:25 ` Abhinaba Rakshit
2026-05-24 19:25 ` [PATCH v9 2/5] ufs: host: Add ICE clock scaling during UFS clock changes Abhinaba Rakshit
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Abhinaba Rakshit @ 2026-05-24 19:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-arm-msm, linux-kernel, linux-scsi, linux-mmc, devicetree,
Abhinaba Rakshit
Register optional operation-points-v2 table for ICE device
during device probe. Attach the OPP-table with only the ICE
core clock. Since, dtbinding is on a trasition phase to include
iface clock and clock-names, attaching the opp-table to core clock
remains optional such that it does not cause probe failures.
Introduce clock scaling API qcom_ice_scale_clk which scale ICE
core clock based on the target frequency provided and if a valid
OPP-table is registered. Use round_ceil passed to decide on the
rounding of the clock freq against OPP-table. Clock scaling is
disabled when a valid OPP-table is not registered.
This ensures when an ICE-device specific OPP table is available,
use the PM OPP framework to manage frequency scaling and maintain
proper power-domain constraints.
Also, ensure to drop the votes in suspend to prevent power/thermal
retention. Subsequently restore the frequency in resume from
core_clk_freq which stores the last ICE core clock operating frequency.
Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
drivers/soc/qcom/ice.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++
include/soc/qcom/ice.h | 2 ++
2 files changed, 95 insertions(+)
diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c
index bf4ab2d9e5c0360d8fe6135cc35f93b6b09e7a0e..7b98afec71f6135f580f82497127b0db7e70a6da 100644
--- a/drivers/soc/qcom/ice.c
+++ b/drivers/soc/qcom/ice.c
@@ -16,6 +16,7 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
#include <linux/firmware/qcom/qcom_scm.h>
@@ -112,6 +113,8 @@ struct qcom_ice {
bool use_hwkm;
bool hwkm_init_complete;
u8 hwkm_version;
+ unsigned long core_clk_freq;
+ bool has_opp;
};
static bool qcom_ice_check_supported(struct qcom_ice *ice)
@@ -311,6 +314,10 @@ int qcom_ice_resume(struct qcom_ice *ice)
struct device *dev = ice->dev;
int err;
+ /* Restore the ICE core clk freq */
+ if (ice->has_opp && ice->core_clk_freq)
+ dev_pm_opp_set_rate(ice->dev, ice->core_clk_freq);
+
err = clk_prepare_enable(ice->core_clk);
if (err) {
dev_err(dev, "Failed to enable core clock: %d\n", err);
@@ -331,6 +338,11 @@ int qcom_ice_suspend(struct qcom_ice *ice)
{
clk_disable_unprepare(ice->iface_clk);
clk_disable_unprepare(ice->core_clk);
+
+ /* Drop the clock votes while suspend */
+ if (ice->has_opp)
+ dev_pm_opp_set_rate(ice->dev, 0);
+
ice->hwkm_init_complete = false;
return 0;
@@ -556,6 +568,51 @@ int qcom_ice_import_key(struct qcom_ice *ice,
}
EXPORT_SYMBOL_GPL(qcom_ice_import_key);
+/**
+ * qcom_ice_scale_clk() - Scale ICE clock for DVFS-aware operations
+ * @ice: ICE driver data
+ * @target_freq: requested frequency in Hz
+ * @round_ceil: when true, selects nearest freq >= @target_freq;
+ * otherwise, selects nearest freq <= @target_freq
+ *
+ * Selects an OPP frequency based on @target_freq and the rounding direction
+ * specified by @round_ceil, then programs it using dev_pm_opp_set_rate(),
+ * including any voltage or power-domain transitions handled by the OPP
+ * framework. Updates ice->core_clk_freq on success.
+ *
+ * Return: 0 on success; -EOPNOTSUPP if no OPP table; or error from
+ * dev_pm_opp_set_rate()/OPP lookup.
+ */
+int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq,
+ bool round_ceil)
+{
+ unsigned long ice_freq = target_freq;
+ struct dev_pm_opp *opp;
+ int ret;
+
+ if (!ice->has_opp)
+ return -EOPNOTSUPP;
+
+ if (round_ceil)
+ opp = dev_pm_opp_find_freq_ceil(ice->dev, &ice_freq);
+ else
+ opp = dev_pm_opp_find_freq_floor(ice->dev, &ice_freq);
+
+ if (IS_ERR(opp))
+ return PTR_ERR(opp);
+ dev_pm_opp_put(opp);
+
+ ret = dev_pm_opp_set_rate(ice->dev, ice_freq);
+ if (ret) {
+ dev_err(ice->dev, "Unable to scale ICE clock rate\n");
+ return ret;
+ }
+ ice->core_clk_freq = ice_freq;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(qcom_ice_scale_clk);
+
static struct qcom_ice *qcom_ice_create(struct device *dev,
void __iomem *base)
{
@@ -731,6 +788,7 @@ static int qcom_ice_probe(struct platform_device *pdev)
{
struct qcom_ice *engine;
void __iomem *base;
+ int err;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base)) {
@@ -742,6 +800,41 @@ static int qcom_ice_probe(struct platform_device *pdev)
if (IS_ERR(engine))
return PTR_ERR(engine);
+ /* qcom_ice_create() may return NULL if scm calls are not available */
+ if (!engine)
+ return -EOPNOTSUPP;
+
+ err = devm_pm_opp_set_clkname(&pdev->dev, "core");
+ if (err && err != -ENOENT) {
+ dev_err(&pdev->dev, "Unable to set core clkname to OPP-table\n");
+ return err;
+ }
+
+ /* OPP table is optional */
+ err = devm_pm_opp_of_add_table(&pdev->dev);
+ if (err && err != -ENODEV) {
+ dev_err(&pdev->dev, "Invalid OPP table in Device tree\n");
+ return err;
+ }
+
+ /*
+ * The OPP table is optional. devm_pm_opp_of_add_table() returns
+ * -ENODEV when no OPP table is present in DT, which is not treated
+ * as an error. Therefore, track successful OPP registration only
+ * when err is not -ENODEV.
+ */
+ if (err == -ENODEV)
+ dev_info(&pdev->dev, "ICE OPP table is not registered, please update your DT\n");
+ else
+ engine->has_opp = true;
+
+ /*
+ * Store the core clock rate for suspend resume cycles,
+ * against OPP aware DVFS operations. core_clk_freq will
+ * have a valid value only for non-legacy bindings.
+ */
+ engine->core_clk_freq = clk_get_rate(engine->core_clk);
+
platform_set_drvdata(pdev, engine);
return 0;
diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h
index 4bee553f0a59d86ec6ce20f7c7b4bce28a706415..4eb58a264d416e71228ed4b13e7f53c549261fdc 100644
--- a/include/soc/qcom/ice.h
+++ b/include/soc/qcom/ice.h
@@ -30,5 +30,7 @@ int qcom_ice_import_key(struct qcom_ice *ice,
const u8 *raw_key, size_t raw_key_size,
u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]);
struct qcom_ice *devm_of_qcom_ice_get(struct device *dev);
+int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq,
+ bool round_ceil);
#endif /* __QCOM_ICE_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v9 2/5] ufs: host: Add ICE clock scaling during UFS clock changes
2026-05-24 19:25 [PATCH v9 0/5] Enable ICE clock scaling Abhinaba Rakshit
2026-05-24 19:25 ` [PATCH v9 1/5] soc: qcom: ice: Add OPP-based clock scaling support for ICE Abhinaba Rakshit
@ 2026-05-24 19:25 ` Abhinaba Rakshit
2026-05-24 19:25 ` [PATCH v9 3/5] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init Abhinaba Rakshit
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Abhinaba Rakshit @ 2026-05-24 19:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-arm-msm, linux-kernel, linux-scsi, linux-mmc, devicetree,
Abhinaba Rakshit
Implement ICE (Inline Crypto Engine) clock scaling in sync with
UFS controller clock scaling. This ensures that the ICE operates at
an appropriate frequency when the UFS clocks are scaled up or down,
improving performance and maintaining stability for crypto operations.
For scale_up operation ensure to pass ~round_ceil (round_floor)
and vice-versa for scale_down operations.
Incase of OPP scaling is not supported by ICE, ensure to not prevent
devfreq for UFS, as ICE OPP-table is optional.
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
drivers/ufs/host/ufs-qcom.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index bc037db46624adaf494d08f6c2a2c55c9ed24606..b248d8db8997341117d014320d22fdf1ae7b89a6 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -306,6 +306,15 @@ static int ufs_qcom_ice_prepare_key(struct blk_crypto_profile *profile,
return qcom_ice_prepare_key(host->ice, lt_key, lt_key_size, eph_key);
}
+static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, unsigned long target_freq,
+ bool round_ceil)
+{
+ if (host->hba->caps & UFSHCD_CAP_CRYPTO)
+ return qcom_ice_scale_clk(host->ice, target_freq, round_ceil);
+
+ return 0;
+}
+
static const struct blk_crypto_ll_ops ufs_qcom_crypto_ops = {
.keyslot_program = ufs_qcom_ice_keyslot_program,
.keyslot_evict = ufs_qcom_ice_keyslot_evict,
@@ -340,6 +349,12 @@ static void ufs_qcom_config_ice_allocator(struct ufs_qcom_host *host)
{
}
+static int ufs_qcom_ice_scale_clk(struct ufs_qcom_host *host, unsigned long target_freq,
+ bool round_ceil)
+{
+ return 0;
+}
+
#endif
static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
@@ -1933,6 +1948,12 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up,
return err;
}
+ err = ufs_qcom_ice_scale_clk(host, target_freq, !scale_up);
+ if (err && err != -EOPNOTSUPP) {
+ ufshcd_uic_hibern8_exit(hba);
+ return err;
+ }
+
ufs_qcom_icc_update_bw(host);
ufshcd_uic_hibern8_exit(hba);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v9 3/5] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init
2026-05-24 19:25 [PATCH v9 0/5] Enable ICE clock scaling Abhinaba Rakshit
2026-05-24 19:25 ` [PATCH v9 1/5] soc: qcom: ice: Add OPP-based clock scaling support for ICE Abhinaba Rakshit
2026-05-24 19:25 ` [PATCH v9 2/5] ufs: host: Add ICE clock scaling during UFS clock changes Abhinaba Rakshit
@ 2026-05-24 19:25 ` Abhinaba Rakshit
2026-05-24 19:25 ` [PATCH v9 4/5] arm64: dts: qcom: kodiak: Add OPP-table for ICE UFS and ICE eMMC nodes Abhinaba Rakshit
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Abhinaba Rakshit @ 2026-05-24 19:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-arm-msm, linux-kernel, linux-scsi, linux-mmc, devicetree,
Abhinaba Rakshit, Konrad Dybcio
MMC controller lacks a clock scaling mechanism, unlike the UFS
controller. By default, the MMC controller is set to TURBO mode
during probe, but the ICE clock remains at XO frequency,
leading to read/write performance degradation on eMMC.
To address this, set the ICE clock to TURBO during sdhci_msm_ice_init
to align it with the controller clock. This ensures consistent
performance and avoids mismatches between the controller
and ICE clock frequencies.
For platforms where ICE is represented as a separate device,
use the OPP framework to vote for TURBO mode, maintaining
proper voltage and power domain constraints.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
drivers/mmc/host/sdhci-msm.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 633462c0be5f43c06c497520faf9f6fa03fa652a..cabcb75ebbac392eb6dce7ac8c756724ef9e1b49 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -1901,6 +1901,8 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
#ifdef CONFIG_MMC_CRYPTO
static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */
+static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, unsigned long target_freq,
+ bool round_ceil); /* forward decl */
static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
struct cqhci_host *cq_host)
@@ -1959,6 +1961,11 @@ static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
}
mmc->caps2 |= MMC_CAP2_CRYPTO;
+
+ err = sdhci_msm_ice_scale_clk(msm_host, ULONG_MAX, false);
+ if (err && err != -EOPNOTSUPP)
+ dev_warn(dev, "Unable to boost ICE clock to TURBO\n");
+
return 0;
}
@@ -1984,6 +1991,16 @@ static int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
return 0;
}
+static int sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host,
+ unsigned long target_freq,
+ bool round_ceil)
+{
+ if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
+ return qcom_ice_scale_clk(msm_host->ice, target_freq, round_ceil);
+
+ return 0;
+}
+
static inline struct sdhci_msm_host *
sdhci_msm_host_from_crypto_profile(struct blk_crypto_profile *profile)
{
@@ -2149,6 +2166,13 @@ sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
{
return 0;
}
+
+static inline int
+sdhci_msm_ice_scale_clk(struct sdhci_msm_host *msm_host, unsigned long target_freq,
+ bool round_ceil)
+{
+ return 0;
+}
#endif /* !CONFIG_MMC_CRYPTO */
/*****************************************************************************\
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v9 4/5] arm64: dts: qcom: kodiak: Add OPP-table for ICE UFS and ICE eMMC nodes
2026-05-24 19:25 [PATCH v9 0/5] Enable ICE clock scaling Abhinaba Rakshit
` (2 preceding siblings ...)
2026-05-24 19:25 ` [PATCH v9 3/5] mmc: sdhci-msm: Set ICE clk to TURBO at sdhci ICE init Abhinaba Rakshit
@ 2026-05-24 19:25 ` Abhinaba Rakshit
2026-05-24 19:25 ` [PATCH v9 5/5] arm64: dts: qcom: monaco: " Abhinaba Rakshit
2026-05-25 7:06 ` [PATCH v9 0/5] Enable ICE clock scaling Abhinaba Rakshit
5 siblings, 0 replies; 7+ messages in thread
From: Abhinaba Rakshit @ 2026-05-24 19:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-arm-msm, linux-kernel, linux-scsi, linux-mmc, devicetree,
Abhinaba Rakshit
Qualcomm Inline Crypto Engine (ICE) platform driver now, supports
an optional OPP-table.
Add OPP-table for ICE UFS and ICE eMMC device nodes for Kodiak
platform.
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 42 ++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index a8260f695058525e77653fd8005fd3d250715a91..8a8328c5dfa88b69594fca926f4f7c1825416259 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -1087,6 +1087,27 @@ sdhc_ice: crypto@7c8000 {
clock-names = "core",
"iface";
power-domains = <&rpmhpd SC7280_CX>;
+
+ operating-points-v2 = <&ice_mmc_opp_table>;
+
+ ice_mmc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
};
gpi_dma0: dma-controller@900000 {
@@ -2597,6 +2618,27 @@ ice: crypto@1d88000 {
clock-names = "core",
"iface";
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+ operating-points-v2 = <&ice_opp_table>;
+
+ ice_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
cryptobam: dma-controller@1dc4000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v9 5/5] arm64: dts: qcom: monaco: Add OPP-table for ICE UFS and ICE eMMC nodes
2026-05-24 19:25 [PATCH v9 0/5] Enable ICE clock scaling Abhinaba Rakshit
` (3 preceding siblings ...)
2026-05-24 19:25 ` [PATCH v9 4/5] arm64: dts: qcom: kodiak: Add OPP-table for ICE UFS and ICE eMMC nodes Abhinaba Rakshit
@ 2026-05-24 19:25 ` Abhinaba Rakshit
2026-05-25 7:06 ` [PATCH v9 0/5] Enable ICE clock scaling Abhinaba Rakshit
5 siblings, 0 replies; 7+ messages in thread
From: Abhinaba Rakshit @ 2026-05-24 19:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-arm-msm, linux-kernel, linux-scsi, linux-mmc, devicetree,
Abhinaba Rakshit
Qualcomm Inline Crypto Engine (ICE) platform driver now, supports
an optional OPP-table.
Add OPP-table for ICE UFS and ICE eMMC device nodes for Monaco
platform.
Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/monaco.dtsi | 37 ++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 805feb481943e0684162048b5e665b056588095f..89586a6fda70dde16007fb9d3d6a1fc4459c58ed 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -2742,6 +2742,27 @@ ice: crypto@1d88000 {
clock-names = "core",
"iface";
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
+ operating-points-v2 = <&ice_opp_table>;
+
+ ice_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-201600000 {
+ opp-hz = /bits/ 64 <201600000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
crypto: crypto@1dfa000 {
@@ -4878,6 +4899,22 @@ sdhc_ice: crypto@87c8000 {
clock-names = "core",
"iface";
power-domains = <&rpmhpd RPMHPD_CX>;
+
+ operating-points-v2 = <&ice_mmc_opp_table>;
+
+ ice_mmc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
};
usb_1_hsphy: phy@8904000 {
--
2.34.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v9 0/5] Enable ICE clock scaling
2026-05-24 19:25 [PATCH v9 0/5] Enable ICE clock scaling Abhinaba Rakshit
` (4 preceding siblings ...)
2026-05-24 19:25 ` [PATCH v9 5/5] arm64: dts: qcom: monaco: " Abhinaba Rakshit
@ 2026-05-25 7:06 ` Abhinaba Rakshit
5 siblings, 0 replies; 7+ messages in thread
From: Abhinaba Rakshit @ 2026-05-25 7:06 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam,
James E.J. Bottomley, Martin K. Petersen, Adrian Hunter,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neeraj Soni, Harshal Dev, Kuldeep Singh
Cc: linux-arm-msm, linux-kernel, linux-scsi, linux-mmc, devicetree,
Konrad Dybcio
On Mon, May 25, 2026 at 12:55:47AM +0530, Abhinaba Rakshit wrote:
> Introduce support for dynamic clock scaling of the ICE (Inline Crypto Engine)
> using the OPP framework. During ICE device probe, the driver now attempts to
> parse an optional OPP table from the ICE-specific device tree node for
> DVFS-aware operations. API qcom_ice_scale_clk is exposed by ICE driver
> and is invoked by UFS host controller driver in response to clock scaling
> requests, ensuring coordination between ICE and host controller.
>
> For MMC controllers that do not support clock scaling, the ICE clock frequency
> is kept aligned with the MMC controller’s clock rate (TURBO) to ensure
> consistent operation.
>
> Dynamic clock scaling based on OPP tables enables better power-performance
> trade-offs. By adjusting ICE clock frequencies according to workload and power
> constraints, the system can achieve higher throughput when needed and
> reduce power consumption during idle or low-load conditions.
>
> The OPP table remains optional, absence of the table will not cause
> probe failure. However, in the absence of an OPP table, ICE clocks will
> remain at their default rates, which may limit performance under
> high-load scenarios or prevent performance optimizations during idle periods.
>
> Testing:
> * dtbs_check
> * Validated on Rb3Gen2 and qcs8300-ride-sx
>
> Merge Order and Dependencies
> ============================
>
> Patch 2 is dependent on patch 1 for the qcom_ice_scale_clk API to be available.
> Patch 3 is dependent on patch 1 for the qcom_ice_scale_clk API to be available.
>
> Due to dependency, all patches should go through Qcom SoC tree.
>
> This patchset supersedes earlier ICE clock scaling series (v1–v8) with updated dependencies.
> Hence, this patchset also *Depends-On* the following patchseries:
>
> [1] Add explicit clock vote and enable power-domain for QCOM-ICE
> https://lore.kernel.org/all/20260416-qcom_ice_power_and_clk_vote-v5-0-5ccf5d7e2846@oss.qualcomm.com/
>
> [2] Enable Inline crypto engine for kodiak and monaco
> https://lore.kernel.org/all/20260310113557.348502-1-neeraj.soni@oss.qualcomm.com/
>
> [3] Enable iface clock and power domain for kodiak and monaco ice sdhc
> https://lore.kernel.org/linux-arm-msm/20260409-ice_emmc_clock_addition-v2-0-90bbcc057361@oss.qualcomm.com/
>
> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
> ---
> Changes in v9:
> - Kodiak ICE eMMC OPP-table entry corresponding to 300MHz is updated with SVS_L1.
> - Add 75MHz for Monaco ICE eMMC OPP-table.
> - Fix error handling and initialization of has_opp variable.
> - Pass ULONG_MAX as target freq instead of INT_MAX from sdhci_ice_init as it better adjusts the data-type of
> the function qcom_ice_scale_clk.
> - Link to v8: https://lore.kernel.org/r/20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com
Hello,
It appears that some of the dependencies for this patch series have already been picked,
and there have also been recent changes in the ICE driver that conflict with my patches.
Please avoid picking this patch series for now. I will post a new version based on the
tip of linux-next, with the ICE driver conflicts resolved.
Abhinaba Rakshit
^ permalink raw reply [flat|nested] 7+ messages in thread