From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: "Inochi Amaoto" <inochiama@gmail.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Yixun Lan" <dlan@kernel.org>, "Paul Walmsley" <pjw@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Christian Bruel" <christian.bruel@foss.st.com>,
"Vincent Guittot" <vincent.guittot@linaro.org>,
"Senchuan Zhang" <zhangsenchuan@eswincomputing.com>,
"Alex Elder" <elder@riscstar.com>,
"Nam Cao" <namcao@linutronix.de>,
"Siddharth Vadapalli" <s-vadapalli@ti.com>,
"Randolph Lin" <randolph@andestech.com>,
"Vidya Sagar" <vidyas@nvidia.com>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
spacemit@lists.linux.dev, "Yixun Lan" <dlan@gentoo.org>,
"Longbin Li" <looong.bin@gmail.com>
Subject: Re: [PATCH v2 5/5] PCI: spacemit-k1: Add Spacemit K3 PCIe host controller support
Date: Tue, 9 Jun 2026 17:49:23 +0300 [thread overview]
Message-ID: <aign88JV3k_wn2HK@ashevche-desk.local> (raw)
In-Reply-To: <wztjdv4t5cn7djj3jyvheest7rn5nr2g3efzwods2fz3yy5wn2@hbl644sd6fst>
On Tue, Jun 09, 2026 at 07:48:12PM +0530, Manivannan Sadhasivam wrote:
> On Sun, May 17, 2026 at 09:48:40AM +0800, Inochi Amaoto wrote:
> > The PCIe controller on Spacemit K3 is almost a standard Synopsys
> > DesignWare PCIe IP with extra link and reset control. Unlike
> > the PCIe controller on K1, this controller supports external MSI
> > interrupt controller and can use multiple PHYs at the same time.
> >
> > Add driver to support PCIe controller on Spacemit K3 PCIe.
...
> > +static int k3_pcie_enable_phy(struct k1_pcie *pcie)
> > +{
> > + int i, ret;
No need to have i signed.
> > +
> > + for (i = 0; i < pcie->phy_count; i++) {
> > + ret = phy_init(pcie->phy[i]);
> > + if (ret)
> > + goto err_phy;
> > + }
> > +
> > + return 0;
> > +
> > +err_phy:
> > + while (--i >= 0)
while (i--)
is shorter form of the same.
> > + phy_exit(pcie->phy[i]);
> > +
...
> > + regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC,
> > + PCIE_IGNORE_PERSTN | PCIE_PERSTN_OE | PCIE_PERSTN_OUT);
> > + usleep_range(1000, 2000);
fsleep(1 * USEC_PER_MSEC)
> > + regmap_clear_bits(k1->pmu, k1->pmu_off + PCIE_CONTROL_LOGIC, PCIE_PERSTN_OUT);
> > +
> > + msleep(PCIE_T_PVPERL_MS);
...
> > + int i;
Why is 'i' signed?
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-06-09 14:49 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-17 1:48 [PATCH v2 0/5] riscv: spacemit: Add PCIe RC controller support for K3 Inochi Amaoto
2026-05-17 1:48 ` [PATCH v2 1/5] PCI: spacemit-k1: Add device data support Inochi Amaoto
2026-05-17 1:48 ` [PATCH v2 2/5] PCI: spacemit-k1: Add multiple PHY handles support Inochi Amaoto
2026-05-17 8:07 ` Andy Shevchenko
2026-05-18 1:18 ` Inochi Amaoto
2026-06-09 16:11 ` Alex Elder
2026-05-17 1:48 ` [PATCH v2 3/5] dt-bindings: PCI: snps,dw-pcie: Add msi-parent for MSI handle check Inochi Amaoto
2026-05-17 1:48 ` [PATCH v2 4/5] dt-bindings: PCI: spacemit: Introduce Spacemit K3 PCIe host controller Inochi Amaoto
2026-05-17 2:48 ` sashiko-bot
2026-05-17 4:38 ` Inochi Amaoto
2026-06-01 22:42 ` Rob Herring
2026-06-03 9:24 ` Inochi Amaoto
2026-06-09 14:03 ` Manivannan Sadhasivam
2026-06-09 16:11 ` Alex Elder
2026-05-17 1:48 ` [PATCH v2 5/5] PCI: spacemit-k1: Add Spacemit K3 PCIe host controller support Inochi Amaoto
2026-05-17 3:16 ` sashiko-bot
2026-05-17 4:41 ` Inochi Amaoto
2026-06-09 14:18 ` Manivannan Sadhasivam
2026-06-09 14:49 ` Andy Shevchenko [this message]
2026-06-09 16:11 ` Alex Elder
2026-06-09 16:11 ` Alex Elder
2026-06-22 8:50 ` Inochi Amaoto
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