Re: [PATCH v2 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Matthew Leung <matthew.leung@oss.qualcomm.com>]

On Sun, Jun 07, 2026 at 11:01:10PM +0300, Dmitry Baryshkov wrote:
> On Fri, May 29, 2026 at 01:10:08AM +0000, Matthew Leung wrote:
> > Add a dedicated schema for the PCIe controllers found on the Hawi
> > platform.
> > 
> > Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
> > ---
> >  .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 204 +++++++++++++++++++++
> >  1 file changed, 204 insertions(+)
> > 
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/qcom,hawi-gcc.h>
> > +    #include <dt-bindings/gpio/gpio.h>
> > +    #include <dt-bindings/interconnect/qcom,icc.h>
> > +    #include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
> 
> Stop referencing clocks and interconnect header files. Replace used nocs
> with ephemeral values.
> 
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> 
> Not looking around should be a sin. Take a look at other Qualcomm PCIe
> bindings. Compare them to yours. Then fix yours to follow.
> 
> Hint: the extra soc node is useless. This is just an example, so use the
> default, 1 cells for address and size.

Thank you for the feedback. This new binding follows the examples set in
the qcom,pcie-sm8x50 bindings and retains the same formatting (extra soc
node and header references).

I understand the example can be simplified with your suggestions but
want additional confirmation that these will be the convention for new
bindings going forward.

> 
> > +
> > +        pcie@1c00000 {
> > +            compatible = "qcom,hawi-pcie";
> > +            reg = <0 0x01c00000 0 0x3000>,
> > +                  <0 0x40000000 0 0xf1d>,
> > +                  <0 0x40000f20 0 0xa8>,
> > +                  <0 0x40001000 0 0x1000>,
> > +                  <0 0x40100000 0 0x100000>;
> > +            reg-names = "parf", "dbi", "elbi", "atu", "config";
> > +            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> > +                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
> > +
> > +            bus-range = <0x00 0xff>;
> > +            device_type = "pci";
> > +            linux,pci-domain = <0>;
> > +            num-lanes = <2>;
> > +
> > +            #address-cells = <3>;
> > +            #size-cells = <2>;
> > +
> > +            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> 
> <&gcc_pcie_0_aux_clk>, etc.
> 
> > +                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> > +                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> > +                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> > +                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> > +                     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
> > +                     <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
> 
> -- 
> With best wishes
> Dmitry