Re: [PATCH 11/12] rtc: rzn1: use FIELD_PREP/FIELD_GET and GENMASK for register access

[Wolfram Sang <wsa+renesas@sang-engineering.com>]

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Hi,

Sashiko found issues with your patch. I curated the list and left only those
which I see as valid. Please have a look at these issues.

Thank you and happy hacking,

   Wolfram

> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Low] Incomplete refactoring: open-coded logic remains for RZN1_RTC_SUBU_RTCA0FX
> --
> 
> commit 2e16f66c80c483d619655d20fbb859a42e9d1b6d
> Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> rtc: rzn1: use FIELD_PREP/FIELD_GET and GENMASK for register access
> 
> This commit replaces open-coded shift and mask operations with the bitfield
> API in the rzn1 RTC driver to improve readability and match the hardware
> manual.
> 
> > diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c
> > index c7ef3c81180f4..9f9cf9882fc49 100644
> > --- a/drivers/rtc/rtc-rzn1.c
> > +++ b/drivers/rtc/rtc-rzn1.c
> [ ... ]
> > @@ -306,7 +312,7 @@ static int rzn1_rtc_read_offset(struct device *dev, long *offset)
> >  	val = readl(rtc->base + RZN1_RTC_SUBU);
> >  	ppb_per_step = val & RZN1_RTC_SUBU_DEV ? 1017 : 3051;
> >  	subtract = val & RZN1_RTC_SUBU_DECR;
> > -	val &= 0x3F;
> > +	val = FIELD_GET(RZN1_RTC_SUBU_RTCA0FX, val);
> >  
> >  	if (!val)
> >  		*offset = 0;
> 
> [Severity: Low]
> Since the stated goal of this patch is to replace open-coded masks with the
> bitfield API, should the remaining 0x3F masks for this register be updated as
> well?
> 
> In rzn1_rtc_read_offset() just below this change, there is still an explicit
> mask used when calculating the offset:
> 
> 	*offset = -(((~val) & 0x3F) + 1) * ppb_per_step;
> 
> Additionally, it looks like the write path in rzn1_rtc_set_offset() was missed
> entirely during the refactoring. It continues to use open-coded logic rather
> than FIELD_PREP when constructing the RZN1_RTC_SUBU register:
> 
> 	subu |= RZN1_RTC_SUBU_DECR;
> 	subu |= (~(-steps - 1)) & 0x3F;
> 
> Would it make sense to update these locations so the bitfield access is
> consistent across the driver?
> 
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20260615154805.1619693-1-prabhakar.mahadev-lad.rj@bp.renesas.com?part=11

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