* [PATCH v2 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings
2026-07-01 13:11 [PATCH v2 0/5] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
@ 2026-07-01 13:11 ` Ioana Ciornei
2026-07-01 14:27 ` Frank Li
2026-07-01 13:11 ` [PATCH v2 2/5] arm64: dts: ls1028a: describe the Lynx 10G SerDes Ioana Ciornei
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Ioana Ciornei @ 2026-07-01 13:11 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes
instance is present in the compatible string, to allow reliable per-lane
capability detection and per-lane customization of electrical properties.
The modern bindings are backward-incompatible with old kernels, due
to the consumer phandles being either in one form or in another, as
explained here:
https://lore.kernel.org/lkml/20250930140735.mvo3jii7wgmzh2bs@skbuf/
One of the major differences between the LX2160A and LX2162A is the
SerDes. So far, LX2162A has used fsl-lx2160a-rev2.dtsi, but we need to
split that up even further, and derive a fsl-lx2162a.dtsi which
overrides the SerDes properties.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Enable serdes_1 on all board DTs that has consumers for it.
- Use the proper name for serdes_3 in fsl-lx2162a.dtsi.
- Remove paragraph from commit message which mentioned some consumer
changes that are no longer needed nor part of the commit.
---
.../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 +
.../dts/freescale/fsl-lx2160a-half-twins.dts | 4 +
.../boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 +
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 150 +++++++++++++++++-
.../dts/freescale/fsl-lx2162a-clearfog.dts | 6 +-
.../boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +-
.../arm64/boot/dts/freescale/fsl-lx2162a.dtsi | 24 +++
7 files changed, 190 insertions(+), 4 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index 4bc151d721dd..1f946d3a4ec0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -135,6 +135,10 @@ &sata3 {
status = "okay";
};
+&serdes_1 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
index d16e27307275..954b9955b1b3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
@@ -805,6 +805,10 @@ &rgmii_phy1 {
status = "disabled";
};
+&serdes_1 {
+ status = "okay";
+};
+
&serdes_2 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 935f421475ac..a40a968b9533 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -329,6 +329,10 @@ &uart0 {
status = "okay";
};
+&serdes_1 {
+ status = "okay";
+};
+
&uart1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 1d73abffa6b7..a687eb3e3190 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -621,17 +621,163 @@ soc: soc {
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+ /* Note on the interpretation of SerDes lane numbering from
+ * LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]:
+ * The letters (A-H) correspond to logical lane numbers in the
+ * SerDes register map (lane A's registers start with LNAGCR0),
+ * while the numbers (0-7) correspond to physical lanes as
+ * routed to pins. SerDes block #1 is flipped in the LX2160A
+ * floorplan (logical lane A goes to physical lane 7's pins),
+ * while SerDes blocks #2 and #3 are not. The lanes below are
+ * listed right to left when looking at that table.
+ * Both the numbers and the letters are according to the logical
+ * numbering scheme, and do not account for the flipping.
+ */
serdes_1: phy@1ea0000 {
- compatible = "fsl,lynx-28g";
+ compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g";
reg = <0x0 0x1ea0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
#phy-cells = <1>;
+ status = "disabled";
+
+ serdes_1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
};
serdes_2: phy@1eb0000 {
- compatible = "fsl,lynx-28g";
+ compatible = "fsl,lx2160a-serdes2", "fsl,lynx-28g";
reg = <0x0 0x1eb0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
+
+ serdes_2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
+ };
+
+ serdes_3: phy@1ec0000 {
+ compatible = "fsl,lx2160a-serdes3";
+ reg = <0x0 0x1ec0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ #phy-cells = <1>;
+
+ serdes_3_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
};
crypto: crypto@8000000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index 99ee2b1c0f13..63f161610caa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -8,7 +8,7 @@
#include <dt-bindings/leds/common.h>
-#include "fsl-lx2160a-rev2.dtsi"
+#include "fsl-lx2162a.dtsi"
#include "fsl-lx2162a-sr-som.dtsi"
/ {
@@ -367,6 +367,10 @@ &pcs_mdio18 {
status = "okay";
};
+&serdes_1 {
+ status = "okay";
+};
+
&serdes_2 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
index 7a595fddc027..0ba56b9819ac 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include "fsl-lx2160a-rev2.dtsi"
+#include "fsl-lx2162a.dtsi"
/ {
model = "NXP Layerscape LX2162AQDS";
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
new file mode 100644
index 000000000000..0e92ac6acd92
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree Include file for Layerscape-LX2162A family SoC.
+//
+// Copyright 2025 NXP
+
+#include "fsl-lx2160a-rev2.dtsi"
+
+&serdes_1 {
+ compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g";
+
+ /delete-node/ phy@0;
+ /delete-node/ phy@1;
+ /delete-node/ phy@2;
+ /delete-node/ phy@3;
+};
+
+&serdes_2 {
+ compatible = "fsl,lx2162a-serdes2", "fsl,lynx-28g";
+};
+
+&soc {
+ /delete-node/ phy@1ec0000;
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings
2026-07-01 13:11 ` [PATCH v2 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings Ioana Ciornei
@ 2026-07-01 14:27 ` Frank Li
2026-07-02 7:35 ` Ioana Ciornei
0 siblings, 1 reply; 9+ messages in thread
From: Frank Li @ 2026-07-01 14:27 UTC (permalink / raw)
To: Ioana Ciornei
Cc: Frank.Li, robh, krzk+dt, conor+dt, devicetree, vladimir.oltean,
linux-arm-kernel, linux-kernel, imx
On Wed, Jul 01, 2026 at 04:11:33PM +0300, Ioana Ciornei wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
>
> Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes
> instance is present in the compatible string, to allow reliable per-lane
> capability detection and per-lane customization of electrical properties.
>
> The modern bindings are backward-incompatible with old kernels, due
> to the consumer phandles being either in one form or in another, as
> explained here:
> https://lore.kernel.org/lkml/20250930140735.mvo3jii7wgmzh2bs@skbuf/
>
> One of the major differences between the LX2160A and LX2162A is the
> SerDes. So far, LX2162A has used fsl-lx2160a-rev2.dtsi, but we need to
> split that up even further, and derive a fsl-lx2162a.dtsi which
> overrides the SerDes properties.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - Enable serdes_1 on all board DTs that has consumers for it.
> - Use the proper name for serdes_3 in fsl-lx2162a.dtsi.
> - Remove paragraph from commit message which mentioned some consumer
> changes that are no longer needed nor part of the commit.
> ---
> .../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 +
> .../dts/freescale/fsl-lx2160a-half-twins.dts | 4 +
> .../boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 +
> .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 150 +++++++++++++++++-
> .../dts/freescale/fsl-lx2162a-clearfog.dts | 6 +-
> .../boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +-
> .../arm64/boot/dts/freescale/fsl-lx2162a.dtsi | 24 +++
> 7 files changed, 190 insertions(+), 4 deletions(-)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
>
...
>
> +&serdes_1 {
> + status = "okay";
> +};
> +
Can you try keep alphabet order? may old file is not ordersed, but try
best, at least should before &uart0
> &uart1 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 1d73abffa6b7..a687eb3e3190 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
Please split chips dtsi and boards dts to two patch.
> @@ -621,17 +621,163 @@ soc: soc {
> ranges;
> dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
>
> + /* Note on the interpretation of SerDes lane numbering from
> + * LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]:
> + * The letters (A-H) correspond to logical lane numbers in the
> + * SerDes register map (lane A's registers start with LNAGCR0),
> + * while the numbers (0-7) correspond to physical lanes as
> + * routed to pins. SerDes block #1 is flipped in the LX2160A
> + * floorplan (logical lane A goes to physical lane 7's pins),
> + * while SerDes blocks #2 and #3 are not. The lanes below are
> + * listed right to left when looking at that table.
> + * Both the numbers and the letters are according to the logical
> + * numbering scheme, and do not account for the flipping.
> + */
...
> + compatible = "fsl,lx2160a-serdes3";
> + reg = <0x0 0x1ec0000 0x0 0x1e30>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
status should be last property
> + #phy-cells = <1>;
> +
> + serdes_3_lane_a: phy@0 {
> + reg = <0>;
> + #phy-cells = <0>;
> + };
> +
...
> +
> +#include "fsl-lx2160a-rev2.dtsi"
> +
> +&serdes_1 {
> + compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g";
> +
> + /delete-node/ phy@0;
> + /delete-node/ phy@1;
> + /delete-node/ phy@2;
> + /delete-node/ phy@3;
Now, do not perfer delete-node. if ver2 is not include phy@0, ...
create ver2 files, let ver2 include it. Now most people like A + B, not
A - B.
Frank
> +};
> +
> +&serdes_2 {
> + compatible = "fsl,lx2162a-serdes2", "fsl,lynx-28g";
> +};
> +
> +&soc {
> + /delete-node/ phy@1ec0000;
> +};
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings
2026-07-01 14:27 ` Frank Li
@ 2026-07-02 7:35 ` Ioana Ciornei
2026-07-02 12:23 ` Frank Li
0 siblings, 1 reply; 9+ messages in thread
From: Ioana Ciornei @ 2026-07-02 7:35 UTC (permalink / raw)
To: Frank Li
Cc: Frank.Li, robh, krzk+dt, conor+dt, devicetree, vladimir.oltean,
linux-arm-kernel, linux-kernel, imx
On Wed, Jul 01, 2026 at 09:27:03AM -0500, Frank Li wrote:
> On Wed, Jul 01, 2026 at 04:11:33PM +0300, Ioana Ciornei wrote:
> > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> >
> > Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes
> > instance is present in the compatible string, to allow reliable per-lane
> > capability detection and per-lane customization of electrical properties.
> >
> > The modern bindings are backward-incompatible with old kernels, due
> > to the consumer phandles being either in one form or in another, as
> > explained here:
> > https://lore.kernel.org/lkml/20250930140735.mvo3jii7wgmzh2bs@skbuf/
> >
> > One of the major differences between the LX2160A and LX2162A is the
> > SerDes. So far, LX2162A has used fsl-lx2160a-rev2.dtsi, but we need to
> > split that up even further, and derive a fsl-lx2162a.dtsi which
> > overrides the SerDes properties.
> >
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > ---
> > Changes in v2:
> > - Enable serdes_1 on all board DTs that has consumers for it.
> > - Use the proper name for serdes_3 in fsl-lx2162a.dtsi.
> > - Remove paragraph from commit message which mentioned some consumer
> > changes that are no longer needed nor part of the commit.
> > ---
> > .../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 +
> > .../dts/freescale/fsl-lx2160a-half-twins.dts | 4 +
> > .../boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 +
> > .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 150 +++++++++++++++++-
> > .../dts/freescale/fsl-lx2162a-clearfog.dts | 6 +-
> > .../boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +-
> > .../arm64/boot/dts/freescale/fsl-lx2162a.dtsi | 24 +++
> > 7 files changed, 190 insertions(+), 4 deletions(-)
> > create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
> >
> ...
> >
> > +&serdes_1 {
> > + status = "okay";
> > +};
> > +
>
> Can you try keep alphabet order? may old file is not ordersed, but try
> best, at least should before &uart0
Sure, will move it.
>
> > &uart1 {
> > status = "okay";
> > };
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > index 1d73abffa6b7..a687eb3e3190 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>
> Please split chips dtsi and boards dts to two patch.
Ok, I will split the serdes_1 explicit enable into a prep patch.
>
> > @@ -621,17 +621,163 @@ soc: soc {
> > ranges;
> > dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
> >
> > + /* Note on the interpretation of SerDes lane numbering from
> > + * LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]:
> > + * The letters (A-H) correspond to logical lane numbers in the
> > + * SerDes register map (lane A's registers start with LNAGCR0),
> > + * while the numbers (0-7) correspond to physical lanes as
> > + * routed to pins. SerDes block #1 is flipped in the LX2160A
> > + * floorplan (logical lane A goes to physical lane 7's pins),
> > + * while SerDes blocks #2 and #3 are not. The lanes below are
> > + * listed right to left when looking at that table.
> > + * Both the numbers and the letters are according to the logical
> > + * numbering scheme, and do not account for the flipping.
> > + */
> ...
> > + compatible = "fsl,lx2160a-serdes3";
> > + reg = <0x0 0x1ec0000 0x0 0x1e30>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
>
> status should be last property
Ok, will move it.
>
> > + #phy-cells = <1>;
> > +
> > + serdes_3_lane_a: phy@0 {
> > + reg = <0>;
> > + #phy-cells = <0>;
> > + };
> > +
> ...
> > +
> > +#include "fsl-lx2160a-rev2.dtsi"
> > +
> > +&serdes_1 {
> > + compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g";
> > +
> > + /delete-node/ phy@0;
> > + /delete-node/ phy@1;
> > + /delete-node/ phy@2;
> > + /delete-node/ phy@3;
>
> Now, do not perfer delete-node. if ver2 is not include phy@0, ...
>
> create ver2 files, let ver2 include it. Now most people like A + B, not
> A - B.
>
I am not sure I follow what you say about the ver2 files - are you
referring to -rev2 or LX2162A?
The LX2162A is a version of the LX2160A SoC, also known as "LX2-Lite".
And the main difference is that the LX2162A does not have the 3rd SerDes
block and only 4 SerDes lanes on the first block.
The delete-node is reflecting exactly how the SoCs came about, the
LX2162A is a smaller version of the LX2160A (which came first) and not
the other way around.
I feel like it's unnecessary churn but let me know if you feel strongly
about this.
Thanks,
Ioana
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings
2026-07-02 7:35 ` Ioana Ciornei
@ 2026-07-02 12:23 ` Frank Li
0 siblings, 0 replies; 9+ messages in thread
From: Frank Li @ 2026-07-02 12:23 UTC (permalink / raw)
To: Ioana Ciornei
Cc: Frank.Li, robh, krzk+dt, conor+dt, devicetree, vladimir.oltean,
linux-arm-kernel, linux-kernel, imx
On Thu, Jul 02, 2026 at 10:35:00AM +0300, Ioana Ciornei wrote:
> On Wed, Jul 01, 2026 at 09:27:03AM -0500, Frank Li wrote:
> > On Wed, Jul 01, 2026 at 04:11:33PM +0300, Ioana Ciornei wrote:
> > > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> > >
> > > Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes
> > > instance is present in the compatible string, to allow reliable per-lane
> > > capability detection and per-lane customization of electrical properties.
> > >
> > > The modern bindings are backward-incompatible with old kernels, due
> > > to the consumer phandles being either in one form or in another, as
> > > explained here:
> > > https://lore.kernel.org/lkml/20250930140735.mvo3jii7wgmzh2bs@skbuf/
> > >
> > > One of the major differences between the LX2160A and LX2162A is the
> > > SerDes. So far, LX2162A has used fsl-lx2160a-rev2.dtsi, but we need to
> > > split that up even further, and derive a fsl-lx2162a.dtsi which
> > > overrides the SerDes properties.
> > >
> > > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > > ---
> > > Changes in v2:
> > > - Enable serdes_1 on all board DTs that has consumers for it.
> > > - Use the proper name for serdes_3 in fsl-lx2162a.dtsi.
> > > - Remove paragraph from commit message which mentioned some consumer
> > > changes that are no longer needed nor part of the commit.
> > > ---
> > > .../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 +
> > > .../dts/freescale/fsl-lx2160a-half-twins.dts | 4 +
> > > .../boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 +
> > > .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 150 +++++++++++++++++-
> > > .../dts/freescale/fsl-lx2162a-clearfog.dts | 6 +-
> > > .../boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +-
> > > .../arm64/boot/dts/freescale/fsl-lx2162a.dtsi | 24 +++
> > > 7 files changed, 190 insertions(+), 4 deletions(-)
> > > create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
> > >
> > ...
> > >
> > > +&serdes_1 {
> > > + status = "okay";
> > > +};
> > > +
> >
> > Can you try keep alphabet order? may old file is not ordersed, but try
> > best, at least should before &uart0
>
> Sure, will move it.
>
> >
> > > &uart1 {
> > > status = "okay";
> > > };
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > > index 1d73abffa6b7..a687eb3e3190 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> >
> > Please split chips dtsi and boards dts to two patch.
>
> Ok, I will split the serdes_1 explicit enable into a prep patch.
>
> >
> > > @@ -621,17 +621,163 @@ soc: soc {
> > > ranges;
> > > dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
> > >
> > > + /* Note on the interpretation of SerDes lane numbering from
> > > + * LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]:
> > > + * The letters (A-H) correspond to logical lane numbers in the
> > > + * SerDes register map (lane A's registers start with LNAGCR0),
> > > + * while the numbers (0-7) correspond to physical lanes as
> > > + * routed to pins. SerDes block #1 is flipped in the LX2160A
> > > + * floorplan (logical lane A goes to physical lane 7's pins),
> > > + * while SerDes blocks #2 and #3 are not. The lanes below are
> > > + * listed right to left when looking at that table.
> > > + * Both the numbers and the letters are according to the logical
> > > + * numbering scheme, and do not account for the flipping.
> > > + */
> > ...
> > > + compatible = "fsl,lx2160a-serdes3";
> > > + reg = <0x0 0x1ec0000 0x0 0x1e30>;
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + status = "disabled";
> >
> > status should be last property
>
> Ok, will move it.
>
> >
> > > + #phy-cells = <1>;
> > > +
> > > + serdes_3_lane_a: phy@0 {
> > > + reg = <0>;
> > > + #phy-cells = <0>;
> > > + };
> > > +
> > ...
> > > +
> > > +#include "fsl-lx2160a-rev2.dtsi"
> > > +
> > > +&serdes_1 {
> > > + compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g";
> > > +
> > > + /delete-node/ phy@0;
> > > + /delete-node/ phy@1;
> > > + /delete-node/ phy@2;
> > > + /delete-node/ phy@3;
> >
> > Now, do not perfer delete-node. if ver2 is not include phy@0, ...
> >
> > create ver2 files, let ver2 include it. Now most people like A + B, not
> > A - B.
> >
>
> I am not sure I follow what you say about the ver2 files - are you
> referring to -rev2 or LX2162A?
>
> The LX2162A is a version of the LX2160A SoC, also known as "LX2-Lite".
> And the main difference is that the LX2162A does not have the 3rd SerDes
> block and only 4 SerDes lanes on the first block.
If it is the same die and it is disable by fuse box. I suggest leave it here
now because default it is disabled and try to access-control-cell in future.
https://lore.kernel.org/imx/20241212-imx-ocotp-v1-1-198bb0af86a0@nxp.com/
That these nodes can be dymatically disabled it.
If it is difference die, it should lx2160a.dtsi include lx2-lite. you
can rename old lx2160a.dtsi to lx2-lites.dtsi. You need adjust file name
and I just said overwhole method.
Frank
>
> The delete-node is reflecting exactly how the SoCs came about, the
> LX2162A is a smaller version of the LX2160A (which came first) and not
> the other way around.
>
> I feel like it's unnecessary churn but let me know if you feel strongly
> about this.
>
> Thanks,
> Ioana
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/5] arm64: dts: ls1028a: describe the Lynx 10G SerDes
2026-07-01 13:11 [PATCH v2 0/5] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
2026-07-01 13:11 ` [PATCH v2 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings Ioana Ciornei
@ 2026-07-01 13:11 ` Ioana Ciornei
2026-07-01 13:11 ` [PATCH v2 3/5] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks Ioana Ciornei
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Ioana Ciornei @ 2026-07-01 13:11 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Describe the Lynx 10G SerDes block and its 4 SerDes lanes found on the
LS1028A SoC. The node is left disabled at the SoC level; board DTs will
be expected to enable it once the consumer Ethernet nodes use it.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Change the size of the region to 0x2000
---
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index f4ba3d16ab86..ef62968590fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -250,6 +250,35 @@ ls1028a_uid: unique-id@1c {
};
};
+ serdes: phy@1ea0000 {
+ compatible = "fsl,ls1028a-serdes";
+ reg = <0x00 0x1ea0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
scfg: syscon@1fc0000 {
compatible = "fsl,ls1028a-scfg", "syscon";
reg = <0x0 0x1fc0000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 3/5] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks
2026-07-01 13:11 [PATCH v2 0/5] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
2026-07-01 13:11 ` [PATCH v2 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings Ioana Ciornei
2026-07-01 13:11 ` [PATCH v2 2/5] arm64: dts: ls1028a: describe the Lynx 10G SerDes Ioana Ciornei
@ 2026-07-01 13:11 ` Ioana Ciornei
2026-07-01 13:11 ` [PATCH v2 4/5] arm64: dts: ls208xa: " Ioana Ciornei
2026-07-01 13:11 ` [PATCH v2 5/5] arm64: dts: ls1088a: " Ioana Ciornei
4 siblings, 0 replies; 9+ messages in thread
From: Ioana Ciornei @ 2026-07-01 13:11 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Describe the two Lynx 10G SerDes blocks and their associated lanes found
on the LS1046A SoC. The nodes are left disabled at the SoC level; board
DTs will be expected to enable them once the consumer Ethernet nodes
appear.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Change the size of the region to 0x2000
---
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 6fefe837f434..270a97711a69 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -424,6 +424,66 @@ sfp: efuse@1e80000 {
clock-names = "sfp";
};
+ serdes1: phy@1ea0000 {
+ compatible = "fsl,ls1046a-serdes1";
+ reg = <0x00 0x1ea0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ big-endian;
+ status = "disabled";
+
+ serdes1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
+ serdes2: phy@1eb0000 {
+ compatible = "fsl,ls1046a-serdes2";
+ reg = <0x00 0x1eb0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ big-endian;
+ status = "disabled";
+
+ serdes2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1046a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x1000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 4/5] arm64: dts: ls208xa: describe the Lynx 10G SerDes blocks
2026-07-01 13:11 [PATCH v2 0/5] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
` (2 preceding siblings ...)
2026-07-01 13:11 ` [PATCH v2 3/5] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks Ioana Ciornei
@ 2026-07-01 13:11 ` Ioana Ciornei
2026-07-01 13:11 ` [PATCH v2 5/5] arm64: dts: ls1088a: " Ioana Ciornei
4 siblings, 0 replies; 9+ messages in thread
From: Ioana Ciornei @ 2026-07-01 13:11 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Describe the two Lynx 10G SerDes blocks and their associated lanes found
on the LS208xA SoC. The nodes are left disabled at the SoC level; board
DTs will enable them once there are consumers.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Change the size of the region to 0x2000
---
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 98 +++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 6073e426774a..cc1a64e63ed5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -280,6 +280,104 @@ sfp: efuse@1e80000 {
clock-names = "sfp";
};
+ serdes1: phy@1ea0000 {
+ compatible = "fsl,ls2088a-serdes1";
+ reg = <0x00 0x1ea0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
+ };
+
+ serdes2: phy@1eb0000 {
+ compatible = "fsl,ls2088a-serdes2";
+ reg = <0x00 0x1eb0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
+ };
+
isc: syscon@1f70000 {
compatible = "fsl,ls2080a-isc", "syscon";
reg = <0x0 0x1f70000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 5/5] arm64: dts: ls1088a: describe the Lynx 10G SerDes blocks
2026-07-01 13:11 [PATCH v2 0/5] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs Ioana Ciornei
` (3 preceding siblings ...)
2026-07-01 13:11 ` [PATCH v2 4/5] arm64: dts: ls208xa: " Ioana Ciornei
@ 2026-07-01 13:11 ` Ioana Ciornei
4 siblings, 0 replies; 9+ messages in thread
From: Ioana Ciornei @ 2026-07-01 13:11 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx
Describe the two Lynx 10G SerDes blocks and their associated lanes found
on the LS1088A SoC. The nodes are left disabled at the SoC level; board
DTs will enable them once there are consumers.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Change the size of the region to 0x2000
---
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 99016768b73f..e02f34329988 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -239,6 +239,64 @@ reset: syscon@1e60000 {
reg = <0x0 0x1e60000 0x0 0x10000>;
};
+ serdes1: phy@1ea0000 {
+ compatible = "fsl,ls1088a-serdes1";
+ reg = <0x00 0x1ea0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
+ serdes2: phy@1eb0000 {
+ compatible = "fsl,ls1088a-serdes2";
+ reg = <0x00 0x1eb0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
isc: syscon@1f70000 {
compatible = "fsl,ls1088a-isc", "syscon";
reg = <0x0 0x1f70000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread