[PATCH v3 0/2] Ambarella CV75: 8250_dw UART

[PATCH v3 0/2] Ambarella CV75: 8250_dw UART

[Long Zhao via B4 Relay]

This is part C of a 3-part CV75 v3 split:

  A: bindings + RCT/CCU clocks + SoC/EVK DT + MAINTAINERS
  B: pinctrl + PL061 GPIO variant
  C: 8250_dw UART quirks  (this series)

Depends on series A:
https://lore.kernel.org/r/20260813-cv75-v3-a-v3-0-cfdd20b1b4dd@ambarella.com

Depends on series B:
https://lore.kernel.org/r/20260813-cv75-v3-b-v3-0-1d82e18da09b@ambarella.com

Link to v2:
https://lore.kernel.org/r/20260806-longzhao-upstream-cv75-v2-v2-0-6b09707c5fe9@ambarella.com

Summary:
- document ambarella,cv75-uart on snps,dw-apb-uart
- Ambarella quirks in 8250_dw

Changes since v2 (C scope):
- drop custom Ambarella UART driver; reuse 8250_dw (Linus)

Verified on CV75 with A+B+C.

Signed-off-by: Long Zhao <longzhao@ambarella.com>

---
Long Zhao (2):
      dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart
      serial: 8250_dw: add Ambarella CV75 quirks

 .../bindings/serial/snps-dw-apb-uart.yaml          |  1 +
 drivers/tty/serial/8250/8250_dw.c                  | 30 ++++++++++++++++++++++
 2 files changed, 31 insertions(+)
---
base-commit: 378c935cabe003ef440c1c79302a1f8ed7913778
change-id: 20260813-cv75-v3-c-d98a97d0f9f1

Best regards,
--  
Long Zhao <longzhao@ambarella.com>

[PATCH v3 1/2] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart

[Long Zhao via B4 Relay]

From: Long Zhao <longzhao@ambarella.com>

Add the Ambarella CV75 compatible string to the Synopsys DW APB UART
binding.

Signed-off-by: Long Zhao <longzhao@ambarella.com>
---
 Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 49f51b002879..cec5c679f1a9 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -51,6 +51,7 @@ properties:
           - const: renesas,rzn1-uart
       - items:
           - enum:
+              - ambarella,cv75-uart
               - anlogic,dr1v90-uart
               - brcm,bcm11351-dw-apb-uart
               - brcm,bcm21664-dw-apb-uart

-- 
2.34.1

[PATCH v3 2/2] serial: 8250_dw: add Ambarella CV75 quirks

[Long Zhao via B4 Relay]

From: Long Zhao <longzhao@ambarella.com>

Add CV75 platform data with an ETOI IER mask and skip-set-rate so the
DesignWare 8250 driver can drive the Ambarella UART for console use.

Signed-off-by: Long Zhao <longzhao@ambarella.com>
---
 drivers/tty/serial/8250/8250_dw.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 5fba913f3301..e8aa592924d4 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -43,6 +43,9 @@
 #define RZN1_UART_xDMACR_8_WORD_BURST	(2 << 1)
 #define RZN1_UART_xDMACR_BLK_SZ(x)	((x) << 3)
 
+/* Ambarella specific register fields */
+#define AMBARELLA_UART_IER_ETOI		BIT(5)
+
 /* Quirks */
 #define DW_UART_QUIRK_OCTEON		BIT(0)
 #define DW_UART_QUIRK_ARMADA_38X	BIT(1)
@@ -60,6 +63,7 @@
 
 struct dw8250_platform_data {
 	u8 usr_reg;
+	u8 ier_mask;
 	u32 cpr_value;
 	unsigned int quirks;
 };
@@ -572,6 +576,23 @@ static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
 	dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
 }
 
+static int dw8250_ier_mask_startup(struct uart_port *p)
+{
+	struct dw8250_data *d = to_dw8250_data(p->private_data);
+	struct uart_8250_port *up = up_to_u8250p(p);
+	int ret;
+
+	ret = serial8250_do_startup(p);
+	if (ret)
+		return ret;
+
+	/* Keep variant-specific bits in the shadow across subsequent updates. */
+	up->ier |= d->pdata->ier_mask;
+	serial_port_out(p, UART_IER, up->ier);
+
+	return 0;
+}
+
 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 {
 	unsigned int quirks = data->pdata->quirks;
@@ -606,6 +627,8 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 		p->serial_in = dw8250_serial_in32;
 		data->uart_16550_compatible = true;
 	}
+	if (data->pdata->ier_mask)
+		p->startup = dw8250_ier_mask_startup;
 }
 
 static void dw8250_reset_control_assert(void *data)
@@ -879,6 +902,12 @@ static const struct dw8250_platform_data dw8250_intc10ee = {
 	.quirks = DW_UART_QUIRK_IER_KICK,
 };
 
+static const struct dw8250_platform_data dw8250_ambarella_cv75_data = {
+	.usr_reg = DW_UART_USR,
+	.ier_mask = AMBARELLA_UART_IER_ETOI,
+	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
+};
+
 static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = {
 	.usr_reg = DW_UART_USR,
 	.cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) |
@@ -889,6 +918,7 @@ static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = {
 };
 
 static const struct of_device_id dw8250_of_match[] = {
+	{ .compatible = "ambarella,cv75-uart", .data = &dw8250_ambarella_cv75_data },
 	{ .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
 	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
 	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },

-- 
2.34.1

Re: [PATCH v3 1/2] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The 'ambarella' vendor prefix is newly introduced in this binding but is not documented in vendor-prefixes.yaml.
--

--- Patch [1]: [PATCH v3 1/2] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart ---
commit 09140ea99754febddffd7c03dfcd93c0fffe28fb
Author: Long Zhao <longzhao@ambarella.com>

dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart

Add the Ambarella CV75 compatible string to the Synopsys DW APB UART
binding.

> diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> index 49f51b0028795..cec5c679f1a9d 100644
> --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
> @@ -51,6 +51,7 @@ properties:
>            - const: renesas,rzn1-uart
>        - items:
>            - enum:
> +              - ambarella,cv75-uart

[Severity: Low]
Has the ambarella vendor prefix added to properties:compatible been formally
documented in vendor-prefixes.yaml?

If this prefix is omitted from vendor-prefixes.yaml, evaluating this schema
with dt-schema will encounter the undocumented ambarella prefix. This will
cause make dt_binding_check to report a schema validation warning or error
during the build.

>                - anlogic,dr1v90-uart
>                - brcm,bcm11351-dw-apb-uart
>                - brcm,bcm21664-dw-apb-uart

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260813-cv75-v3-c-v3-0-9352b3fd6026@ambarella.com?part=1

Re: [PATCH v3 2/2] serial: 8250_dw: add Ambarella CV75 quirks

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [High] Premature and lockless write to UART_IER in dw8250_ier_mask_startup defeats interrupt deferral and introduces race conditions.

Pre-existing issues:
- [High] Runtime PM is enabled after port registration, violating subsystem PM initialization rules and causing circular wait conditions.
--

--- Patch [2]: [PATCH v3 2/2] serial: 8250_dw: add Ambarella CV75 quirks ---
commit 6e65f0f86d7deb4c1cfc42c64f909eb5435425fe
Author: Long Zhao <longzhao@ambarella.com>

serial: 8250_dw: add Ambarella CV75 quirks

Add CV75 platform data with an ETOI IER mask and skip-set-rate so the
DesignWare 8250 driver can drive the Ambarella UART for console use.

> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index 5fba913f33010..e8aa592924d4d 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
[ ... ]
> @@ -572,6 +576,23 @@ static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
>  	dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
>  }
>  
> +static int dw8250_ier_mask_startup(struct uart_port *p)
> +{
> +	struct dw8250_data *d = to_dw8250_data(p->private_data);
> +	struct uart_8250_port *up = up_to_u8250p(p);
> +	int ret;
> +
> +	ret = serial8250_do_startup(p);
> +	if (ret)
> +		return ret;
> +
> +	/* Keep variant-specific bits in the shadow across subsequent updates. */
> +	up->ier |= d->pdata->ier_mask;
> +	serial_port_out(p, UART_IER, up->ier);

[Severity: High]
Does this lockless write to UART_IER introduce a race condition against the
serial console? 

The 8250 core explicitly defers enabling hardware RX interrupts until
set_termios() configures the FIFOs to prevent swamping the interrupt handler.
Writing to UART_IER here defeats that safety mechanism.

Furthermore, if a printk occurs concurrently, serial8250_console_write()
executes on another CPU and performs a read-modify-restore on UART_IER. This
lockless write races with the console driver, which can permanently drop the
ier_mask bits or cause unpredictable hardware behavior.

Should this write be protected by p->lock, and potentially deferred until
the FIFOs are configured?

> +
> +	return 0;
> +}
> +

[Severity: High]
This isn't a bug introduced by this patch, but there is a pre-existing
issue in dw8250_probe() regarding runtime PM initialization:

drivers/tty/serial/8250/8250_dw.c:dw8250_probe() {
    ...
	data->data.line = serial8250_register_8250_port(up);
	if (data->data.line < 0)
		return data->data.line;

	platform_set_drvdata(pdev, data);

	pm_runtime_enable(dev);
    ...
}

Does registering the port before enabling runtime PM cause circular wait
conditions during device probe?

Registration synchronously invokes the driver's pm callback (dw8250_do_pm)
via uart_add_one_port(). The dw8250_do_pm() callback unconditionally calls
pm_runtime_get_sync(port->dev). 

As documented in the TTY subsystem guidelines, invoking runtime PM APIs from
callbacks before pm_runtime_enable() is called leads to circular dependencies,
hanging the probe function indefinitely because the runtime PM infrastructure
is not yet initialized for the device.

Should pm_runtime_enable(dev) be called before serial8250_register_8250_port()?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260813-cv75-v3-c-v3-0-9352b3fd6026@ambarella.com?part=2

Re: [PATCH v3 1/2] dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart

[Linus Walleij]

On Thu, Aug 13, 2026 at 12:35 PM Long Zhao via B4 Relay
<devnull+longzhao.ambarella.com@kernel.org> wrote:

> From: Long Zhao <longzhao@ambarella.com>
>
> Add the Ambarella CV75 compatible string to the Synopsys DW APB UART
> binding.
>
> Signed-off-by: Long Zhao <longzhao@ambarella.com>

Reviewed-by: Linus Walleij <linusw@kernel.org>

Yours,
Linus Walleij

Re: [PATCH v3 2/2] serial: 8250_dw: add Ambarella CV75 quirks

[Linus Walleij]

On Thu, Aug 13, 2026 at 12:35 PM Long Zhao via B4 Relay
<devnull+longzhao.ambarella.com@kernel.org> wrote:

> From: Long Zhao <longzhao@ambarella.com>
>
> Add CV75 platform data with an ETOI IER mask and skip-set-rate so the
> DesignWare 8250 driver can drive the Ambarella UART for console use.
>
> Signed-off-by: Long Zhao <longzhao@ambarella.com>

I see this approach was successful! :)
Look into the Sashiko comment abour lockless write to UART_IER
but from my PoV this is fine:
Reviewed-by: Linus Walleij <linusw@kernel.org>

Yours,
Linus Walleij

RE: Re: [PATCH v3 2/2] serial: 8250_dw: add Ambarella CV75 quirks

[Long Zhao]

Hi Linus,

Thanks for the review and for steering us to 8250_dw. I'll also look
into the Sashiko comment on the lockless UART_IER write.

Best regards!
Long Zhao

Ambarella Shanghai Co., Ltd
-----Original Message-----
From: Linus Walleij <linusw@kernel.org> 
Sent: Friday, August 14, 2026 15:00
To: Long Zhao <longzhao@ambarella.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>; Jiri Slaby <jirislaby@kernel.org>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>; Andy Shevchenko <andriy.shevchenko@linux.intel.com>; linux-kernel@vger.kernel.org; linux-serial@vger.kernel.org; devicetree@vger.kernel.org
Subject: [EXT] Re: [PATCH v3 2/2] serial: 8250_dw: add Ambarella CV75 quirks

On Thu, Aug 13, 2026 at 12:35 PM Long Zhao via B4 Relay <devnull+longzhao.ambarella.com@kernel.org> wrote:

> From: Long Zhao <longzhao@ambarella.com>
>
> Add CV75 platform data with an ETOI IER mask and skip-set-rate so the 
> DesignWare 8250 driver can drive the Ambarella UART for console use.
>
> Signed-off-by: Long Zhao <longzhao@ambarella.com>

I see this approach was successful! :)
Look into the Sashiko comment abour lockless write to UART_IER but from my PoV this is fine:
Reviewed-by: Linus Walleij <linusw@kernel.org>

Yours,
Linus Walleij

######################################################################
This EXTERNAL email has been scanned by Proofpoint Email Protect service.

**********************************************************************
This email and attachments contain Ambarella Proprietary and/or Confidential Information and is intended solely for the use of the individual(s) to whom it is addressed. Any unauthorized review, use, disclosure, distribute, copy, or print is prohibited. If you are not an intended recipient, please contact the sender by reply email and destroy all copies of the original message. Thank you.

Re: [PATCH v3 2/2] serial: 8250_dw: add Ambarella CV75 quirks

[Andy Shevchenko]

On Thu, Aug 13, 2026 at 06:35:13PM +0800, Long Zhao via B4 Relay wrote:

> Add CV75 platform data with an ETOI IER mask and skip-set-rate so the
> DesignWare 8250 driver can drive the Ambarella UART for console use.

This is way too cryptic commit message, we need much more details.
What's wrong with HW implementation? Is it integration HW bug or some specific
case of the IP synthesis? What is happening when this patch is *not*
applied? Et cetera, et cetera...

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v3 2/2] serial: 8250_dw: add Ambarella CV75 quirks

[Andy Shevchenko]

On Thu, Aug 13, 2026 at 06:35:13PM +0800, Long Zhao via B4 Relay wrote:

> Add CV75 platform data with an ETOI IER mask and skip-set-rate so the
> DesignWare 8250 driver can drive the Ambarella UART for console use.

...

> +	/* Keep variant-specific bits in the shadow across subsequent updates. */

This says what code is doing. Instead it must say "why?" the code is doing this.

> +	up->ier |= d->pdata->ier_mask;
> +	serial_port_out(p, UART_IER, up->ier);

...

In case there is an HW bug, where can we get the errata, please? (For a bare
minimum add a reference to the Errata document you give to the customers.)

-- 
With Best Regards,
Andy Shevchenko

RE: [EXT] Re: [PATCH v3 2/2] serial: 8250_dw: add Ambarella CV75 quirks

[Long Zhao]

Hi Andy,

Thanks for the review. Agreed the commit message was too brief.

This is not a silicon erratum. The Ambarella UART is not Synopsys
DesignWare IP; it is an Ambarella 8250-compatible UART. We still use
the snps-dw-apb-uart binding / 8250_dw because the programming model
matches closely enough, with two quirks (ETOI IER bit and
SKIP_SET_RATE). I will expand the commit message and rewrite the
comment to explain why in the next revision.

Best regards!
Long Zhao

Ambarella Shanghai Co., Ltd
-----Original Message-----
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 
Sent: Friday, August 14, 2026 16:56
To: Long Zhao <longzhao@ambarella.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>; Jiri Slaby <jirislaby@kernel.org>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Linus Walleij <linusw@kernel.org>; Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>; linux-kernel@vger.kernel.org; linux-serial@vger.kernel.org; devicetree@vger.kernel.org
Subject: [EXT] Re: [PATCH v3 2/2] serial: 8250_dw: add Ambarella CV75 quirks

On Thu, Aug 13, 2026 at 06:35:13PM +0800, Long Zhao via B4 Relay wrote:

> Add CV75 platform data with an ETOI IER mask and skip-set-rate so the 
> DesignWare 8250 driver can drive the Ambarella UART for console use.

...

> +	/* Keep variant-specific bits in the shadow across subsequent 
> +updates. */

This says what code is doing. Instead it must say "why?" the code is doing this.

> +	up->ier |= d->pdata->ier_mask;
> +	serial_port_out(p, UART_IER, up->ier);

...

In case there is an HW bug, where can we get the errata, please? (For a bare minimum add a reference to the Errata document you give to the customers.)

--
With Best Regards,
Andy Shevchenko



######################################################################
This EXTERNAL email has been scanned by Proofpoint Email Protect service.

**********************************************************************
This email and attachments contain Ambarella Proprietary and/or Confidential Information and is intended solely for the use of the individual(s) to whom it is addressed. Any unauthorized review, use, disclosure, distribute, copy, or print is prohibited. If you are not an intended recipient, please contact the sender by reply email and destroy all copies of the original message. Thank you.

Re: [EXT] Re: [PATCH v3 2/2] serial: 8250_dw: add Ambarella CV75 quirks

[Andy Shevchenko]

On Fri, Aug 14, 2026 at 09:33:45AM +0000, Long Zhao wrote:
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 
> Sent: Friday, August 14, 2026 16:56
> On Thu, Aug 13, 2026 at 06:35:13PM +0800, Long Zhao via B4 Relay wrote:
> 
> > Add CV75 platform data with an ETOI IER mask and skip-set-rate so the 
> > DesignWare 8250 driver can drive the Ambarella UART for console use.

> Thanks for the review. Agreed the commit message was too brief.

...

> > +	/* Keep variant-specific bits in the shadow across subsequent 
> > +updates. */
> 
> This says what code is doing. Instead it must say "why?" the code is doing this.
> 
> > +	up->ier |= d->pdata->ier_mask;
> > +	serial_port_out(p, UART_IER, up->ier);

...

> In case there is an HW bug, where can we get the errata, please? (For a bare
> minimum add a reference to the Errata document you give to the customers.)

> This is not a silicon erratum. The Ambarella UART is not Synopsys
> DesignWare IP; it is an Ambarella 8250-compatible UART. We still use
> the snps-dw-apb-uart binding / 8250_dw because the programming model
> matches closely enough, with two quirks (ETOI IER bit and
> SKIP_SET_RATE). I will expand the commit message and rewrite the
> comment to explain why in the next revision.

Okay, what does it make to think that 8250_dw is a suitable choice?
What are the features that are repetitive would be if you use a custom
8250-based driver (using the generic 8250 code)?

-- 
With Best Regards,
Andy Shevchenko