* [PATCH v5 1/2] dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock
2026-08-06 14:51 [PATCH v5 0/2] Add LPASS VA CSR HeartBeat pulse clock support Sarath Ganapathiraju via B4 Relay
@ 2026-08-06 14:51 ` Sarath Ganapathiraju via B4 Relay
2026-08-10 16:01 ` Bjorn Andersson
2026-08-06 14:51 ` [PATCH v5 2/2] clk: qcom: Add LPASS VA CSR heartbeat " Sarath Ganapathiraju via B4 Relay
1 sibling, 1 reply; 4+ messages in thread
From: Sarath Ganapathiraju via B4 Relay @ 2026-08-06 14:51 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Srinivas Kandagatla
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel,
prasad.kumpatla, Sarath Ganapathiraju, Krzysztof Kozlowski
From: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
Add a binding for the Qualcomm LPASS VA CSR rate generator node that
exposes the lpass_heartbeat_pulse clock on hawi.
The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the
start of the DMAs and Codec Interfaces for the audio usecase and can
serve as a periodic wakeup source for the DSP.
Signed-off-by: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../bindings/clock/qcom,hawi-lpass-va-csr.yaml | 51 ++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml
new file mode 100644
index 000000000000..9935173d8bee
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,hawi-lpass-va-csr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS VA CSR heartbeat pulse clock provider
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
+ - Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
+
+description:
+ The LPASS (Low Power Audio Subsystem) VA CSR block contains a rate
+ generator that produces a periodic HeartBeat Pulse, also known as
+ the RateGen Pulse. This pulse synchronizes the start of DMAs and
+ Codec Interfaces for audio usecases and can serve as a periodic
+ wakeup source for the DSP.
+
+properties:
+ compatible:
+ enum:
+ - qcom,hawi-lpass-va-csr
+
+ reg:
+ maxItems: 1
+ description: Address and size of the rate generator registers within
+ the VA CSR block.
+
+ "#clock-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@7eed000 {
+ compatible = "qcom,hawi-lpass-va-csr";
+ reg = <0x0 0x07eed000 0x0 0x14>;
+ #clock-cells = <0>;
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v5 2/2] clk: qcom: Add LPASS VA CSR heartbeat pulse clock
2026-08-06 14:51 [PATCH v5 0/2] Add LPASS VA CSR HeartBeat pulse clock support Sarath Ganapathiraju via B4 Relay
2026-08-06 14:51 ` [PATCH v5 1/2] dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock Sarath Ganapathiraju via B4 Relay
@ 2026-08-06 14:51 ` Sarath Ganapathiraju via B4 Relay
1 sibling, 0 replies; 4+ messages in thread
From: Sarath Ganapathiraju via B4 Relay @ 2026-08-06 14:51 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Srinivas Kandagatla
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel,
prasad.kumpatla, Sarath Ganapathiraju
From: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the
start of the DMAs and Codec Interfaces for the audio usecases and
can serve as a periodic wakeup source for the DSP.
Add the LPASS VA CSR driver that models the rate generator as a clock
provider so it is enabled and disabled automatically alongside the
other clocks during runtime PM resume and suspend.
Signed-off-by: Sarath Ganapathiraju <sarath.ganapathiraju@oss.qualcomm.com>
---
drivers/clk/qcom/Kconfig | 14 ++++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/lpass-va-csr.c | 148 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 163 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index d1fc9bf87126..756f6ed727d0 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -2040,6 +2040,20 @@ config CLK_GFM_LPASS_SM8250
Support for the Glitch Free Mux (GFM) Low power audio
subsystem (LPASS) clocks found on SM8250 SoCs.
+config QCOM_CLK_LPASS_HEARTBEAT_PULSE
+ tristate "Qualcomm LPASS VA CSR heartbeat pulse clock provider"
+ depends on COMMON_CLK
+ depends on ARM64 || COMPILE_TEST
+ select REGMAP_MMIO
+ default m if ARCH_QCOM
+ help
+ Qualcomm LPASS VA CSR block contains the rate generator hardware
+ that produces the HeartBeat Pulse (also known as RateGen Pulse).
+ This driver models the rate generator as a clock provider so
+ that consumers can enable or disable it via the common clock
+ framework, and it can be used to synchronize the start of DMAs
+ and Codec Interfaces or as a periodic wakeup source for the DSP.
+
config SM_VIDEOCC_8450
tristate "SM8450 Video Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index daf25d583be2..8d3e3381bc29 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_CLK_ELIZA_DISPCC) += dispcc-eliza.o
obj-$(CONFIG_CLK_ELIZA_GCC) += gcc-eliza.o
obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o
obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
+obj-$(CONFIG_QCOM_CLK_LPASS_HEARTBEAT_PULSE) += lpass-va-csr.o
obj-$(CONFIG_CLK_GLYMUR_CAMCC) += camcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_EVACC) += evacc-glymur.o
diff --git a/drivers/clk/qcom/lpass-va-csr.c b/drivers/clk/qcom/lpass-va-csr.c
new file mode 100644
index 000000000000..2e692407a966
--- /dev/null
+++ b/drivers/clk/qcom/lpass-va-csr.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_clk.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/pm_runtime.h>
+
+#define LPASS_RATE_GEN_CTRL 0xd000
+#define LPASS_RATE_GEN_COUNTER_0 0xd004
+#define LPASS_RATE_GEN_DELAY 0xd010
+
+#define LPASS_RATE_GEN_MAX_REG LPASS_RATE_GEN_DELAY
+
+#define LPASS_RG_CTRL_EN BIT(0)
+
+struct lpass_va_csr_data {
+ u32 counter_0;
+ u32 delay;
+};
+
+static const struct lpass_va_csr_data hawi_csr_data = {
+ .counter_0 = 0x960,
+ .delay = 0x16,
+};
+
+static const struct regmap_config lpass_rate_gen_regmap_config = {
+ .name = "lpass_rate_gen",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = LPASS_RATE_GEN_MAX_REG,
+ .cache_type = REGCACHE_MAPLE,
+};
+
+struct lpass_va_csr {
+ struct regmap *regmap;
+ const struct lpass_va_csr_data *data;
+ struct clk_hw hb_hw;
+};
+
+#define to_lpass_va_csr(_hw) container_of(_hw, struct lpass_va_csr, hb_hw)
+
+static int heartbeat_pulse_prepare(struct clk_hw *hw)
+{
+ struct lpass_va_csr *csr = to_lpass_va_csr(hw);
+ int ret;
+
+ ret = regmap_write(csr->regmap, LPASS_RATE_GEN_COUNTER_0, csr->data->counter_0);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(csr->regmap, LPASS_RATE_GEN_DELAY, csr->data->delay);
+ if (ret)
+ return ret;
+
+ return regmap_set_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_EN);
+}
+
+static void heartbeat_pulse_unprepare(struct clk_hw *hw)
+{
+ struct lpass_va_csr *csr = to_lpass_va_csr(hw);
+
+ regmap_clear_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_EN);
+}
+
+static int heartbeat_pulse_is_prepared(struct clk_hw *hw)
+{
+ struct lpass_va_csr *csr = to_lpass_va_csr(hw);
+
+ return regmap_test_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_EN);
+}
+
+static const struct clk_ops heartbeat_pulse_ops = {
+ .prepare = heartbeat_pulse_prepare,
+ .unprepare = heartbeat_pulse_unprepare,
+ .is_prepared = heartbeat_pulse_is_prepared,
+};
+
+static int lpass_va_csr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct lpass_va_csr *csr;
+ struct clk_init_data init = {
+ .name = "lpass_heartbeat_pulse",
+ .ops = &heartbeat_pulse_ops,
+ };
+ void __iomem *base;
+ int ret;
+
+ csr = devm_kzalloc(dev, sizeof(*csr), GFP_KERNEL);
+ if (!csr)
+ return -ENOMEM;
+
+ csr->data = of_device_get_match_data(dev);
+ if (!csr->data)
+ return dev_err_probe(dev, -EINVAL, "no variant data for compatible\n");
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ csr->regmap = devm_regmap_init_mmio(dev, base,
+ &lpass_rate_gen_regmap_config);
+ if (IS_ERR(csr->regmap))
+ return dev_err_probe(dev, PTR_ERR(csr->regmap),
+ "failed to init regmap\n");
+
+ csr->hb_hw.init = &init;
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to enable PM runtime\n");
+
+ ret = devm_clk_hw_register(dev, &csr->hb_hw);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to register heartbeat clock\n");
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &csr->hb_hw);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to add clock provider\n");
+
+ return 0;
+}
+
+static const struct of_device_id lpass_va_csr_dt_match[] = {
+ { .compatible = "qcom,hawi-lpass-va-csr", .data = &hawi_csr_data },
+ {}
+};
+MODULE_DEVICE_TABLE(of, lpass_va_csr_dt_match);
+
+static struct platform_driver lpass_va_csr_driver = {
+ .driver = {
+ .name = "qcom-lpass-va-csr",
+ .of_match_table = lpass_va_csr_dt_match,
+ },
+ .probe = lpass_va_csr_probe,
+};
+
+module_platform_driver(lpass_va_csr_driver);
+
+MODULE_DESCRIPTION("Qualcomm LPASS VA CSR heartbeat pulse clock provider");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread