[PATCH v2 0/3] arm64: dts: freescale: add Free Mobile Nodebox v3 CPU Module (LX2160A)

[PATCH v2 0/3] arm64: dts: freescale: add Free Mobile Nodebox v3 CPU Module (LX2160A)

[Vincent Jardin via B4 Relay]

The Nodebox v3 is a Free Mobile CPU module built around the NXP LX2160A
(16x Cortex-A72, DPAA2).

The same fsl-lx2160a-nbxv3.dtsi shall be used verbatim by the
U-Boot port, sent in parallel to the U-Boot list, so the two trees
cannot drift.

XXX Dependency:

the DTS uses gpio hogs on the QorIQ GPIO controllers, which
needs the commit
  78c0baf85cd0 ("dt-bindings: gpio: fsl,qoriq-gpio: allow gpio-hog child nodes")
already in gpio/for-next and that will likely arrive in v7.4-rc1.
Until it lands, dtbs_check reports the five hog nodes, the rest of the
tree validates clean against the current schemas.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
Changes in v2: (from Sashiko's comments)
- Makefile: dtb entry in alphabetical order (before qds).
- Move the XSPI1_A_DATA[7:4] GPIO mux group from &fspi to &gpio1, so
  the reset hogs on gpio1 do not depend on the fspi probe.
- gpio hogs: describe ethsw-reset# and ethsw-mdio-en with their
  active-low polarity (GPIO_ACTIVE_LOW), same electrical levels.
- Link to v1: https://lore.kernel.org/r/20260907-for-upstream-nbxv3-dts-v1-0-f43fd0028b78@free.fr

---
Vincent Jardin (3):
      dt-bindings: vendor-prefixes: add Free Mobile
      dt-bindings: arm: fsl: add freemobile,nbxv3 board
      arm64: dts: freescale: add Nodebox v3 CPU Module

 Documentation/devicetree/bindings/arm/fsl.yaml     |   6 +
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 arch/arm64/boot/dts/freescale/Makefile             |   2 +
 .../arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dts |  34 ++
 .../boot/dts/freescale/fsl-lx2160a-nbxv3.dtsi      | 342 +++++++++++++++++++++
 5 files changed, 386 insertions(+)
---
base-commit: df2908090cda368b01ff43709f51890076c56157
change-id: 20260907-for-upstream-nbxv3-dts-bbecd04038a2

Best regards,
-- 
Vincent Jardin <vjardin@free.fr>

[PATCH v2 1/3] dt-bindings: vendor-prefixes: add Free Mobile

[Vincent Jardin via B4 Relay]

From: Vincent Jardin <vjardin@free.fr>

Free Mobile is a French mobile network operator. Add its vendor
prefix, used by the Nodebox v3 CPU Module (freemobile,nbxv3).

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ba20029693734..e467da45cd7ac 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -626,6 +626,8 @@ patternProperties:
     description: Freebox SAS
   "^freecom,.*":
     description: Freecom Gmbh
+  "^freemobile,.*":
+    description: Free Mobile
   "^frida,.*":
     description: Shenzhen Frida LCD Co., Ltd.
   "^friendlyarm,.*":

-- 
2.43.0

[PATCH v2 2/3] dt-bindings: arm: fsl: add freemobile,nbxv3 board

[Vincent Jardin via B4 Relay]

From: Vincent Jardin <vjardin@free.fr>

Add the Free Mobile Nodebox v3 CPU module to the list of
NXP, former Freescale, LX2160A-based boards.

The board's root is:
  "freemobile,nbxv3", "fsl,lx2160a"
and the DTS is at
  arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dts.

It is needed for
  make CHECK_DTBS=y

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 656f2596e1d53..baff4f4159b29 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1937,6 +1937,12 @@ properties:
               - fsl,lx2162a-qds
           - const: fsl,lx2160a
 
+      - description: Free Mobile LX2160A based Boards
+        items:
+          - enum:
+              - freemobile,nbxv3
+          - const: fsl,lx2160a
+
       - description: SolidRun LX2160A CEX-7 based Boards
         items:
           - enum:

-- 
2.43.0

[PATCH v2 3/3] arm64: dts: freescale: add Nodebox v3 CPU Module

[Vincent Jardin via B4 Relay]

From: Vincent Jardin <vjardin@free.fr>

The Nodebox v3 is a Free Mobile CPU module built around the NXP
LX2160A (16x Cortex-A72, DPAA2).

The same .dtsi is used by the U-Boot port, so both Linux and
u-boot should not drift.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
 arch/arm64/boot/dts/freescale/Makefile             |   2 +
 .../arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dts |  34 ++
 .../boot/dts/freescale/fsl-lx2160a-nbxv3.dtsi      | 342 +++++++++++++++++++++
 3 files changed, 378 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 95ae85ab4adf5..faab8bf0e1676 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -55,6 +55,8 @@ DTC_FLAGS_fsl-lx2160a-half-twins := -Wno-interrupt_map
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-half-twins.dtb
 DTC_FLAGS_fsl-lx2160a-honeycomb := -Wno-interrupt_map
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
+DTC_FLAGS_fsl-lx2160a-nbxv3 := -Wno-interrupt_map
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-nbxv3.dtb
 DTC_FLAGS_fsl-lx2160a-qds := -Wno-interrupt_map
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
 DTC_FLAGS_fsl-lx2160a-rdb := -Wno-interrupt_map
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dts
new file mode 100644
index 0000000000000..b07e9def0a529
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Free Mobile Nodebox v3 CPU Module (LX2160A)
+ *
+ * Copyright 2026 Free Mobile, Vincent Jardin
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-rev2.dtsi"
+#include "fsl-lx2160a-nbxv3.dtsi"
+
+/ {
+	model = "Free Mobile Nodebox v3 CPU Module (LX2160A)";
+	compatible = "freemobile,nbxv3", "fsl,lx2160a";
+};
+
+&fspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&fspi_dqs_sck_cs10_pins>, <&fspi_data30_pins>;
+};
+
+&gpio1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpio1_31_28_pins>;
+};
+
+&pcs_mdio13 {
+	status = "okay";
+};
+
+&pcs_mdio14 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dtsi
new file mode 100644
index 0000000000000..3357f1beddac9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dtsi
@@ -0,0 +1,342 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Free Mobile Nodebox v3 CPU Module (LX2160A)
+ *
+ * Copyright 2026 Free Mobile, Vincent Jardin
+ *
+ * This file is shared by the Linux kernel and U-Boot.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+		priority = <128>;
+	};
+};
+
+&crypto {
+	status = "okay";
+};
+
+&dspi0 {
+	status = "okay";
+
+	dpll@0 {
+		compatible = "microchip,zl30733";
+		reg = <0>;
+		spi-max-frequency = <12500000>;
+	};
+};
+
+&dspi2 {
+	status = "okay";
+};
+
+&dpmac13 {
+	status = "okay";
+	phy-handle = <&lan8023_phy_s0>;
+	phy-connection-type = "10gbase-r";
+};
+
+&dpmac14 {
+	status = "okay";
+	phy-handle = <&lan8023_phy_s1>;
+	phy-connection-type = "10gbase-r";
+};
+
+&dpmac17 {
+	status = "okay";
+	phy-handle = <&rtl8211fd>;
+	phy-connection-type = "rgmii-id";
+};
+
+&emdio1 {
+	status = "okay";
+
+	/* Microchip LAN8023 dual 10G PCS/retimer, Clause 45 only, one address per slice */
+	lan8023_phy_s0: ethernet-phy@2 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <2>;
+	};
+
+	lan8023_phy_s1: ethernet-phy@3 {
+		compatible = "ethernet-phy-ieee802.3-c45";
+		reg = <3>;
+	};
+
+	rtl8211fd: ethernet-phy@6 {
+		compatible = "ethernet-phy-id001c.c916";
+		reg = <6>;
+	};
+};
+
+&emdio2 {
+	status = "okay";
+};
+
+&esdhc1 {
+	status = "okay";
+	bus-width = <8>;
+	non-removable;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+};
+
+&fspi {
+	status = "okay";
+
+	/* GigaDevice GD55LB02GF, 256 MiB boot NOR */
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <150000000>;
+		spi-rx-bus-width = <1>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&fsl_mc {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+	gpio-line-names =
+		"", "",
+		"altfn:iic1-sda", "altfn:iic1-scl",
+		"altfn:uart4-sin", "altfn:uart4-sout",
+		"altfn:uart2-sin", "altfn:uart2-sout",
+		"altfn:uart3-sin", "altfn:uart3-sout",
+		"altfn:uart1-sin", "altfn:uart1-sout",
+		"altfn:spi3-pcs3", "altfn:spi3-pcs2",
+		"altfn:spi3-pcs1", "altfn:spi3-pcs0",
+		"altfn:spi1-sck", "altfn:spi1-sin",
+		"altfn:spi1-pcs2", "altfn:spi1-pcs1",
+		"altfn:spi1-pcs0", "altfn:spi1-sout",
+		"altfn:iic6-sda", "altfn:iic6-scl",
+		"altfn:spi3-sin", "altfn:spi3-sout",
+		"altfn:iic4-sda", "altfn:iic4-scl",
+		"altfn:iic3-sda", "altfn:iic3-scl",
+		"altfn:iic2-sda", "altfn:iic2-scl";
+};
+
+&gpio1 {
+	status = "okay";
+	gpio-line-names =
+		"", "", "", "", "", "",
+		"cfg-rcw-src2", "cfg-rcw-src3",
+		"reset-req-b",
+		"altfn:sdhc2-clk", "altfn:sdhc2-ds",
+		"altfn:sdhc2-dat0", "altfn:sdhc2-dat1",
+		"altfn:sdhc2-dat2", "altfn:sdhc2-dat3",
+		"altfn:sdhc2-dat4", "altfn:sdhc2-dat5",
+		"altfn:sdhc2-dat6", "altfn:sdhc2-dat7",
+		"altfn:sdhc2-cmd",
+		"cfg-svr1",
+		"altfn:xspi1-cs0", "altfn:xspi1-sck",
+		"thermtrip",
+		"altfn:xspi1-data0", "altfn:xspi1-data1",
+		"", "",
+		"flash-reset#", "pltrst#", "", "ethsw-reset#";
+
+	pltrst-hog {
+		gpio-hog;
+		gpios = <29 GPIO_ACTIVE_LOW>;
+		output-low;
+		line-name = "pltrst#";
+	};
+
+	thermtrip-hog {
+		gpio-hog;
+		gpios = <23 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "thermtrip";
+	};
+
+	/* Boot NOR reset, released: electrical high */
+	flash-reset-hog {
+		gpio-hog;
+		gpios = <28 GPIO_ACTIVE_LOW>;
+		output-low;
+		line-name = "flash-reset#";
+	};
+
+	/* Ethernet switch reset, released: electrical high */
+	ethsw-reset-hog {
+		gpio-hog;
+		gpios = <31 GPIO_ACTIVE_LOW>;
+		output-low;
+		line-name = "ethsw-reset#";
+	};
+};
+
+&gpio2 {
+	status = "okay";
+	gpio-line-names =
+		"lan8023-mdint",
+		"i2c2-alert#", "i2c4-alert#", "i2c6-alert#",
+		"u800-tca9539-int#",
+		"spi3-alert#",
+		"wake0", "wake1",
+		"carrier-hot#",
+		"u1300-rtl8211fd-int#",
+		"ethsw-int#",
+		"", "",
+		"u1700-zl30733-clk-gpio0", "u1700-zl30733-clk-gpio1",
+		"u1700-zl30733-clk-gpio2", "u1700-zl30733-clk-gpio3",
+		"", "", "", "", "", "", "", "",
+		"", "", "", "", "", "", "";
+};
+
+&gpio3 {
+	status = "okay";
+	gpio-line-names =
+		"altfn:ec1-txd3", "altfn:ec1-txd2",
+		"altfn:ec1-txd1", "altfn:ec1-txd0",
+		"altfn:ec1-tx-en", "altfn:ec1-gtx-clk",
+		"altfn:ec1-rxd3", "altfn:ec1-rxd2",
+		"altfn:ec1-rxd1", "altfn:ec1-rxd0",
+		"altfn:ec1-rx-clk", "altfn:ec1-rx-dv",
+		"", "",
+		"ptp-refclk-in",
+		"", "", "", "", "", "", "", "",
+		"u1700-zl30733-pps-out",
+		"",
+		"ethsw-mdio-en",
+		"usb01-oc#",	/* USB1_PWRFAULT and USB2_PWRFAULT share one net */
+		"",
+		"usb01-oc#",
+		"altfn:spi3-sck",
+		"", "";
+
+	/* Low enables the carrier-side EMDIO2 level translator */
+	ethsw-mdio-en-hog {
+		gpio-hog;
+		gpios = <25 GPIO_ACTIVE_LOW>;
+		output-high;
+		line-name = "ethsw-mdio-en";
+	};
+};
+
+/* On-module management bus */
+&i2c0 {
+	status = "okay";
+
+	eeprom@52 {
+		compatible = "atmel,24c32";
+		reg = <0x52>;
+		pagesize = <32>;
+	};
+
+	/* Board ID straps */
+	gpio@74 {
+		compatible = "ti,tca9539";
+		reg = <0x74>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names =
+			"boardid-0x0001", "boardid-0x0002",
+			"boardid-0x0004", "boardid-0x0008",
+			"boardid-0x0010", "boardid-0x0020",
+			"boardid-0x0040", "boardid-0x0080",
+			"boardid-0x0100", "boardid-0x0200",
+			"boardid-0x0400", "boardid-0x0800",
+			"boardid-0x1000", "boardid-0x2000",
+			"boardid-0x4000", "boardid-0x8000";
+	};
+
+	u800: gpio@75 {
+		compatible = "ti,tca9539";
+		reg = <0x75>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+		gpio-line-names =
+			"carrier-gpio0", "carrier-gpio1",
+			"carrier-gpio2", "carrier-gpio3",
+			"carrier-gpio4", "carrier-gpio5",
+			"carrier-gpio6", "carrier-gpio7",
+			"carrier-gpio8", "carrier-gpio9",
+			"carrier-gpio10", "carrier-gpio11",
+			"", "", "",
+			"lan8023-rst";
+	};
+
+	/* +0V8_VDD core rail, MPS MPQ8646 (MPQ8785 core) over PMBus */
+	vdd08: regulator@10 {
+		compatible = "mps,mpq8646";
+		reg = <0x10>;
+	};
+
+	/* SO-DIMM SPD temperature sensors */
+	temperature-sensor@18 {
+		compatible = "jedec,jc-42.4-temp";
+		reg = <0x18>;
+	};
+
+	temperature-sensor@19 {
+		compatible = "jedec,jc-42.4-temp";
+		reg = <0x19>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&pcie3 {
+	status = "okay";
+};
+
+&pcie4 {
+	status = "okay";
+};
+
+&pcie5 {
+	status = "okay";
+};
+
+&pcie6 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};

-- 
2.43.0

Re: [PATCH v2 3/3] arm64: dts: freescale: add Nodebox v3 CPU Module

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] GPIO hog 'thermtrip-hog' on gpio1 pin 23 structurally conflicts with the FSPI pin multiplexer configuration.
- [Medium] The FSPI flash is artificially restricted to 1-bit bus width despite the hardware being wired for 4-bit Quad SPI.
- [Medium] Ethernet PHYs are missing their hardware interrupt assignments, forcing the kernel into inefficient polling mode.
- [Medium] The LAN8023 PHY nodes are missing the `reset-gpios` property, leaving the PHY unreset during initialization.
--

commit 7aa7c67b7fab76be5b6b8b173d9fb60dc30944d9
Author: Vincent Jardin <vjardin@free.fr>
Subject: arm64: dts: freescale: add Nodebox v3 CPU Module

This commit introduces the device tree files for the Free Mobile Nodebox v3 CPU
Module based on the NXP LX2160A SoC. It configures the SPI, MDIO, Ethernet, and
GPIO controllers for the board.

> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dts
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dts

[ ... ]

> +&fspi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&fspi_dqs_sck_cs10_pins>, <&fspi_data30_pins>;
> +};

[Severity: High]
Does this pinmux configuration conflict with the thermtrip-hog defined on gpio1
pin 23?

During boot, the pin controller configures the RCWPMUXCR0 register (via
fspi_dqs_sck_cs10_pins) to route pins 20-23 to the FSPI (XSPI1) controller en
masse. Concurrently, the GPIO driver applies the thermtrip-hog to pin 23 in
fsl-lx2160a-nbxv3.dtsi, attempting to drive it low as a GPIO.

Because the pin multiplexer strictly routes pin 23 to FSPI instead of the GPIO
controller, the GPIO hog will fail to control the physical pad. Furthermore,
the FSPI controller will actively drive pin 23 during SPI accesses, which can
inadvertently toggle the thermal trip line and cause unexpected hardware
shutdowns.

[ ... ]

> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dtsi
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-nbxv3.dtsi

[ ... ]

> +&emdio1 {
> +	status = "okay";
> +
> +	/* Microchip LAN8023 dual 10G PCS/retimer, Clause 45 only, one address per slice */
> +	lan8023_phy_s0: ethernet-phy@2 {
> +		compatible = "ethernet-phy-ieee802.3-c45";
> +		reg = <2>;
> +	};

[Severity: Medium]
Will this force the kernel into an inefficient polling mode for the Ethernet
PHYs?

The hardware possesses dedicated interrupt lines for the PHYs, as the gpio2
node explicitly defines the line names 'lan8023-mdint' and
'u1300-rtl8211fd-int#'. Without interrupts and interrupt-parent properties in
the PHY nodes (lan8023_phy_s0, lan8023_phy_s1, and rtl8211fd), the PHY driver
will fall back to periodically polling the MDIO bus to check for link state
changes.

[Severity: Medium]
Should this node also include a reset-gpios property to ensure the PHY is
properly initialized?

The u800 I2C GPIO expander explicitly defines line 15 as 'lan8023-rst'.
Without claiming this GPIO (e.g., reset-gpios = <&u800 15 GPIO_ACTIVE_LOW>),
the Ethernet driver will not execute a hardware reset sequence during probing,
leaving the hardware dependent on the state the bootloader left it in and
potentially failing to recover from a suspended state.

[ ... ]

> +&fspi {
> +	status = "okay";
> +
> +	/* GigaDevice GD55LB02GF, 256 MiB boot NOR */
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		spi-max-frequency = <150000000>;
> +		spi-rx-bus-width = <1>;
> +		spi-tx-bus-width = <1>;
> +	};
> +};

[Severity: Medium]
Does this artificially restrict the FSPI flash to a 1-bit bus width despite the
hardware being wired for 4-bit Quad SPI?

The pinctrl-0 property in the .dts file includes <&fspi_data30_pins>, which
configures four data lines (DATA[3:0]) for the FSPI controller. However, this
flash@0 node sets the spi-rx-bus-width and spi-tx-bus-width to 1. This mismatch
forces the SPI NOR flash driver to operate in single-bit mode rather than
quad mode, needlessly degrading I/O performance.

[ ... ]

> +&gpio1 {
> +	status = "okay";

[ ... ]

> +	thermtrip-hog {
> +		gpio-hog;
> +		gpios = <23 GPIO_ACTIVE_HIGH>;
> +		output-low;
> +		line-name = "thermtrip";
> +	};

[Severity: High]
Does this GPIO hog structurally conflict with the FSPI pin multiplexer
configuration in the .dts file?

As mentioned earlier, the fspi node routes pin 23 to the FSPI controller,
meaning the GPIO controller is disconnected from the physical pad. Attempting
to hog it here will fail and may allow the SPI controller to inadvertently
trigger the thermal trip line during accesses.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260907-for-upstream-nbxv3-dts-v2-0-6b4afd36180b@free.fr?part=3

Re: [PATCH v2 3/3] arm64: dts: freescale: add Nodebox v3 CPU Module

[Vincent Jardin]

Hi M. Bot,

I'll submit a v3 update tomorrow.

See below for the few other topics,

> > +&fspi {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&fspi_dqs_sck_cs10_pins>, <&fspi_data30_pins>;
> > +};
> 
> [Severity: High]
> Does this pinmux configuration conflict with the thermtrip-hog defined on gpio1
> pin 23?
> 
> During boot, the pin controller configures the RCWPMUXCR0 register (via
> fspi_dqs_sck_cs10_pins) to route pins 20-23 to the FSPI (XSPI1) controller en
> masse. Concurrently, the GPIO driver applies the thermtrip-hog to pin 23 in
> fsl-lx2160a-nbxv3.dtsi, attempting to drive it low as a GPIO.

Correct, it is something I should have cleaned sooner. I'll be removed into the
next update.

> > +&emdio1 {
> > +	status = "okay";
> > +
> > +	/* Microchip LAN8023 dual 10G PCS/retimer, Clause 45 only, one address per slice */
> > +	lan8023_phy_s0: ethernet-phy@2 {
> > +		compatible = "ethernet-phy-ieee802.3-c45";
> > +		reg = <2>;
> > +	};
> 
> [Severity: Medium]
> Will this force the kernel into an inefficient polling mode for the Ethernet
> PHYs?
> 
> The hardware possesses dedicated interrupt lines for the PHYs, as the gpio2
> node explicitly defines the line names 'lan8023-mdint' and
> 'u1300-rtl8211fd-int#'. Without interrupts and interrupt-parent properties in
> the PHY nodes (lan8023_phy_s0, lan8023_phy_s1, and rtl8211fd), the PHY driver
> will fall back to periodically polling the MDIO bus to check for link state
> changes.

The lines do exist and gpio2 is an interrupt-controller, so this can be
added. I'd prefer to keep it for a future update.

> [Severity: Medium]
> Should this node also include a reset-gpios property to ensure the PHY is
> properly initialized?
> 
> The u800 I2C GPIO expander explicitly defines line 15 as 'lan8023-rst'.
> Without claiming this GPIO (e.g., reset-gpios = <&u800 15 GPIO_ACTIVE_LOW>),
> the Ethernet driver will not execute a hardware reset sequence during probing,
> leaving the hardware dependent on the state the bootloader left it in and
> potentially failing to recover from a suspended state.

It is a single reset shared by both slices of the one LAN8023, so it cannot be
claimed by both.
The reset is owned by the bring-up userland application of the lan8023.

> > +&fspi {
> > +	status = "okay";
> > +
> > +	/* GigaDevice GD55LB02GF, 256 MiB boot NOR */
> > +	flash@0 {
> > +		compatible = "jedec,spi-nor";
> > +		reg = <0>;
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		spi-max-frequency = <150000000>;
> > +		spi-rx-bus-width = <1>;
> > +		spi-tx-bus-width = <1>;
> > +	};
> > +};
> 
> [Severity: Medium]
> Does this artificially restrict the FSPI flash to a 1-bit bus width despite the
> hardware being wired for 4-bit Quad SPI?
> 
> The pinctrl-0 property in the .dts file includes <&fspi_data30_pins>, which
> configures four data lines (DATA[3:0]) for the FSPI controller. However, this
> flash@0 node sets the spi-rx-bus-width and spi-tx-bus-width to 1. This mismatch
> forces the SPI NOR flash driver to operate in single-bit mode rather than
> quad mode, needlessly degrading I/O performance.

Deliberately on purpose for this board ! for the time being.

Thanks,
  Vincent
 
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20260907-for-upstream-nbxv3-dts-v2-0-6b4afd36180b@free.fr?part=3