[PATCH v3 00/13] Add support for DU, LVDS and DSI on the Renesas RZ/G3L SoC

[PATCH v3 00/13] Add support for DU, LVDS and DSI on the Renesas RZ/G3L SoC

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Hi All,

This patch series aims to add DSI, LVDS and LCD support for the RZ/G3L
SMARC EVK. The RZ/G3L LCDC is similar to the one found on RZ/G2L, but has
LVDS support.

Patch#4 has build dependency on [1]
[1] https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git/commit/?id=d51fc9d4cd6eb18ac82913d83ecf7bd8c85f71ee

v2->v3:
 * Dropped binding patches as it is accepted.
 * Collected tags.
 * Dropped .dsi_global_timings from rzv2h_mipi_dsi_info as it uses
   different path.
 * Updated powerseq API names.
 * Moved set duty cycle from bridge driver to DU encoder.
 * Added min/max frequencies for DPI.
v1->v2:
 * Dropped renesas,sysc-pwrrdy property as it is modelled as power
   sequence.
 * Switched to power sequence for handling pwrrdy signal.
 * Dropped header file regmap.h and mfd/syscon.h
 * Added header file pwrseq/consumer.h
 * Replaced syscon_field->pwrrdy in struct rzg3l_mipi_dsi_info.
 * Restored ports in DU bindings.
 * Replaced endpoint with port in ports node.
 * Dropped the macro RZG2L_DU_FEATURE_SMUX2_DSI_CLK and RZG2L_DU_MAX_LVDS.
 * Dropped the variable rcdu from struct rzg2l_du_encoder.
 * Dropped the variable lvds from struct rzg2l_du_device.
 * Dropped renesas,sysc-pwrrdy from dsi node.

Biju Das (13):
  drm: renesas: rzg2l_mipi_dsi: Add dphyctrl0_init_val to hw_info
  drm: renesas: rzg2l_mipi_dsi: Add activation_dly to hw_info
  drm: renesas: rzg2l_mipi_dsi: Move global timings into hardware info
    struct
  drm: renesas: rzg2l_mipi_dsi: Add support for DSI PWRRDY
  drm: renesas: rzg2l_mipi_dsi: Add RZ/G3L MIPI DSI support
  drm: renesas: rz-du: Add RZ/G3L (R9A08G046) DU support
  drm: renesas: rz-du: Add support for RZ/G3L LVDS encoder
  arm64: dts: renesas: r9a08g046: Add fcpvd node
  arm64: dts: renesas: r9a08g046: Add vspd node
  arm64: dts: renesas: r9a08g046: Add DU and DSI nodes
  arm64: dts: renesas: r9a08g046: Add LVDS node
  arm64: dts: renesas: Add DSI overlay for RZ/G3L SMARC EVK with ADV7535
  arm64: dts: renesas: Add LVDS overlay for RZ/G3L SMARC EVK with
    ITE6263

 arch/arm64/boot/dts/renesas/Makefile          |   6 +
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi    | 139 +++++++++
 .../r9a08g046l48-smarc-dsi-adv7535.dtso       |  95 ++++++
 .../r9a08g046l48-smarc-lvds-ite6263.dtso      | 104 ++++++
 drivers/gpu/drm/renesas/rz-du/Kconfig         |  13 +
 drivers/gpu/drm/renesas/rz-du/Makefile        |   1 +
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c  |  24 +-
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h  |   3 +-
 .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.c  |  24 ++
 .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c    | 174 ++++++++++-
 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c    | 295 ++++++++++++++++++
 .../gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h   |  25 ++
 12 files changed, 895 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-dsi-adv7535.dtso
 create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.dtso
 create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c
 create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h

-- 
2.43.0

[PATCH v3 08/13] arm64: dts: renesas: r9a08g046: Add fcpvd node

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add fcpvd node to RZ/G3L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * No change.
---
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 9f5ea62efc2c..ad38aee2efb3 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -696,6 +696,17 @@ ssi3: ssi@100e4c00 {
 			status = "disabled";
 		};
 
+		fcpvd: fcp@10880000 {
+			compatible = "renesas,r9a08g046-fcpvd", "renesas,fcpv";
+			reg = <0 0x10880000 0 0x10000>;
+			clocks = <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>,
+				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>,
+				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>;
+			clock-names = "aclk", "pclk", "vclk";
+			resets = <&cpg R9A08G046_LCDC_RESET_N>;
+			power-domains = <&cpg>;
+		};
+
 		gpu: gpu@108b0000 {
 			compatible = "renesas,r9a08g046-mali",
 				     "arm,mali-bifrost";
-- 
2.43.0

Re: [PATCH v3 08/13] arm64: dts: renesas: r9a08g046: Add fcpvd node

[Tommaso Merciai]

Hi Biju,
Thanks for your patch.

On Wed, Aug 26, 2026 at 06:48:42PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Add fcpvd node to RZ/G3L SoC DTSI.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * No change.
> v1->v2:
>  * No change.
> ---
>  arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index 9f5ea62efc2c..ad38aee2efb3 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> @@ -696,6 +696,17 @@ ssi3: ssi@100e4c00 {
>  			status = "disabled";
>  		};
>  
> +		fcpvd: fcp@10880000 {
> +			compatible = "renesas,r9a08g046-fcpvd", "renesas,fcpv";
> +			reg = <0 0x10880000 0 0x10000>;
> +			clocks = <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>,
> +				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>,
> +				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>;
> +			clock-names = "aclk", "pclk", "vclk";
> +			resets = <&cpg R9A08G046_LCDC_RESET_N>;
> +			power-domains = <&cpg>;

Maybe for consistency with:

	- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
	- arch/arm64/boot/dts/renesas/r9a07g044.dtsi
	- arch/arm64/boot/dts/renesas/r9a07g054.dtsi

You can move reset entry to the latest position.
Apart from that LGTM.

Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Kind regards,
Tommaso

> +		};
> +
>  		gpu: gpu@108b0000 {
>  			compatible = "renesas,r9a08g046-mali",
>  				     "arm,mali-bifrost";
> -- 
> 2.43.0
> 

Re: [PATCH v3 08/13] arm64: dts: renesas: r9a08g046: Add fcpvd node

[Geert Uytterhoeven]

On Thu, 27 Aug 2026 at 12:35, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> On Wed, Aug 26, 2026 at 06:48:42PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add fcpvd node to RZ/G3L SoC DTSI.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2->v3:
> >  * No change.
> > v1->v2:
> >  * No change.
> > ---
> >  arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > index 9f5ea62efc2c..ad38aee2efb3 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > @@ -696,6 +696,17 @@ ssi3: ssi@100e4c00 {
> >                       status = "disabled";
> >               };
> >
> > +             fcpvd: fcp@10880000 {
> > +                     compatible = "renesas,r9a08g046-fcpvd", "renesas,fcpv";
> > +                     reg = <0 0x10880000 0 0x10000>;
> > +                     clocks = <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>,
> > +                              <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>,
> > +                              <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>;
> > +                     clock-names = "aclk", "pclk", "vclk";
> > +                     resets = <&cpg R9A08G046_LCDC_RESET_N>;
> > +                     power-domains = <&cpg>;
>
> Maybe for consistency with:
>
>         - arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
>         - arch/arm64/boot/dts/renesas/r9a07g044.dtsi
>         - arch/arm64/boot/dts/renesas/r9a07g054.dtsi
>
> You can move reset entry to the latest position.
> Apart from that LGTM.
>
> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.4 with reset moved.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 09/13] arm64: dts: renesas: r9a08g046: Add vspd node

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add vspd node to RZ/G3L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * No change.
---
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index ad38aee2efb3..6ff145dc81fa 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -696,6 +696,20 @@ ssi3: ssi@100e4c00 {
 			status = "disabled";
 		};
 
+		vspd: vsp@10870000 {
+			compatible = "renesas,r9a08g046-vsp2",
+				     "renesas,r9a07g044-vsp2";
+			reg = <0 0x10870000 0 0x10000>;
+			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>,
+				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>,
+				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>;
+			clock-names = "aclk", "pclk", "vclk";
+			resets = <&cpg R9A08G046_LCDC_RESET_N>;
+			power-domains = <&cpg>;
+			renesas,fcp = <&fcpvd>;
+		};
+
 		fcpvd: fcp@10880000 {
 			compatible = "renesas,r9a08g046-fcpvd", "renesas,fcpv";
 			reg = <0 0x10880000 0 0x10000>;
-- 
2.43.0

Re: [PATCH v3 09/13] arm64: dts: renesas: r9a08g046: Add vspd node

[Tommaso Merciai]

Hi Biju,
Thanks for your patch.

On Wed, Aug 26, 2026 at 06:48:43PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Add vspd node to RZ/G3L SoC DTSI.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * No change.
> v1->v2:
>  * No change.
> ---
>  arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index ad38aee2efb3..6ff145dc81fa 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> @@ -696,6 +696,20 @@ ssi3: ssi@100e4c00 {
>  			status = "disabled";
>  		};
>  
> +		vspd: vsp@10870000 {
> +			compatible = "renesas,r9a08g046-vsp2",
> +				     "renesas,r9a07g044-vsp2";
> +			reg = <0 0x10870000 0 0x10000>;
> +			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>,
> +				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>,
> +				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>;
> +			clock-names = "aclk", "pclk", "vclk";
> +			resets = <&cpg R9A08G046_LCDC_RESET_N>;
> +			power-domains = <&cpg>;

Same here IMHO we can switch resets with power-domains position.
Apart from that LGTM.

Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Kind regards,
Tommaso

> +			renesas,fcp = <&fcpvd>;
> +		};
> +
>  		fcpvd: fcp@10880000 {
>  			compatible = "renesas,r9a08g046-fcpvd", "renesas,fcpv";
>  			reg = <0 0x10880000 0 0x10000>;
> -- 
> 2.43.0
> 

Re: [PATCH v3 09/13] arm64: dts: renesas: r9a08g046: Add vspd node

[Geert Uytterhoeven]

On Thu, 27 Aug 2026 at 12:39, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> On Wed, Aug 26, 2026 at 06:48:43PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add vspd node to RZ/G3L SoC DTSI.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

> > --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > @@ -696,6 +696,20 @@ ssi3: ssi@100e4c00 {
> >                       status = "disabled";
> >               };
> >
> > +             vspd: vsp@10870000 {
> > +                     compatible = "renesas,r9a08g046-vsp2",
> > +                                  "renesas,r9a07g044-vsp2";
> > +                     reg = <0 0x10870000 0 0x10000>;
> > +                     interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
> > +                     clocks = <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>,
> > +                              <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>,
> > +                              <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>;
> > +                     clock-names = "aclk", "pclk", "vclk";
> > +                     resets = <&cpg R9A08G046_LCDC_RESET_N>;
> > +                     power-domains = <&cpg>;
>
> Same here IMHO we can switch resets with power-domains position.
> Apart from that LGTM.
>
> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.4 with reset moved.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 10/13] arm64: dts: renesas: r9a08g046: Add DU and DSI nodes

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add DU and DSI nodes to RZ/G3L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * Dropped renesas,sysc-pwrrdy from dsi node.
---
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 77 ++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index 6ff145dc81fa..cc8bfb24da87 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -696,6 +696,49 @@ ssi3: ssi@100e4c00 {
 			status = "disabled";
 		};
 
+		dsi: dsi@10850000 {
+			compatible = "renesas,r9a08g046-mipi-dsi";
+			reg = <0 0x10850000 0 0x20000>;
+			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "seq0", "seq1", "vin1", "rcv",
+					  "ferr", "ppi", "debug";
+			clocks = <&cpg CPG_CORE R9A08G046_MIPI_DSI_PLLCLK>,
+				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_SYSCLK>,
+				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_ACLK>,
+				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
+				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_VCLK>,
+				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_LPCLK>;
+			clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
+			resets = <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
+				 <&cpg R9A08G046_MIPI_DSI_ARESET_N>,
+				 <&cpg R9A08G046_MIPI_DSI_PRESET_N>;
+			reset-names = "rst", "arst", "prst";
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dsi_in: endpoint {
+						remote-endpoint = <&du_out_dsi>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+			};
+		};
+
 		vspd: vsp@10870000 {
 			compatible = "renesas,r9a08g046-vsp2",
 				     "renesas,r9a07g044-vsp2";
@@ -721,6 +764,40 @@ fcpvd: fcp@10880000 {
 			power-domains = <&cpg>;
 		};
 
+		du: display@10890000 {
+			compatible = "renesas,r9a08g046-du";
+			reg = <0 0x10890000 0 0x10000>;
+			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>,
+				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>,
+				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>;
+			clock-names = "aclk", "pclk", "vclk";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G046_LCDC_RESET_N>;
+			renesas,vsps = <&vspd 0>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					du_out_dsi: endpoint {
+						remote-endpoint = <&dsi_in>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+				};
+
+				port@2 {
+					reg = <2>;
+				};
+			};
+		};
+
 		gpu: gpu@108b0000 {
 			compatible = "renesas,r9a08g046-mali",
 				     "arm,mali-bifrost";
-- 
2.43.0

Re: [PATCH v3 10/13] arm64: dts: renesas: r9a08g046: Add DU and DSI nodes

[Tommaso Merciai]

Hi Biju,
Thanks for your patch.

On Wed, Aug 26, 2026 at 06:48:44PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Add DU and DSI nodes to RZ/G3L SoC DTSI.
> 

Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Kind regards,
Tommaso

> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * No change.
> v1->v2:
>  * Dropped renesas,sysc-pwrrdy from dsi node.
> ---
>  arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 77 ++++++++++++++++++++++
>  1 file changed, 77 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index 6ff145dc81fa..cc8bfb24da87 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> @@ -696,6 +696,49 @@ ssi3: ssi@100e4c00 {
>  			status = "disabled";
>  		};
>  
> +		dsi: dsi@10850000 {
> +			compatible = "renesas,r9a08g046-mipi-dsi";
> +			reg = <0 0x10850000 0 0x20000>;
> +			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "seq0", "seq1", "vin1", "rcv",
> +					  "ferr", "ppi", "debug";
> +			clocks = <&cpg CPG_CORE R9A08G046_MIPI_DSI_PLLCLK>,
> +				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_SYSCLK>,
> +				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_ACLK>,
> +				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
> +				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_VCLK>,
> +				 <&cpg CPG_MOD R9A08G046_MIPI_DSI_LPCLK>;
> +			clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
> +			resets = <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
> +				 <&cpg R9A08G046_MIPI_DSI_ARESET_N>,
> +				 <&cpg R9A08G046_MIPI_DSI_PRESET_N>;
> +			reset-names = "rst", "arst", "prst";
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +					dsi_in: endpoint {
> +						remote-endpoint = <&du_out_dsi>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +				};
> +			};
> +		};
> +
>  		vspd: vsp@10870000 {
>  			compatible = "renesas,r9a08g046-vsp2",
>  				     "renesas,r9a07g044-vsp2";
> @@ -721,6 +764,40 @@ fcpvd: fcp@10880000 {
>  			power-domains = <&cpg>;
>  		};
>  
> +		du: display@10890000 {
> +			compatible = "renesas,r9a08g046-du";
> +			reg = <0 0x10890000 0 0x10000>;
> +			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD R9A08G046_LCDC_CLK_A>,
> +				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_P>,
> +				 <&cpg CPG_MOD R9A08G046_LCDC_CLK_D>;
> +			clock-names = "aclk", "pclk", "vclk";
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A08G046_LCDC_RESET_N>;
> +			renesas,vsps = <&vspd 0>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +					du_out_dsi: endpoint {
> +						remote-endpoint = <&dsi_in>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +				};
> +
> +				port@2 {
> +					reg = <2>;
> +				};
> +			};
> +		};
> +
>  		gpu: gpu@108b0000 {
>  			compatible = "renesas,r9a08g046-mali",
>  				     "arm,mali-bifrost";
> -- 
> 2.43.0
> 

Re: [PATCH v3 10/13] arm64: dts: renesas: r9a08g046: Add DU and DSI nodes

[Geert Uytterhoeven]

On Thu, 27 Aug 2026 at 14:58, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> On Wed, Aug 26, 2026 at 06:48:44PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add DU and DSI nodes to RZ/G3L SoC DTSI.
>
> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.4 with DSI resets moved.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 11/13] arm64: dts: renesas: r9a08g046: Add LVDS node

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add LVDS node to RZ/G3L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * No change.
---
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 37 ++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index cc8bfb24da87..f652ad3f1d1a 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -794,6 +794,43 @@ port@1 {
 
 				port@2 {
 					reg = <2>;
+					du_out_lvds: endpoint {
+						remote-endpoint = <&lvds_in>;
+					};
+				};
+			};
+		};
+
+		lvds: lvds@108a0000 {
+			compatible = "renesas,r9a08g046-lvds";
+			reg = <0 0x108a0000 0 0x10000>;
+			clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
+				 <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>,
+				 <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>;
+			clock-names = "pclk", "phyclk", "dotclk";
+			resets = <&cpg R9A08G046_LVDS_RESET_N>,
+				 <&cpg R9A08G046_MIPI_DSI_PRESET_N>,
+				 <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
+				 <&cpg R9A08G046_MIPI_DSI_ARESET_N>;
+			reset-names = "lvdrst", "prst", "rst", "arst";
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					lvds_in: endpoint {
+						remote-endpoint = <&du_out_lvds>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					lvds_out: endpoint {
+					};
 				};
 			};
 		};
-- 
2.43.0

Re: [PATCH v3 11/13] arm64: dts: renesas: r9a08g046: Add LVDS node

[Tommaso Merciai]

On Wed, Aug 26, 2026 at 06:48:45PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Add LVDS node to RZ/G3L SoC DTSI.
>

Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * No change.
> v1->v2:
>  * No change.
> ---
>  arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 37 ++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> index cc8bfb24da87..f652ad3f1d1a 100644
> --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> @@ -794,6 +794,43 @@ port@1 {
>  
>  				port@2 {
>  					reg = <2>;
> +					du_out_lvds: endpoint {
> +						remote-endpoint = <&lvds_in>;
> +					};
> +				};
> +			};
> +		};
> +
> +		lvds: lvds@108a0000 {
> +			compatible = "renesas,r9a08g046-lvds";
> +			reg = <0 0x108a0000 0 0x10000>;
> +			clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>,
> +				 <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>,
> +				 <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>;
> +			clock-names = "pclk", "phyclk", "dotclk";
> +			resets = <&cpg R9A08G046_LVDS_RESET_N>,
> +				 <&cpg R9A08G046_MIPI_DSI_PRESET_N>,
> +				 <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>,
> +				 <&cpg R9A08G046_MIPI_DSI_ARESET_N>;
> +			reset-names = "lvdrst", "prst", "rst", "arst";
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +					lvds_in: endpoint {
> +						remote-endpoint = <&du_out_lvds>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +					lvds_out: endpoint {
> +					};
>  				};
>  			};
>  		};
> -- 
> 2.43.0
> 

Re: [PATCH v3 11/13] arm64: dts: renesas: r9a08g046: Add LVDS node

[Geert Uytterhoeven]

On Wed, 26 Aug 2026 at 19:49, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add LVDS node to RZ/G3L SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.4 with resets moved.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 12/13] arm64: dts: renesas: Add DSI overlay for RZ/G3L SMARC EVK with ADV7535

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add a Device Tree overlay (r9a08g046l48-smarc-dsi-adv7535.dtso) for the
RZ/G3L (R9A08G046) SMARC EVK board to support DSI-to-HDMI output via the
Analog Devices ADV7535 HDMI transmitter.

The overlay enables the DSI controller with a 4-lane data path and the
display unit (DU/LCDC), and configures the ADV7535 on I2C2.

Update the Makefile to build the overlay as both a standalone .dtbo and
a composite .dtb (base DTB + overlay).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * No change.
---
 arch/arm64/boot/dts/renesas/Makefile          |  3 +
 .../r9a08g046l48-smarc-dsi-adv7535.dtso       | 95 +++++++++++++++++++
 2 files changed, 98 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-dsi-adv7535.dtso

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 8bf155badd11..8c6a44890715 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -187,6 +187,9 @@ r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-sma
 dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtb
 
 dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc.dtb
+dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc-dsi-adv7535.dtbo
+r9a08g046l48-smarc-dsi-adv7535-dtbs := r9a08g046l48-smarc.dtb r9a08g046l48-smarc-dsi-adv7535.dtbo
+dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc-dsi-adv7535.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
 
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-dsi-adv7535.dtso b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-dsi-adv7535.dtso
new file mode 100644
index 000000000000..cede3b4ba318
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-dsi-adv7535.dtso
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree overlay for the RZ/G3L SMARC EVK with ADV7535
+ * connected to DSI and LCDC enabled.
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h>
+
+&{/} {
+	osc1: cec-clock {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <12000000>;
+	};
+
+	dsi-to-hdmi-out {
+		compatible = "hdmi-connector";
+		type = "d";
+
+		port {
+			dsi_to_hdmi_con_out: endpoint {
+				remote-endpoint = <&adv7535_out>;
+			};
+		};
+	};
+};
+
+&dsi {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@1 {
+			reg = <1>;
+			dsi_out: endpoint {
+				data-lanes = <1 2 3 4>;
+				remote-endpoint = <&adv7535_in>;
+			};
+		};
+	};
+};
+
+&du {
+	status = "okay";
+};
+
+&i2c2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	adv7535: hdmi@3d {
+		compatible = "adi,adv7535";
+		reg = <0x3d>;
+
+		interrupts-extended = <&pinctrl RZG3L_GPIO(K, 3) IRQ_TYPE_EDGE_FALLING>;
+		clocks = <&osc1>;
+		clock-names = "cec";
+		avdd-supply = <&reg_1p8v>;
+		dvdd-supply = <&reg_1p8v>;
+		pvdd-supply = <&reg_1p8v>;
+		a2vdd-supply = <&reg_1p8v>;
+		v3p3-supply = <&reg_3p3v>;
+		v1p2-supply = <&reg_1p8v>;
+
+		adi,dsi-lanes = <4>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				adv7535_in: endpoint {
+					remote-endpoint = <&dsi_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				adv7535_out: endpoint {
+					remote-endpoint = <&dsi_to_hdmi_con_out>;
+				};
+			};
+		};
+	};
+};
-- 
2.43.0

Re: [PATCH v3 12/13] arm64: dts: renesas: Add DSI overlay for RZ/G3L SMARC EVK with ADV7535

[Geert Uytterhoeven]

Hi Biju,

On Wed, 26 Aug 2026 at 19:49, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add a Device Tree overlay (r9a08g046l48-smarc-dsi-adv7535.dtso) for the
> RZ/G3L (R9A08G046) SMARC EVK board to support DSI-to-HDMI output via the
> Analog Devices ADV7535 HDMI transmitter.
>
> The overlay enables the DSI controller with a 4-lane data path and the
> display unit (DU/LCDC), and configures the ADV7535 on I2C2.
>
> Update the Makefile to build the overlay as both a standalone .dtbo and
> a composite .dtb (base DTB + overlay).
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-dsi-adv7535.dtso
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: GPL-2.0

Any chance this can be "(GPL-2.0-only OR BSD-2-Clause)", like all
already existing arch/arm64/boot/dts/renesas/r9a08g046* files
(and arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi)?


> +/*
> + * Device Tree overlay for the RZ/G3L SMARC EVK with ADV7535
> + * connected to DSI and LCDC enabled.
> + *
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h>
> +
> +&{/} {
> +       osc1: cec-clock {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <12000000>;
> +       };
> +
> +       dsi-to-hdmi-out {
> +               compatible = "hdmi-connector";
> +               type = "d";

No ddc-i2c-bus?

> +
> +               port {
> +                       dsi_to_hdmi_con_out: endpoint {
> +                               remote-endpoint = <&adv7535_out>;
> +                       };
> +               };
> +       };
> +};
> +
> +&dsi {
> +       status = "okay";
> +
> +       ports {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               port@1 {
> +                       reg = <1>;
> +                       dsi_out: endpoint {
> +                               data-lanes = <1 2 3 4>;
> +                               remote-endpoint = <&adv7535_in>;
> +                       };
> +               };
> +       };
> +};
> +
> +&du {
> +       status = "okay";
> +};
> +
> +&i2c2 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +
> +       adv7535: hdmi@3d {
> +               compatible = "adi,adv7535";
> +               reg = <0x3d>;
> +
> +               interrupts-extended = <&pinctrl RZG3L_GPIO(K, 3) IRQ_TYPE_EDGE_FALLING>;
> +               clocks = <&osc1>;
> +               clock-names = "cec";
> +               avdd-supply = <&reg_1p8v>;
> +               dvdd-supply = <&reg_1p8v>;
> +               pvdd-supply = <&reg_1p8v>;
> +               a2vdd-supply = <&reg_1p8v>;
> +               v3p3-supply = <&reg_3p3v>;
> +               v1p2-supply = <&reg_1p8v>;
> +
> +               adi,dsi-lanes = <4>;
> +
> +               ports {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       port@0 {
> +                               reg = <0>;
> +                               adv7535_in: endpoint {
> +                                       remote-endpoint = <&dsi_out>;
> +                               };
> +                       };
> +
> +                       port@1 {
> +                               reg = <1>;
> +                               adv7535_out: endpoint {
> +                                       remote-endpoint = <&dsi_to_hdmi_con_out>;
> +                               };
> +                       };

No audio?

> +               };
> +       };
> +};

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v3 12/13] arm64: dts: renesas: Add DSI overlay for RZ/G3L SMARC EVK with ADV7535

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 08 September 2026 14:25
> Subject: Re: [PATCH v3 12/13] arm64: dts: renesas: Add DSI overlay for RZ/G3L SMARC EVK with ADV7535
> 
> Hi Biju,
> 
> On Wed, 26 Aug 2026 at 19:49, Biju <biju.das.au@gmail.com> wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add a Device Tree overlay (r9a08g046l48-smarc-dsi-adv7535.dtso) for
> > the RZ/G3L (R9A08G046) SMARC EVK board to support DSI-to-HDMI output
> > via the Analog Devices ADV7535 HDMI transmitter.
> >
> > The overlay enables the DSI controller with a 4-lane data path and the
> > display unit (DU/LCDC), and configures the ADV7535 on I2C2.
> >
> > Update the Makefile to build the overlay as both a standalone .dtbo
> > and a composite .dtb (base DTB + overlay).
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-dsi-adv7535.dtso
> > @@ -0,0 +1,95 @@
> > +// SPDX-License-Identifier: GPL-2.0
> 
> Any chance this can be "(GPL-2.0-only OR BSD-2-Clause)", like all already existing
> arch/arm64/boot/dts/renesas/r9a08g046* files (and arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi)?

OK will fix.
> 
> 
> > +/*
> > + * Device Tree overlay for the RZ/G3L SMARC EVK with ADV7535
> > + * connected to DSI and LCDC enabled.
> > + *
> > + * Copyright (C) 2026 Renesas Electronics Corp.
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h>
> > +
> > +&{/} {
> > +       osc1: cec-clock {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               clock-frequency = <12000000>;
> > +       };
> > +
> > +       dsi-to-hdmi-out {
> > +               compatible = "hdmi-connector";
> > +               type = "d";
> 
> No ddc-i2c-bus?
> 
> > +
> > +               port {
> > +                       dsi_to_hdmi_con_out: endpoint {
> > +                               remote-endpoint = <&adv7535_out>;
> > +                       };
> > +               };
> > +       };
> > +};
> > +
> > +&dsi {
> > +       status = "okay";
> > +
> > +       ports {
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               port@1 {
> > +                       reg = <1>;
> > +                       dsi_out: endpoint {
> > +                               data-lanes = <1 2 3 4>;
> > +                               remote-endpoint = <&adv7535_in>;
> > +                       };
> > +               };
> > +       };
> > +};
> > +
> > +&du {
> > +       status = "okay";
> > +};
> > +
> > +&i2c2 {
> > +       #address-cells = <1>;
> > +       #size-cells = <0>;
> > +
> > +       adv7535: hdmi@3d {
> > +               compatible = "adi,adv7535";
> > +               reg = <0x3d>;
> > +
> > +               interrupts-extended = <&pinctrl RZG3L_GPIO(K, 3) IRQ_TYPE_EDGE_FALLING>;
> > +               clocks = <&osc1>;
> > +               clock-names = "cec";
> > +               avdd-supply = <&reg_1p8v>;
> > +               dvdd-supply = <&reg_1p8v>;
> > +               pvdd-supply = <&reg_1p8v>;
> > +               a2vdd-supply = <&reg_1p8v>;
> > +               v3p3-supply = <&reg_3p3v>;
> > +               v1p2-supply = <&reg_1p8v>;
> > +
> > +               adi,dsi-lanes = <4>;
> > +
> > +               ports {
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +
> > +                       port@0 {
> > +                               reg = <0>;
> > +                               adv7535_in: endpoint {
> > +                                       remote-endpoint = <&dsi_out>;
> > +                               };
> > +                       };
> > +
> > +                       port@1 {
> > +                               reg = <1>;
> > +                               adv7535_out: endpoint {
> > +                                       remote-endpoint = <&dsi_to_hdmi_con_out>;
> > +                               };
> > +                       };
> 
> No audio?

Ok, Will add HDMI audio support.

Cheers,
Biju

[PATCH v3 13/13] arm64: dts: renesas: Add LVDS overlay for RZ/G3L SMARC EVK with ITE6263

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add a Device Tree overlay (r9a08g046l48-smarc-lvds-ite6263.dtso) for the
RZ/G3L (R9A08G046) SMARC EVK board to support LVDS-to-HDMI output via the
ITE 6263 HDMI transmitter.

The overlay enables the LVDS controller and the display unit (DU/LCDC),
and configures the ITE6263 on I2C2.

Update the Makefile to build the overlay as both a standalone .dtbo and
a composite .dtb (base DTB + overlay).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * No change.
---
 arch/arm64/boot/dts/renesas/Makefile          |   3 +
 .../r9a08g046l48-smarc-lvds-ite6263.dtso      | 104 ++++++++++++++++++
 2 files changed, 107 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.dtso

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 8c6a44890715..3cecc40204e9 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -190,6 +190,9 @@ dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc.dtb
 dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc-dsi-adv7535.dtbo
 r9a08g046l48-smarc-dsi-adv7535-dtbs := r9a08g046l48-smarc.dtb r9a08g046l48-smarc-dsi-adv7535.dtbo
 dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc-dsi-adv7535.dtb
+dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc-lvds-ite6263.dtbo
+r9a08g046l48-smarc-lvds-ite6263-dtbs := r9a08g046l48-smarc.dtb r9a08g046l48-smarc-lvds-ite6263.dtbo
+dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc-lvds-ite6263.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
 
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.dtso b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.dtso
new file mode 100644
index 000000000000..95e1f411fa04
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.dtso
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree overlay for the RZ/G3L SMARC EVK with ITE6263
+ * connected to LVDS and LCDC enabled.
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h>
+
+&{/} {
+	lvds-to-hdmi-out {
+		compatible = "hdmi-connector";
+		type = "d";
+
+		port {
+			lvds_to_hdmi_con_out: endpoint {
+				remote-endpoint = <&it6263_out>;
+			};
+		};
+	};
+
+	reg_1v8: regulator-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3v3: regulator-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&du {
+	status = "okay";
+};
+
+&i2c2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	it6263: it6263@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+		data-mapping = "vesa-24";
+		ivdd-supply = <&reg_1v8>;
+		ovdd-supply = <&reg_3v3>;
+		txavcc18-supply = <&reg_1v8>;
+		txavcc33-supply = <&reg_3v3>;
+		pvcc1-supply = <&reg_1v8>;
+		pvcc2-supply = <&reg_1v8>;
+		avcc-supply = <&reg_3v3>;
+		anvdd-supply = <&reg_1v8>;
+		apvdd-supply = <&reg_1v8>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				bridge_in: endpoint {
+					remote-endpoint = <&lvds_out>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				it6263_out: endpoint {
+					remote-endpoint = <&lvds_to_hdmi_con_out>;
+				};
+			};
+		};
+	};
+};
+
+&lvds {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@1 {
+			reg = <1>;
+			lvds_out: endpoint {
+				remote-endpoint = <&bridge_in>;
+			};
+		};
+	};
+};
-- 
2.43.0

Re: [PATCH v3 13/13] arm64: dts: renesas: Add LVDS overlay for RZ/G3L SMARC EVK with ITE6263

[Geert Uytterhoeven]

Hi Biju,

On Wed, 26 Aug 2026 at 19:49, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add a Device Tree overlay (r9a08g046l48-smarc-lvds-ite6263.dtso) for the
> RZ/G3L (R9A08G046) SMARC EVK board to support LVDS-to-HDMI output via the
> ITE 6263 HDMI transmitter.
>
> The overlay enables the LVDS controller and the display unit (DU/LCDC),
> and configures the ITE6263 on I2C2.
>
> Update the Makefile to build the overlay as both a standalone .dtbo and
> a composite .dtb (base DTB + overlay).
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.dtso
> @@ -0,0 +1,104 @@
> +// SPDX-License-Identifier: GPL-2.0

Any chance this can be "(GPL-2.0-only OR BSD-2-Clause)", like all
already existing arch/arm64/boot/dts/renesas/r9a08g046* files?

> +/*
> + * Device Tree overlay for the RZ/G3L SMARC EVK with ITE6263
> + * connected to LVDS and LCDC enabled.
> + *
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h>
> +
> +&{/} {
> +       lvds-to-hdmi-out {
> +               compatible = "hdmi-connector";
> +               type = "d";
> +
> +               port {
> +                       lvds_to_hdmi_con_out: endpoint {
> +                               remote-endpoint = <&it6263_out>;
> +                       };
> +               };

No DDC?

> +       };
> +
> +       reg_1v8: regulator-1v8 {
> +               compatible = "regulator-fixed";
> +               regulator-name = "fixed-1.8V";
> +               regulator-min-microvolt = <1800000>;
> +               regulator-max-microvolt = <1800000>;
> +               regulator-boot-on;
> +               regulator-always-on;
> +       };
> +
> +       reg_3v3: regulator-3v3 {
> +               compatible = "regulator-fixed";
> +               regulator-name = "fixed-3.3V";
> +               regulator-min-microvolt = <3300000>;
> +               regulator-max-microvolt = <3300000>;
> +               regulator-boot-on;
> +               regulator-always-on;
> +       };

Any specific reason you cannot just reuse the existing &reg_1p8v
and &reg_3p3v?

> +};
> +
> +&du {
> +       status = "okay";
> +};
> +
> +&i2c2 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +
> +       it6263: it6263@4c {

hdmi@4c

> +               compatible = "ite,it6263";
> +               reg = <0x4c>;
> +               data-mapping = "vesa-24";
> +               ivdd-supply = <&reg_1v8>;
> +               ovdd-supply = <&reg_3v3>;
> +               txavcc18-supply = <&reg_1v8>;
> +               txavcc33-supply = <&reg_3v3>;
> +               pvcc1-supply = <&reg_1v8>;
> +               pvcc2-supply = <&reg_1v8>;
> +               avcc-supply = <&reg_3v3>;
> +               anvdd-supply = <&reg_1v8>;
> +               apvdd-supply = <&reg_1v8>;
> +
> +               ports {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       port@0 {
> +                               reg = <0>;
> +                               bridge_in: endpoint {
> +                                       remote-endpoint = <&lvds_out>;
> +                               };
> +                       };
> +
> +                       port@2 {
> +                               reg = <2>;
> +                               it6263_out: endpoint {
> +                                       remote-endpoint = <&lvds_to_hdmi_con_out>;
> +                               };
> +                       };
> +               };

No audio?

> +       };
> +};

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v3 13/13] arm64: dts: renesas: Add LVDS overlay for RZ/G3L SMARC EVK with ITE6263

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Subject: Re: [PATCH v3 13/13] arm64: dts: renesas: Add LVDS overlay for RZ/G3L SMARC EVK with ITE6263
> 
> Hi Biju,
> 
> On Wed, 26 Aug 2026 at 19:49, Biju <biju.das.au@gmail.com> wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add a Device Tree overlay (r9a08g046l48-smarc-lvds-ite6263.dtso) for
> > the RZ/G3L (R9A08G046) SMARC EVK board to support LVDS-to-HDMI output
> > via the ITE 6263 HDMI transmitter.
> >
> > The overlay enables the LVDS controller and the display unit
> > (DU/LCDC), and configures the ITE6263 on I2C2.
> >
> > Update the Makefile to build the overlay as both a standalone .dtbo
> > and a composite .dtb (base DTB + overlay).
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.dtso
> > @@ -0,0 +1,104 @@
> > +// SPDX-License-Identifier: GPL-2.0
> 
> Any chance this can be "(GPL-2.0-only OR BSD-2-Clause)", like all already existing
> arch/arm64/boot/dts/renesas/r9a08g046* files?

Ooops, will fix this.

> 
> > +/*
> > + * Device Tree overlay for the RZ/G3L SMARC EVK with ITE6263
> > + * connected to LVDS and LCDC enabled.
> > + *
> > + * Copyright (C) 2026 Renesas Electronics Corp.
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h>
> > +
> > +&{/} {
> > +       lvds-to-hdmi-out {
> > +               compatible = "hdmi-connector";
> > +               type = "d";
> > +
> > +               port {
> > +                       lvds_to_hdmi_con_out: endpoint {
> > +                               remote-endpoint = <&it6263_out>;
> > +                       };
> > +               };
> 
> No DDC?

The driver uses parent i2c bus as ddc-i2c-bus. That is the reason not added.


> 
> > +       };
> > +
> > +       reg_1v8: regulator-1v8 {
> > +               compatible = "regulator-fixed";
> > +               regulator-name = "fixed-1.8V";
> > +               regulator-min-microvolt = <1800000>;
> > +               regulator-max-microvolt = <1800000>;
> > +               regulator-boot-on;
> > +               regulator-always-on;
> > +       };
> > +
> > +       reg_3v3: regulator-3v3 {
> > +               compatible = "regulator-fixed";
> > +               regulator-name = "fixed-3.3V";
> > +               regulator-min-microvolt = <3300000>;
> > +               regulator-max-microvolt = <3300000>;
> > +               regulator-boot-on;
> > +               regulator-always-on;
> > +       };
> 
> Any specific reason you cannot just reuse the existing &reg_1p8v and &reg_3p3v?

Ok, will drop these.

> 
> > +};
> > +
> > +&du {
> > +       status = "okay";
> > +};
> > +
> > +&i2c2 {
> > +       #address-cells = <1>;
> > +       #size-cells = <0>;
> > +
> > +       it6263: it6263@4c {
> 
> hdmi@4c
Ok.

> 
> > +               compatible = "ite,it6263";
> > +               reg = <0x4c>;
> > +               data-mapping = "vesa-24";
> > +               ivdd-supply = <&reg_1v8>;
> > +               ovdd-supply = <&reg_3v3>;
> > +               txavcc18-supply = <&reg_1v8>;
> > +               txavcc33-supply = <&reg_3v3>;
> > +               pvcc1-supply = <&reg_1v8>;
> > +               pvcc2-supply = <&reg_1v8>;
> > +               avcc-supply = <&reg_3v3>;
> > +               anvdd-supply = <&reg_1v8>;
> > +               apvdd-supply = <&reg_1v8>;
> > +
> > +               ports {
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +
> > +                       port@0 {
> > +                               reg = <0>;
> > +                               bridge_in: endpoint {
> > +                                       remote-endpoint = <&lvds_out>;
> > +                               };
> > +                       };
> > +
> > +                       port@2 {
> > +                               reg = <2>;
> > +                               it6263_out: endpoint {
> > +                                       remote-endpoint = <&lvds_to_hdmi_con_out>;
> > +                               };
> > +                       };
> > +               };
> 
> No audio?

Binding describes audio port, but ITE6263 driver supports only video mode compared to
both Audio/Video support on ADV7535 driver.

I will add audio entries once we have driver support.
Hope it is ok for you?

Cheers,
Biju

> 
> > +       };
> > +};
> 
> The rest LGTM.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But when I'm talking to
> journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Re: [PATCH v3 13/13] arm64: dts: renesas: Add LVDS overlay for RZ/G3L SMARC EVK with ITE6263

[Geert Uytterhoeven]

Hi Biju,

On Wed, 9 Sept 2026 at 04:57, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > On Wed, 26 Aug 2026 at 19:49, Biju <biju.das.au@gmail.com> wrote:
> > > Add a Device Tree overlay (r9a08g046l48-smarc-lvds-ite6263.dtso) for
> > > the RZ/G3L (R9A08G046) SMARC EVK board to support LVDS-to-HDMI output
> > > via the ITE 6263 HDMI transmitter.
> > >
> > > The overlay enables the LVDS controller and the display unit
> > > (DU/LCDC), and configures the ITE6263 on I2C2.
> > >
> > > Update the Makefile to build the overlay as both a standalone .dtbo
> > > and a composite .dtb (base DTB + overlay).
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.dtso

> > > +&{/} {
> > > +       lvds-to-hdmi-out {
> > > +               compatible = "hdmi-connector";
> > > +               type = "d";
> > > +
> > > +               port {
> > > +                       lvds_to_hdmi_con_out: endpoint {
> > > +                               remote-endpoint = <&it6263_out>;
> > > +                       };
> > > +               };
> >
> > No DDC?
>
> The driver uses parent i2c bus as ddc-i2c-bus. That is the reason not added.

Neat trick. Do you know where that is handled? I couldn't find it.

> > > +       it6263: it6263@4c {
> >
> > hdmi@4c
> Ok.
>
> >
> > > +               compatible = "ite,it6263";
> > > +               reg = <0x4c>;
> > > +               data-mapping = "vesa-24";
> > > +               ivdd-supply = <&reg_1v8>;
> > > +               ovdd-supply = <&reg_3v3>;
> > > +               txavcc18-supply = <&reg_1v8>;
> > > +               txavcc33-supply = <&reg_3v3>;
> > > +               pvcc1-supply = <&reg_1v8>;
> > > +               pvcc2-supply = <&reg_1v8>;
> > > +               avcc-supply = <&reg_3v3>;
> > > +               anvdd-supply = <&reg_1v8>;
> > > +               apvdd-supply = <&reg_1v8>;
> > > +
> > > +               ports {
> > > +                       #address-cells = <1>;
> > > +                       #size-cells = <0>;
> > > +
> > > +                       port@0 {
> > > +                               reg = <0>;
> > > +                               bridge_in: endpoint {
> > > +                                       remote-endpoint = <&lvds_out>;
> > > +                               };
> > > +                       };
> > > +
> > > +                       port@2 {
> > > +                               reg = <2>;
> > > +                               it6263_out: endpoint {
> > > +                                       remote-endpoint = <&lvds_to_hdmi_con_out>;
> > > +                               };
> > > +                       };
> > > +               };
> >
> > No audio?
>
> Binding describes audio port, but ITE6263 driver supports only video mode compared to
> both Audio/Video support on ADV7535 driver.
>
> I will add audio entries once we have driver support.
> Hope it is ok for you?

That's fine, thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v3 13/13] arm64: dts: renesas: Add LVDS overlay for RZ/G3L SMARC EVK with ITE6263

[Biju Das]

Hi Geert,


> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 09 September 2026 08:44
> Subject: Re: [PATCH v3 13/13] arm64: dts: renesas: Add LVDS overlay for RZ/G3L SMARC EVK with ITE6263
> 
> Hi Biju,
> 
> On Wed, 9 Sept 2026 at 04:57, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Wed, 26 Aug 2026
> > > at 19:49, Biju <biju.das.au@gmail.com> wrote:
> > > > Add a Device Tree overlay (r9a08g046l48-smarc-lvds-ite6263.dtso)
> > > > for the RZ/G3L (R9A08G046) SMARC EVK board to support LVDS-to-HDMI
> > > > output via the ITE 6263 HDMI transmitter.
> > > >
> > > > The overlay enables the LVDS controller and the display unit
> > > > (DU/LCDC), and configures the ITE6263 on I2C2.
> > > >
> > > > Update the Makefile to build the overlay as both a standalone
> > > > .dtbo and a composite .dtb (base DTB + overlay).
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc-lvds-ite6263.
> > > > +++ dtso
> 
> > > > +&{/} {
> > > > +       lvds-to-hdmi-out {
> > > > +               compatible = "hdmi-connector";
> > > > +               type = "d";
> > > > +
> > > > +               port {
> > > > +                       lvds_to_hdmi_con_out: endpoint {
> > > > +                               remote-endpoint = <&it6263_out>;
> > > > +                       };
> > > > +               };
> > >
> > > No DDC?
> >
> > The driver uses parent i2c bus as ddc-i2c-bus. That is the reason not added.
> 
> Neat trick. Do you know where that is handled? I couldn't find it.

https://elixir.bootlin.com/linux/v7.3-rc1/source/drivers/gpu/drm/bridge/ite-it6263.c#L527

Cheers,
Biju