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From: Andy Shevchenko <andriy.shevchenko@intel.com>
To: Janani Sunil <janani.sunil@analog.com>
Cc: "Nuno Sá" <nuno.sa@analog.com>,
	"Michael Hennerich" <Michael.Hennerich@analog.com>,
	"Jonathan Cameron" <jic23@kernel.org>,
	"David Lechner" <dlechner@baylibre.com>,
	"Andy Shevchenko" <andy@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Olivier Moysan" <olivier.moysan@foss.st.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Linus Walleij" <linusw@kernel.org>,
	"Bartosz Golaszewski" <brgl@kernel.org>,
	"Jonathan Corbet" <corbet@lwn.net>,
	"Shuah Khan" <skhan@linuxfoundation.org>,
	"Michael Walle" <mwalle@kernel.org>,
	linux@analog.com, linux-iio@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org,
	jananisunil.dev@gmail.com,
	"Uwe Kleine-König" <u.kleine-koenig@baylibre.com>
Subject: Re: [PATCH v5 08/20] iio: adc: ad7768: Derive output data rates
Date: Mon, 31 Aug 2026 11:09:38 +0300	[thread overview]
Message-ID: <apU2wvlPtlZtxhPF@ashevche-desk.local> (raw)
In-Reply-To: <20260828-ad7768-driver-v5-8-e33ca6f841a2@analog.com>

On Fri, Aug 28, 2026 at 05:30:31PM +0200, Janani Sunil wrote:
> Derive valid output data rates from the master clock, power mode and
> decimation ratio.
> 
> Replace the fixed x64 decimation and open-coded DCLK divider in
> ad7768_configure_capture() with the derived default output rate and the
> new decimation and clock-divider helpers. Select the maximum rate
> supported by the configured data interface for the initial capture
> configuration.

...

> +static int ad7768_set_clk_divs(struct ad7768_state *st, unsigned int freq)
> +{
> +	const struct ad7768_freq_config *freq_cfg;
> +	unsigned int mclk, dclk, dclk_div;
> +	unsigned int chan_per_doutx;
> +	unsigned int dclk_div_reg;
> +
> +	freq_cfg = ad7768_find_freq_config(st, st->power_mode_idx, freq);
> +	if (!freq_cfg)
> +		return -EINVAL;
> +
> +	mclk = clk_get_rate(st->mclk);
> +	chan_per_doutx = st->chip_info->num_channels / st->datalines;
> +	if (!chan_per_doutx)
> +		return -EINVAL;
> +
> +	dclk = freq_cfg->freq_hz * AD7768_SAMPLE_SIZE * chan_per_doutx;
> +	if (!dclk || dclk > mclk)
> +		return -EINVAL;

SAMPLE_SIZE must not be 0, the chan_per_doutx is checked above, so this check
is about freq_hz, do we need it? If yes, make it better written

	freq_cfg = ad7768_find_freq_config(st, st->power_mode_idx, freq);
	if (!freq_cfg)
		return -EINVAL;
	// Do we really need this?
	if (!freq_cfg->freq_hz)
		return -EINVAL;
	...
	dclk = freq_cfg->freq_hz * AD7768_SAMPLE_SIZE * chan_per_doutx;
	if (dclk > mclk)
		return -EINVAL;

> +	/* Set the divider to the next-lowest supported power of two. */
> +	dclk_div = DIV_ROUND_CLOSEST(mclk, dclk);
> +	if (dclk_div > AD7768_MAX_DCLK_DIV)
> +		dclk_div = AD7768_MAX_DCLK_DIV;
> +	else
> +		dclk_div = rounddown_pow_of_two(dclk_div);

It's okay as is, but just to show that this can be shorten to

	dclk_div = DIV_ROUND_CLOSEST(mclk, dclk);

	/* Set the divider to the next-lowest supported power of two. */
	dclk_div = rounddown_pow_of_two(min(dclk_div, AD7768_MAX_DCLK_DIV));

> +	dclk_div_reg = AD7768_INTERFACE_CFG_DCLK_DIV(dclk_div);
> +
> +	return regmap_update_bits(st->regmap, AD7768_REG_INTERFACE_CFG,
> +				  AD7768_INTERFACE_CFG_DCLK_DIV_MSK,
> +				  FIELD_PREP(AD7768_INTERFACE_CFG_DCLK_DIV_MSK,
> +					     dclk_div_reg));
> +}

...

> +static void ad7768_set_available_sampling_freqs(struct ad7768_state *st)
> +{

	unsigned int n_power_modes = ARRAY_SIZE(ad7768_power_modes);

> +	unsigned int mclk = clk_get_rate(st->mclk);
> +
> +	for (unsigned int mode_idx = 0;
> +	     mode_idx < ARRAY_SIZE(ad7768_power_modes); mode_idx++) {

	for (unsigned int mode_idx = 0; mode_idx < n_power_modes); mode_idx++) {

> +		struct ad7768_avail_freq *avail_freq;
> +
> +		avail_freq = &st->avail_freq[mode_idx];

> +		for (unsigned int dec = ARRAY_SIZE(ad7768_dec_rate); dec > 0;
> +		     dec--) {

Leave this on a single line, it's okay to have it slightly bigger. However,
taking into account the below I would rather do it differently, id est

		unsigned int dec = ARRAY_SIZE(ad7768_dec_rate);
		struct ad7768_avail_freq *avail_freq;
		...
		while (dec--) {

> +			struct ad7768_freq_config *freq_cfg;
> +
> +			freq_cfg = &avail_freq->freq_cfg[avail_freq->n_freqs++];
> +			freq_cfg->dec_rate = dec - 1;

			freq_cfg->dec_rate = dec;

> +			freq_cfg->freq_hz = mclk /
> +				(ad7768_dec_rate[dec - 1] *
> +				 ad7768_power_modes[mode_idx].mclk_div);

This style is not good, better to take longer lines, but split on logical
boundaries. I also would go with a temporary variable

			// can be shortened to 'd' if you wish
			unsigned int div = ad7768_power_modes[mode_idx].mclk_div;
			...

			freq_cfg->freq_hz = mclk / (ad7768_dec_rate[dec] * div);
> +		}
> +	}
> +
> +	/* One DOUT line cannot carry the AD7768 fast-mode x32 output rate. */
> +	if (st->datalines == 1 &&
> +	    st->chip_info->num_channels == AD7768_MAX_CHANNEL)

> +		st->avail_freq[ARRAY_SIZE(ad7768_power_modes) - 1].n_freqs--;

		st->avail_freq[n_power_modes - 1].n_freqs--;

> +}

-- 
With Best Regards,
Andy Shevchenko



  reply	other threads:[~2026-08-31  8:09 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-28 15:30 [PATCH v5 00/20] iio: adc: Add AD7768/AD7768-4 ADC driver support Janani Sunil
2026-08-28 15:30 ` [PATCH v5 01/20] iio: adc: adi-axi-adc: Initialize state mutex Janani Sunil
2026-08-28 15:30 ` [PATCH v5 02/20] dt-bindings: iio: adc: Add AD7768 Janani Sunil
2026-08-28 15:30 ` [PATCH v5 03/20] iio: backend: Add support for CRC Janani Sunil
2026-08-28 15:30 ` [PATCH v5 04/20] iio: adc: adi-axi-adc: " Janani Sunil
2026-08-28 15:30 ` [PATCH v5 05/20] iio: adc: Add AD7768 and AD7768-4 core support Janani Sunil
2026-08-31  9:04   ` Andy Shevchenko
2026-08-31 15:20     ` Janani Sunil
2026-09-01  7:19       ` Andy Shevchenko
2026-08-28 15:30 ` [PATCH v5 06/20] iio: adc: ad7768: Validate master clock rate Janani Sunil
2026-08-28 15:30 ` [PATCH v5 07/20] iio: adc: ad7768: Add power mode helper Janani Sunil
2026-08-31  4:44   ` Andy Shevchenko
2026-08-28 15:30 ` [PATCH v5 08/20] iio: adc: ad7768: Derive output data rates Janani Sunil
2026-08-31  8:09   ` Andy Shevchenko [this message]
2026-08-28 15:30 ` [PATCH v5 09/20] iio: adc: ad7768: Configure channel sampling profiles Janani Sunil
2026-08-31  8:18   ` Andy Shevchenko
2026-08-28 15:30 ` [PATCH v5 10/20] iio: adc: ad7768: Add sampling frequency controls Janani Sunil
2026-08-31  8:24   ` Andy Shevchenko
2026-08-28 15:30 ` [PATCH v5 11/20] iio: adc: ad7768: Add per-channel filter controls Janani Sunil
2026-08-28 15:30 ` [PATCH v5 12/20] iio: adc: ad7768: Wait for digital filters to settle Janani Sunil
2026-08-31  7:45   ` Andy Shevchenko
2026-08-28 15:30 ` [PATCH v5 13/20] iio: adc: ad7768: Add calibration controls Janani Sunil
2026-08-31  8:26   ` Andy Shevchenko
2026-08-28 15:30 ` [PATCH v5 14/20] iio: adc: ad7768: Add per-channel conversion delay Janani Sunil
2026-08-31  8:30   ` Andy Shevchenko
2026-08-28 15:30 ` [PATCH v5 15/20] iio: adc: ad7768: Add VCM regulator support Janani Sunil
2026-08-28 15:30 ` [PATCH v5 16/20] iio: adc: ad7768: Register GPIO auxiliary device Janani Sunil
2026-08-31  8:33   ` Andy Shevchenko
2026-08-28 15:30 ` [PATCH v5 17/20] gpio: regmap: Use regmap_test_bits() for single bit reads Janani Sunil
2026-09-02 13:48   ` Bartosz Golaszewski
2026-08-28 15:30 ` [PATCH v5 18/20] gpio: regmap: Add optional runtime PM support Janani Sunil
2026-08-31  7:15   ` Andy Shevchenko
2026-08-28 15:30 ` [PATCH v5 19/20] gpio: ad7768: Add AD7768 GPIO auxiliary driver Janani Sunil
2026-08-28 15:30 ` [PATCH v5 20/20] Documentation: iio: Add AD7768 Documentation Janani Sunil
2026-08-29 18:19 ` [PATCH v5 00/20] iio: adc: Add AD7768/AD7768-4 ADC driver support Jonathan Cameron
2026-08-30  7:12   ` Andy Shevchenko
2026-09-01  8:32 ` Bartosz Golaszewski
2026-09-01 15:44   ` Jonathan Cameron

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