[PATCH v8 0/9] drm: renesas: rz-du: Add RZ/G3E support

[PATCH v8 0/9] drm: renesas: rz-du: Add RZ/G3E support

[Tommaso Merciai]

Dear All,

This patch series adds DU/DRM support for the 2 Display Units (DUs) interface
found on the Renesas RZ/G3E SoC.

RZ/G3E SoC has 2 LCD controller (LCDC0 and LCDC1), both are composed
of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD),
and Display Unit (DU).

LCDC0 is connected to LVDS (single or dual channel) and DSI.
LCDC1 is connected to LVDS (single ch), DSI, and GPIO (Parallel I/F).

The first patches prepare the driver for SoCs with more than one DU
channel: the registers, clocks and resets become per channel, and the
CRTCs are created from the channels_mask of the SoC information.
The RZ/G3E support and the DU node follow.

This series apply on top of RZ/G3L du support [1]

[1] https://lore.kernel.org/all/20260826174854.199139-1-biju.das.jz@bp.renesas.com/

Kind regards,
Tommaso

v7->v8:
 - Rebased on top of next-20260827 + [1].
 - Improved cover letter.
 - Modelled using ports/port instead of port/ep.
 - PATCH 01/9: Add RZ/G3E support on top of [1] using R-Car like architecture,
   improved commit msg and commit body.
 - PATCH 08/9: Use R-Car like architecture for RZ/G3E and added
   mode_clock_min, mode_clock_max for parallel output, improved commit msg
   and commit body.

v6->v7:
 - Rebased on top of next-20260605
 - Splitted the original series into smaller chunks for easy review and easy
   merging. The original series is available here:
   http://lore.kernel.org/all/cover.1775636898.git.tommaso.merciai.xr@bp.renesas.com/
 - PATCH 01/13: Collected LPinchart tag. Removed wrong fixes tag.
 - PATCH 02/13: Rebased on top of [1]. Use single DRM device aggregating
   both DU instances (1 DU dt node), modelling single port for each DU0,
   DU1 and multiple endpoints for outputs.
 - PATCH 12/13: Removed feature flag usage, rebased on top of T2H/N2H LCDC series [1]
   Reworked commit body as now outputs routing is based on endpoint id
   instead of port number. Fixed rzg2l_du_r9a09g047_info instead of
   rzg2l_du_r9a09g047_du_info.
   Added bump of RZG2L_DU_MAX_CRTCS and RZG2L_DU_MAX_VSPS to 2.

v5->v6:
 - Rebased on top of next-20260406
 - PATCH 1: Fixed rzv2h_cpg_plldsi_smux_clk_register() removed u8 width, mask
   variables and replaced with direct use of smux.width and clk_div_mask(smux.width).
 - PATCH 9: New patch.
 - PATCH 10: Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and
   explicitly disable port@2 and port@3 for existing SoCs that do not expose
   them. Reworked ports numbering + improved/fixed ports descriptions in the
   bindings documentation. Improved commit body.
 - PATCH 15: Aligned ports numbering with the bindings changes.
 - PATCH 20: Update ports numbering accordingly to the latest DT bindings.

v4->v5:
 - Rebased on top of next-20260211
 - PATCH 9: Dropped renesas,id property.
 - PATCH 10: Collected tag.
 - PATCH 14: Fixed RG2L_DU_FEATURE_SMUX2_DSI_CLK to RZG2L_DU_FEATURE_SMUX2_DSI_CLK
             Added features field documentation.
 - PATCH 19: Rename du0_out_dsi0 into du0_out_dsi.
             Rename du1_out_dsi0 into du1_out_dsi.
             Drop renesas,id entry from DU nodes.
 - PATCH 20: Use DU0 -> DSI instead of DU1 -> DSI.

v3->v4:
 - Rebased on top of next-20260130
 - PATCH 1: Fixed build error: https://lore.kernel.org/oe-kbuild-all/202601311423.gWtJuxiU-lkp@intel.com/

v2->v3:
 - PATCH 1: Added missing defines for duty num/den.

v1->v2:
 - Rebased on top of next-20260129.
 - PATCH 1: Added rzv2h_cpg_plldsi_smux_{get,set}_duty_cycle clock
   operations to allow the DRM driver to query and configure the
   appropriate clock path based on the required output duty cycle.
   Updated commit message accordingly.
 - PATCH 2-5: Collected tags.
 - PATCH 6: Moved clk_ids to match enum order.
 - PATCH 7: Collected GUytterhoeven tag. Fixed "dsi_0_vclk2" position
   to match order.
 - PATCH 8: Collected GUytterhoeven tag.
 - PATCH 9: Use single compatible string instead of multiple compatible
   strings for the two DU instances, leveraging a 'renesas,id' property
   to differentiate between DU0 and DU1. Updated commit message.
 - PATCH 10: Removed oneOf from clocks property, which is not sufficient
   to differentiate between RZ/G3E, RZ/V2H(P) and RZ/G2L. Use the already
   existing vclk instead of vclk1 for RZ/G3E DSI bindings. Updated allOf.
 - PATCH 14: Instead of using clk-provider API to select the right parent
   clock, just set the correct duty cycle based on the output. Updated
   commit message accordingly.
 - PATCH 15-16: Collected tags.
 - PATCH 17: Squashed fcpvd0 and fcpvd1 patches into a single patch.
   Collected tags.
 - PATCH 18: Squashed vspd0 and vspd1 patches into a single patch.
   Collected tags.
 - PATCH 19: Reworked DU nodes to use single compatible. Use vclk instead
   of vclk1 for DSI Node and set to the right position.
 - PATCH 20: Fixed: dsi, du and adv7535 are part of the R9A09G047E57
   SMARC SoM board then add entries in the rzg3e-smarc-som.dtsi instead
   of using the r9a09g047e57-smarc-du1-adv7535.dtsi.

Tommaso Merciai (9):
  dt-bindings: display: renesas,rzg2l-du: Document RZ/G3E SoC
  drm: renesas: rz-du: Move mmio from rzg2l_du_device to rzg2l_du_crtc
  drm: renesas: rz-du: crtc: Parameterize rzg2l_du_crtc_create()
  drm: renesas: rz-du: vsp: Keep the planes in the VSP
  drm: renesas: rz-du: kms: Enable multi CRTC creation
  drm: renesas: rz-du: crtc: Support per-channel named resources
  drm: renesas: rz-du: Rename possible_outputs to possible_crtcs
  drm: renesas: rz-du: Add RZ/G3E (R9A09G047) DU support
  arm64: dts: renesas: r9a09g047: Add DU node

 .../bindings/display/renesas,rzg2l-du.yaml    | 95 ++++++++++++++++++-
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 52 ++++++++++
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 88 ++++++++++++-----
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h |  5 +-
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c  | 50 +++++++---
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h  | 14 +--
 .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.c  |  3 +-
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c  | 18 +++-
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c  | 21 +---
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h  | 11 +--
 10 files changed, 279 insertions(+), 78 deletions(-)

-- 
2.54.0

[PATCH v8 1/9] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3E SoC

[Tommaso Merciai]

The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
Processor (VSPD), and Display Unit (DU).

 - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
 - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.

Add new SoC-specific compatible string 'renesas,r9a09g047-du'.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v7->v8:
 - Rebased on top of RZ/G3L du support [1]
 - Modelled using ports/port instead of port/ep.
   [1] https://lore.kernel.org/all/20260826174854.199139-1-biju.das.jz@bp.renesas.com/
 - Improved commit msg and commit body.

v6->v7:
 - Rebased on top of [1]
   [1] https://lore.kernel.org/all/20260429170012.366537-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
 - Use single DRM device aggregating both DU instances (1 DU dt node),
   modelling single port for each DU0, DU1 and multiple endpoints for
   outputs.

v5->v6:
 - Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and
   explicitly disable port@2 and port@3 for existing SoCs that do not expose
   them.
 - Reworked ports numbering + improved/fixed ports descriptions in the
   bindings documentation.
 - Improved commit body.

v4->v5:
 - Dropped renesas,id property and updated bindings
   accordingly.

v2->v3:
 - No changes.

v2->v3:
 - No changes.

v1->v2:
 - Use single compatible string instead of multiple compatible strings
   for the two DU instances, leveraging a 'renesas,id' property to
   differentiate between DU0 and DU1.
 - Updated commit message accordingly.

 .../bindings/display/renesas,rzg2l-du.yaml    | 95 ++++++++++++++++++-
 1 file changed, 91 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
index 5c9b15a09dee..d44c7c0add8d 100644
--- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
+++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
@@ -21,6 +21,7 @@ properties:
           - renesas,r9a07g043u-du # RZ/G2UL
           - renesas,r9a07g044-du # RZ/G2{L,LC}
           - renesas,r9a08g046-du # RZ/G3L
+          - renesas,r9a09g047-du # RZ/G3E
           - renesas,r9a09g057-du # RZ/V2H(P)
           - renesas,r9a09g077-du # RZ/T2H
       - items:
@@ -35,25 +36,51 @@ properties:
           - const: renesas,r9a09g077-du # RZ/T2H fallback
 
   reg:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: du.0
+      - const: du.1
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  interrupt-names:
+    items:
+      - const: du.0
+      - const: du.1
 
   clocks:
+    minItems: 3
     items:
       - description: Main clock
       - description: Register access clock
       - description: Video clock
+      - description: Main clock for DU1
+      - description: Register access clock for DU1
+      - description: Video clock for DU1
 
   clock-names:
+    minItems: 3
     items:
       - const: aclk
       - const: pclk
       - const: vclk
+      - const: aclk1
+      - const: pclk1
+      - const: vclk1
 
   resets:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  reset-names:
+    items:
+      - const: resetn
+      - const: resetn1
 
   power-domains:
     maxItems: 1
@@ -66,7 +93,7 @@ properties:
       model-dependent. Each port shall have a single endpoint.
 
     patternProperties:
-      "^port@[0-2]$":
+      "^port@[0-3]$":
         $ref: /schemas/graph.yaml#/properties/port
         unevaluatedProperties: false
 
@@ -110,6 +137,7 @@ allOf:
               description: DPI
             port@1: false
             port@2: false
+            port@3: false
 
           required:
             - port@0
@@ -127,6 +155,7 @@ allOf:
             port@1:
               description: DPI
             port@2: false
+            port@3: false
 
           required:
             - port@0
@@ -146,11 +175,68 @@ allOf:
               description: DPI
             port@2:
               description: LVDS
+            port@3: false
 
           required:
             - port@0
             - port@1
             - port@2
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g047-du
+    then:
+      properties:
+        reg:
+          minItems: 2
+        interrupts:
+          minItems: 2
+        clocks:
+          minItems: 6
+        clock-names:
+          minItems: 6
+        resets:
+          minItems: 2
+        renesas,vsps:
+          minItems: 2
+          maxItems: 2
+        ports:
+          properties:
+            port@0:
+              description: DSI
+            port@1:
+              description: DPI
+            port@2:
+              description: LVDS channel 0
+            port@3:
+              description: LVDS channel 1
+
+          required:
+            - port@0
+            - port@1
+            - port@2
+            - port@3
+
+      required:
+        - reg-names
+        - interrupt-names
+        - reset-names
+    else:
+      properties:
+        reg:
+          maxItems: 1
+        reg-names: false
+        interrupts:
+          maxItems: 1
+        interrupt-names: false
+        clocks:
+          maxItems: 3
+        clock-names:
+          maxItems: 3
+        resets:
+          maxItems: 1
+        reset-names: false
   - if:
       properties:
         compatible:
@@ -164,6 +250,7 @@ allOf:
               description: DSI
             port@1: false
             port@2: false
+            port@3: false
 
           required:
             - port@0
-- 
2.54.0

[PATCH v8 2/9] drm: renesas: rz-du: Move mmio from rzg2l_du_device to rzg2l_du_crtc

[Tommaso Merciai]

The DU registers are per display channel. On SoCs that integrate several
channels each of them has its own register window, so the base address
belongs to the CRTC rather than to the device.

Move the mmio pointer to struct rzg2l_du_crtc and map the registers from
rzg2l_du_crtc_create(). No functional change.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v7->v8:
 - No changes.

v6->v7:
 - New patch.

 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 25 ++++++++++++-------
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h |  2 ++
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c  |  5 ----
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h  |  2 --
 4 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
index d0f01aa642a7..3e82a0a2014a 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
@@ -67,7 +67,6 @@ static void rzg2l_du_crtc_set_display_timing(struct rzg2l_du_crtc *rcrtc)
 	const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
 	unsigned long mode_clock = mode->clock * 1000;
 	u32 ditr0, ditr1, ditr2, ditr3, ditr4, pbcr0;
-	struct rzg2l_du_device *rcdu = rcrtc->dev;
 
 	clk_prepare_enable(rcrtc->rzg2l_clocks.dclk);
 	clk_set_rate(rcrtc->rzg2l_clocks.dclk, mode_clock);
@@ -90,15 +89,15 @@ static void rzg2l_du_crtc_set_display_timing(struct rzg2l_du_crtc *rcrtc)
 
 	pbcr0 = DU_PBCR0_PB_DEP(0x1f);
 
-	writel(ditr0, rcdu->mmio + DU_DITR0);
-	writel(ditr1, rcdu->mmio + DU_DITR1);
-	writel(ditr2, rcdu->mmio + DU_DITR2);
-	writel(ditr3, rcdu->mmio + DU_DITR3);
-	writel(ditr4, rcdu->mmio + DU_DITR4);
-	writel(pbcr0, rcdu->mmio + DU_PBCR0);
+	writel(ditr0, rcrtc->mmio + DU_DITR0);
+	writel(ditr1, rcrtc->mmio + DU_DITR1);
+	writel(ditr2, rcrtc->mmio + DU_DITR2);
+	writel(ditr3, rcrtc->mmio + DU_DITR3);
+	writel(ditr4, rcrtc->mmio + DU_DITR4);
+	writel(pbcr0, rcrtc->mmio + DU_PBCR0);
 
 	/* Enable auto clear */
-	writel(DU_MCR1_PB_AUTOCLR, rcdu->mmio + DU_MCR1);
+	writel(DU_MCR1_PB_AUTOCLR, rcrtc->mmio + DU_MCR1);
 }
 
 /* -----------------------------------------------------------------------------
@@ -223,7 +222,7 @@ static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start)
 	if (start && rzg2l_du_has(rcdu, RZG2L_DU_FEATURE_DPIO_OE))
 		val |= DU_MCR0_DPI_EN;
 
-	writel(start ? val : 0, rcdu->mmio + DU_MCR0);
+	writel(start ? val : 0, rcrtc->mmio + DU_MCR0);
 }
 
 static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc)
@@ -380,11 +379,19 @@ static const struct drm_crtc_funcs crtc_funcs_rz = {
 
 int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu)
 {
+	struct platform_device *pdev = to_platform_device(rcdu->dev);
 	struct rzg2l_du_crtc *rcrtc = &rcdu->crtcs[0];
 	struct drm_crtc *crtc = &rcrtc->crtc;
 	struct drm_plane *primary;
 	int ret;
 
+	/* I/O resources */
+	rcrtc->mmio = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(rcrtc->mmio)) {
+		dev_err(rcdu->dev, "failed to map MMIO for DU\n");
+		return PTR_ERR(rcrtc->mmio);
+	}
+
 	rcrtc->rstc = devm_reset_control_get_optional_shared(rcdu->dev, NULL);
 	if (IS_ERR(rcrtc->rstc)) {
 		dev_err(rcdu->dev, "can't get cpg reset\n");
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h
index cbba38acc377..77ec92c4825d 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h
@@ -29,6 +29,7 @@ struct rzg2l_du_format_info;
  * struct rzg2l_du_crtc - the CRTC, representing a DU superposition processor
  * @crtc: base DRM CRTC
  * @dev: the DU device
+ * @mmio: base address of the DU registers of this CRTC
  * @initialized: whether the CRTC has been initialized and clocks enabled
  * @vblank_enable: whether vblank events are enabled on this CRTC
  * @event: event to post when the pending page flip completes
@@ -42,6 +43,7 @@ struct rzg2l_du_crtc {
 	struct drm_crtc crtc;
 
 	struct rzg2l_du_device *dev;
+	void __iomem *mmio;
 	bool initialized;
 
 	bool vblank_enable;
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
index 6c2dc86abc7d..3b868d4ef8bc 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
@@ -181,11 +181,6 @@ static int rzg2l_du_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, rcdu);
 
-	/* I/O resources */
-	rcdu->mmio = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(rcdu->mmio))
-		return PTR_ERR(rcdu->mmio);
-
 	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 	if (ret)
 		return ret;
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
index e9626ef37cde..3a649fd438e0 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
@@ -67,8 +67,6 @@ struct rzg2l_du_device {
 	struct device *dev;
 	const struct rzg2l_du_device_info *info;
 
-	void __iomem *mmio;
-
 	struct drm_device ddev;
 
 	struct rzg2l_du_crtc crtcs[RZG2L_DU_MAX_CRTCS];
-- 
2.54.0

[PATCH v8 3/9] drm: renesas: rz-du: crtc: Parameterize rzg2l_du_crtc_create()

[Tommaso Merciai]

In preparation for SoCs that integrate several DU channels, pass the
software and hardware channel indices to rzg2l_du_crtc_create().

The single caller is updated to pass zero for both indices, so there is
no functional change.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v7->v8
 - New patch.

 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 15 ++++++++-------
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h |  3 ++-
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c  |  2 +-
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
index 3e82a0a2014a..5aecf325e89b 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
@@ -377,10 +377,11 @@ static const struct drm_crtc_funcs crtc_funcs_rz = {
  * Initialization
  */
 
-int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu)
+int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu, unsigned int swindex,
+			 unsigned int hwindex)
 {
 	struct platform_device *pdev = to_platform_device(rcdu->dev);
-	struct rzg2l_du_crtc *rcrtc = &rcdu->crtcs[0];
+	struct rzg2l_du_crtc *rcrtc = &rcdu->crtcs[swindex];
 	struct drm_crtc *crtc = &rcrtc->crtc;
 	struct drm_plane *primary;
 	int ret;
@@ -388,31 +389,31 @@ int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu)
 	/* I/O resources */
 	rcrtc->mmio = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(rcrtc->mmio)) {
-		dev_err(rcdu->dev, "failed to map MMIO for DU\n");
+		dev_err(rcdu->dev, "failed to map MMIO for DU%u\n", hwindex);
 		return PTR_ERR(rcrtc->mmio);
 	}
 
 	rcrtc->rstc = devm_reset_control_get_optional_shared(rcdu->dev, NULL);
 	if (IS_ERR(rcrtc->rstc)) {
-		dev_err(rcdu->dev, "can't get cpg reset\n");
+		dev_err(rcdu->dev, "can't get cpg reset for DU%u\n", hwindex);
 		return PTR_ERR(rcrtc->rstc);
 	}
 
 	rcrtc->rzg2l_clocks.aclk = devm_clk_get(rcdu->dev, "aclk");
 	if (IS_ERR(rcrtc->rzg2l_clocks.aclk)) {
-		dev_err(rcdu->dev, "no axi clock for DU\n");
+		dev_err(rcdu->dev, "no axi clock for DU%u\n", hwindex);
 		return PTR_ERR(rcrtc->rzg2l_clocks.aclk);
 	}
 
 	rcrtc->rzg2l_clocks.pclk = devm_clk_get(rcdu->dev, "pclk");
 	if (IS_ERR(rcrtc->rzg2l_clocks.pclk)) {
-		dev_err(rcdu->dev, "no peripheral clock for DU\n");
+		dev_err(rcdu->dev, "no peripheral clock for DU%u\n", hwindex);
 		return PTR_ERR(rcrtc->rzg2l_clocks.pclk);
 	}
 
 	rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk");
 	if (IS_ERR(rcrtc->rzg2l_clocks.dclk)) {
-		dev_err(rcdu->dev, "no video clock for DU\n");
+		dev_err(rcdu->dev, "no video clock for DU%u\n", hwindex);
 		return PTR_ERR(rcrtc->rzg2l_clocks.dclk);
 	}
 
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h
index 77ec92c4825d..0fa8c4369851 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h
@@ -84,7 +84,8 @@ static inline struct rzg2l_du_crtc_state *to_rzg2l_crtc_state(struct drm_crtc_st
 	return container_of(s, struct rzg2l_du_crtc_state, state);
 }
 
-int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu);
+int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu, unsigned int swindex,
+			 unsigned int hwindex);
 
 void rzg2l_du_crtc_finish_page_flip(struct rzg2l_du_crtc *rcrtc);
 
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
index 87f171145a23..7cbdf146788e 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
@@ -440,7 +440,7 @@ int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu)
 		return ret;
 
 	/* Create the CRTCs. */
-	ret = rzg2l_du_crtc_create(rcdu);
+	ret = rzg2l_du_crtc_create(rcdu, 0, 0);
 	if (ret < 0)
 		return ret;
 
-- 
2.54.0

[PATCH v8 4/9] drm: renesas: rz-du: vsp: Keep the planes in the VSP

[Tommaso Merciai]

Each VSP numbers its planes from zero, so the device-wide search in
rzg2l_du_vsp_get_drm_plane() picks the wrong plane as soon as a SoC has
more than one VSP: the primary plane of the second CRTC is looked up on
the first VSP, whose possible_crtcs mask does not cover that CRTC.

In preparation of supporting RZ/G3E, store the planes in the VSP that
owns them and index the per-VSP array directly from
rzg2l_du_crtc_create(). Validate the pipe index read from the device
tree, and drop the now unused search helper.

No functional change intended.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v7->v8
 - New patch.

 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 10 ++++++---
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c  | 21 ++++---------------
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h  | 11 ++++------
 3 files changed, 15 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
index 5aecf325e89b..81934fcb551b 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
@@ -420,9 +420,13 @@ int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu, unsigned int swindex,
 	init_waitqueue_head(&rcrtc->flip_wait);
 	rcrtc->dev = rcdu;
 
-	primary = rzg2l_du_vsp_get_drm_plane(rcrtc, rcrtc->vsp_pipe);
-	if (IS_ERR(primary))
-		return PTR_ERR(primary);
+	if (rcrtc->vsp_pipe >= rcrtc->vsp->num_planes) {
+		dev_err(rcdu->dev, "invalid VSP pipe %u for DU%u\n",
+			rcrtc->vsp_pipe, hwindex);
+		return -EINVAL;
+	}
+
+	primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe]->plane;
 
 	ret = drmm_crtc_init_with_planes(&rcdu->ddev, crtc, primary, NULL,
 					 &crtc_funcs_rz, NULL);
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c
index 1efa0f0451fe..b0565b88d841 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c
@@ -71,22 +71,6 @@ void rzg2l_du_vsp_atomic_flush(struct rzg2l_du_crtc *crtc)
 	vsp1_du_atomic_flush(crtc->vsp->vsp, crtc->vsp_pipe, &cfg);
 }
 
-struct drm_plane *rzg2l_du_vsp_get_drm_plane(struct rzg2l_du_crtc *crtc,
-					     unsigned int pipe_index)
-{
-	struct rzg2l_du_device *rcdu = crtc->vsp->dev;
-	struct drm_plane *plane = NULL;
-
-	drm_for_each_plane(plane, &rcdu->ddev) {
-		struct rzg2l_du_vsp_plane *vsp_plane = to_rzg2l_vsp_plane(plane);
-
-		if (vsp_plane->index == pipe_index)
-			break;
-	}
-
-	return plane ? plane : ERR_PTR(-EINVAL);
-}
-
 static const u32 rzg2l_du_vsp_formats[] = {
 	DRM_FORMAT_RGB332,
 	DRM_FORMAT_ARGB4444,
@@ -306,7 +290,7 @@ int rzg2l_du_vsp_init(struct rzg2l_du_vsp *vsp, struct device_node *np,
 	struct rzg2l_du_device *rcdu = vsp->dev;
 	struct platform_device *pdev;
 	unsigned int num_crtcs = hweight32(crtcs);
-	unsigned int num_planes = 2;
+	unsigned int num_planes = RZG2L_DU_VSP_MAX_PLANES;
 	unsigned int i;
 	int ret;
 
@@ -353,6 +337,7 @@ int rzg2l_du_vsp_init(struct rzg2l_du_vsp *vsp, struct device_node *np,
 
 		plane->vsp = vsp;
 		plane->index = i;
+		vsp->planes[i] = plane;
 
 		drm_plane_helper_add(&plane->plane,
 				     &rzg2l_du_vsp_plane_helper_funcs);
@@ -365,6 +350,8 @@ int rzg2l_du_vsp_init(struct rzg2l_du_vsp *vsp, struct device_node *np,
 					BIT(DRM_MODE_BLEND_PIXEL_NONE) |
 					BIT(DRM_MODE_BLEND_PREMULTI) |
 					BIT(DRM_MODE_BLEND_COVERAGE));
+
+		vsp->num_planes++;
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h
index a22aaf0843ed..63f6e508264d 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h
@@ -27,11 +27,15 @@ struct rzg2l_du_vsp_plane {
 	unsigned int index;
 };
 
+#define RZG2L_DU_VSP_MAX_PLANES		2
+
 struct rzg2l_du_vsp {
 	unsigned int index;
 	struct device *vsp;
 	struct device_link *link;
 	struct rzg2l_du_device *dev;
+	struct rzg2l_du_vsp_plane *planes[RZG2L_DU_VSP_MAX_PLANES];
+	unsigned int num_planes;
 };
 
 static inline struct rzg2l_du_vsp_plane *to_rzg2l_vsp_plane(struct drm_plane *p)
@@ -62,8 +66,6 @@ int rzg2l_du_vsp_init(struct rzg2l_du_vsp *vsp, struct device_node *np,
 void rzg2l_du_vsp_enable(struct rzg2l_du_crtc *crtc);
 void rzg2l_du_vsp_disable(struct rzg2l_du_crtc *crtc);
 void rzg2l_du_vsp_atomic_flush(struct rzg2l_du_crtc *crtc);
-struct drm_plane *rzg2l_du_vsp_get_drm_plane(struct rzg2l_du_crtc *crtc,
-					     unsigned int pipe_index);
 #else
 static inline int rzg2l_du_vsp_init(struct rzg2l_du_vsp *vsp, struct device_node *np,
 				    unsigned int crtcs)
@@ -74,11 +76,6 @@ static inline int rzg2l_du_vsp_init(struct rzg2l_du_vsp *vsp, struct device_node
 static inline void rzg2l_du_vsp_enable(struct rzg2l_du_crtc *crtc) { };
 static inline void rzg2l_du_vsp_disable(struct rzg2l_du_crtc *crtc) { };
 static inline void rzg2l_du_vsp_atomic_flush(struct rzg2l_du_crtc *crtc) { };
-static inline struct drm_plane *rzg2l_du_vsp_get_drm_plane(struct rzg2l_du_crtc *crtc,
-							   unsigned int pipe_index)
-{
-	return ERR_PTR(-ENXIO);
-}
 #endif
 
 #endif /* __RZG2L_DU_VSP_H__ */
-- 
2.54.0

[PATCH v8 5/9] drm: renesas: rz-du: kms: Enable multi CRTC creation

[Tommaso Merciai]

Raise the CRTC and VSP limits to two and create one CRTC per bit set in
the channels_mask of the SoC information, mapping the software CRTC
index to the hardware channel index.

All currently supported SoCs have a single DU channel, so there is no
functional change for them.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v7->v8
 - New patch.

 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h |  4 ++--
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 14 +++++++++++---
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
index 3a649fd438e0..cb9ad869d66b 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
@@ -59,8 +59,8 @@ struct rzg2l_du_device_info {
 	unsigned int features;
 };
 
-#define RZG2L_DU_MAX_CRTCS		1
-#define RZG2L_DU_MAX_VSPS		1
+#define RZG2L_DU_MAX_CRTCS		2
+#define RZG2L_DU_MAX_VSPS		2
 #define RZG2L_DU_MAX_DSI		1
 
 struct rzg2l_du_device {
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
index 7cbdf146788e..04f51b9d1dd8 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
@@ -405,6 +405,8 @@ int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu)
 	struct drm_device *dev = &rcdu->ddev;
 	struct drm_encoder *encoder;
 	unsigned int num_encoders;
+	unsigned int swindex;
+	unsigned int hwindex;
 	int ret;
 
 	ret = drmm_mode_config_init(dev);
@@ -440,9 +442,15 @@ int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu)
 		return ret;
 
 	/* Create the CRTCs. */
-	ret = rzg2l_du_crtc_create(rcdu, 0, 0);
-	if (ret < 0)
-		return ret;
+	for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) {
+		/* Skip unpopulated DU channels. */
+		if (!(rcdu->info->channels_mask & BIT(hwindex)))
+			continue;
+
+		ret = rzg2l_du_crtc_create(rcdu, swindex++, hwindex);
+		if (ret < 0)
+			return ret;
+	}
 
 	/* Initialize the encoders. */
 	ret = rzg2l_du_encoders_init(rcdu);
-- 
2.54.0

[PATCH v8 6/9] drm: renesas: rz-du: crtc: Support per-channel named resources

[Tommaso Merciai]

SoCs that integrate several DU channels describe the registers, clocks
and resets of each channel separately, and name them after the channel
they belong to. Introduce a table of resource names indexed by hardware
channel index, selected by the new RZG2L_DU_FEATURE_CHANNEL_RES feature
flag, and keep looking the resources up unnamed and unindexed for the
single-channel SoCs.

No functional change for the currently supported SoCs.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v7->v8
 - New patch.

 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 42 ++++++++++++++++---
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h  |  1 +
 2 files changed, 38 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
index 81934fcb551b..dea6d92a7a8a 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
@@ -377,41 +377,73 @@ static const struct drm_crtc_funcs crtc_funcs_rz = {
  * Initialization
  */
 
+/*
+ * struct rzg2l_du_channel_res - Names of the resources of a DU channel
+ * @reg: reg-names entry holding the channel registers, NULL if unnamed
+ * @aclk: name of the channel main clock
+ * @pclk: name of the channel register access clock
+ * @vclk: name of the channel video clock
+ * @rst: reset-names entry of the channel reset, NULL if unnamed
+ */
+struct rzg2l_du_channel_res {
+	const char *reg;
+	const char *aclk;
+	const char *pclk;
+	const char *vclk;
+	const char *rst;
+};
+
 int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu, unsigned int swindex,
 			 unsigned int hwindex)
 {
+	static const struct rzg2l_du_channel_res channel_res[] = {
+		[0] = { "du.0", "aclk", "pclk", "vclk", "resetn" },
+		[1] = { "du.1", "aclk1", "pclk1", "vclk1", "resetn1" },
+	};
+	static const struct rzg2l_du_channel_res single_channel_res = {
+		NULL, "aclk", "pclk", "vclk", NULL,
+	};
+
+	static_assert(ARRAY_SIZE(channel_res) == RZG2L_DU_MAX_CRTCS);
+
 	struct platform_device *pdev = to_platform_device(rcdu->dev);
 	struct rzg2l_du_crtc *rcrtc = &rcdu->crtcs[swindex];
+	const struct rzg2l_du_channel_res *res;
 	struct drm_crtc *crtc = &rcrtc->crtc;
 	struct drm_plane *primary;
 	int ret;
 
+	res = rzg2l_du_has(rcdu, RZG2L_DU_FEATURE_CHANNEL_RES)
+	    ? &channel_res[hwindex] : &single_channel_res;
+
 	/* I/O resources */
-	rcrtc->mmio = devm_platform_ioremap_resource(pdev, 0);
+	rcrtc->mmio = res->reg
+		    ? devm_platform_ioremap_resource_byname(pdev, res->reg)
+		    : devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(rcrtc->mmio)) {
 		dev_err(rcdu->dev, "failed to map MMIO for DU%u\n", hwindex);
 		return PTR_ERR(rcrtc->mmio);
 	}
 
-	rcrtc->rstc = devm_reset_control_get_optional_shared(rcdu->dev, NULL);
+	rcrtc->rstc = devm_reset_control_get_optional_shared(rcdu->dev, res->rst);
 	if (IS_ERR(rcrtc->rstc)) {
 		dev_err(rcdu->dev, "can't get cpg reset for DU%u\n", hwindex);
 		return PTR_ERR(rcrtc->rstc);
 	}
 
-	rcrtc->rzg2l_clocks.aclk = devm_clk_get(rcdu->dev, "aclk");
+	rcrtc->rzg2l_clocks.aclk = devm_clk_get(rcdu->dev, res->aclk);
 	if (IS_ERR(rcrtc->rzg2l_clocks.aclk)) {
 		dev_err(rcdu->dev, "no axi clock for DU%u\n", hwindex);
 		return PTR_ERR(rcrtc->rzg2l_clocks.aclk);
 	}
 
-	rcrtc->rzg2l_clocks.pclk = devm_clk_get(rcdu->dev, "pclk");
+	rcrtc->rzg2l_clocks.pclk = devm_clk_get(rcdu->dev, res->pclk);
 	if (IS_ERR(rcrtc->rzg2l_clocks.pclk)) {
 		dev_err(rcdu->dev, "no peripheral clock for DU%u\n", hwindex);
 		return PTR_ERR(rcrtc->rzg2l_clocks.pclk);
 	}
 
-	rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk");
+	rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, res->vclk);
 	if (IS_ERR(rcrtc->rzg2l_clocks.dclk)) {
 		dev_err(rcdu->dev, "no video clock for DU%u\n", hwindex);
 		return PTR_ERR(rcrtc->rzg2l_clocks.dclk);
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
index cb9ad869d66b..6e1e4222d2f4 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
@@ -21,6 +21,7 @@ struct device;
 struct drm_property;
 
 #define RZG2L_DU_FEATURE_DPIO_OE	BIT(0)	/* Has DPIO output enable control */
+#define RZG2L_DU_FEATURE_CHANNEL_RES	BIT(1)	/* Per-channel named reg, clocks and resets */
 
 enum rzg2l_du_output {
 	RZG2L_DU_OUTPUT_DSI0,
-- 
2.54.0

[PATCH v8 7/9] drm: renesas: rz-du: Rename possible_outputs to possible_crtcs

[Tommaso Merciai]

The field holds the mask of the CRTCs that can drive the output, and is
assigned as-is to drm_encoder.possible_crtcs. Its name says the opposite
of what it contains. Rename it to possible_crtcs, matching the R-Car DU
field it was derived from.

No functional change.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v7->v8
 - New patch.

 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 16 ++++++++--------
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h |  4 ++--
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c |  4 ++--
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
index 3b868d4ef8bc..0c08701b1502 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
@@ -31,7 +31,7 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = {
 	.channels_mask = BIT(0),
 	.routes = {
 		[RZG2L_DU_OUTPUT_DPAD0] = {
-			.possible_outputs = BIT(0),
+			.possible_crtcs = BIT(0),
 			.port = 0,
 		},
 	},
@@ -43,11 +43,11 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
 	.channels_mask = BIT(0),
 	.routes = {
 		[RZG2L_DU_OUTPUT_DSI0] = {
-			.possible_outputs = BIT(0),
+			.possible_crtcs = BIT(0),
 			.port = 0,
 		},
 		[RZG2L_DU_OUTPUT_DPAD0] = {
-			.possible_outputs = BIT(0),
+			.possible_crtcs = BIT(0),
 			.port = 1,
 		}
 	},
@@ -59,15 +59,15 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a08g046_info = {
 	.channels_mask = BIT(0),
 	.routes = {
 		[RZG2L_DU_OUTPUT_DSI0] = {
-			.possible_outputs = BIT(0),
+			.possible_crtcs = BIT(0),
 			.port = 0,
 		},
 		[RZG2L_DU_OUTPUT_DPAD0] = {
-			.possible_outputs = BIT(0),
+			.possible_crtcs = BIT(0),
 			.port = 1,
 		},
 		[RZG2L_DU_OUTPUT_LVDS0] = {
-			.possible_outputs = BIT(0),
+			.possible_crtcs = BIT(0),
 			.port = 2,
 		},
 	},
@@ -79,7 +79,7 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = {
 	.channels_mask = BIT(0),
 	.routes = {
 		[RZG2L_DU_OUTPUT_DSI0] = {
-			.possible_outputs = BIT(0),
+			.possible_crtcs = BIT(0),
 			.port = 0,
 		},
 	},
@@ -89,7 +89,7 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a09g077_info = {
 	.channels_mask = BIT(0),
 	.routes = {
 		[RZG2L_DU_OUTPUT_DPAD0] = {
-			.possible_outputs = BIT(0),
+			.possible_crtcs = BIT(0),
 			.port = 0,
 		},
 	},
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
index 6e1e4222d2f4..66ebcbaf0687 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
@@ -32,7 +32,7 @@ enum rzg2l_du_output {
 
 /*
  * struct rzg2l_du_output_routing - Output routing specification
- * @possible_outputs: bitmask of possible outputs
+ * @possible_crtcs: bitmask of possible CRTCs for the output
  * @port: device tree port number corresponding to this output route
  *
  * The DU has 3 possible outputs (DPAD0, DSI0, LVDS0). Output routing data
@@ -40,7 +40,7 @@ enum rzg2l_du_output {
  * of in-SoC encoder for the output.
  */
 struct rzg2l_du_output_routing {
-	unsigned int possible_outputs;
+	unsigned int possible_crtcs;
 	unsigned int port;
 };
 
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
index 04f51b9d1dd8..21e34d99b12d 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
@@ -290,7 +290,7 @@ static int rzg2l_du_encoders_init(struct rzg2l_du_device *rcdu)
 
 		/* Find the output route corresponding to the port number. */
 		for (i = 0; i < RZG2L_DU_OUTPUT_MAX; ++i) {
-			if (rcdu->info->routes[i].possible_outputs &&
+			if (rcdu->info->routes[i].possible_crtcs &&
 			    rcdu->info->routes[i].port == ep.port) {
 				output = i;
 				break;
@@ -475,7 +475,7 @@ int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu)
 		const struct rzg2l_du_output_routing *route =
 			&rcdu->info->routes[renc->output];
 
-		encoder->possible_crtcs = route->possible_outputs;
+		encoder->possible_crtcs = route->possible_crtcs;
 		encoder->possible_clones = (1 << num_encoders) - 1;
 	}
 
-- 
2.54.0

[PATCH v8 8/9] drm: renesas: rz-du: Add RZ/G3E (R9A09G047) DU support

[Tommaso Merciai]

Add Display Unit driver support for the Renesas RZ/G3E SoC (R9A09G047).
Unlike the other SoCs, it has two DU channels: channel 0 drives the
LVDS encoder in single or dual channel mode and the DSI encoder, while
channel 1 drives the LVDS encoder in single channel mode, the DSI
encoder and the parallel interface.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v7->v8
 - Modelled using ports/port instead of port/ep.
 - Rebased on top of RZ/G3L du support [1]
   [1] https://lore.kernel.org/all/20260826174854.199139-1-biju.das.jz@bp.renesas.com/
 - Added mode_clock_min, mode_clock_max for parallel output.
 - Improved commit msg and commit body.

v6->v7:
 - Removed feature flag usage, rebased on top of T2H/N2H LCDC series [1]
   [1] https://patchwork.global.renesas.com/project/spl2-reviews/list/?series=694&state=%2A&archive=both
 - Reworked commit body as now outputs routing is based on endpoint id
   instead of port number.
 - Fixed rzg2l_du_r9a09g047_info instead of rzg2l_du_r9a09g047_du_info.
 - Added bump of RZG2L_DU_MAX_CRTCS and RZG2L_DU_MAX_VSPS to 2.

v5->v6:
 - Aligned ports numbering with the bindings changes.

v4->v5:
 - Fixed RG2L_DU_FEATURE_SMUX2_DSI_CLK to RZG2L_DU_FEATURE_SMUX2_DSI_CLK,
   update commit body accordingly.
 - Added features field documentation.

v3->v4:
 - No changes.

v2->v3:
 - No changes.

v1->v2:
 - Instead of using clk-provider API to select the right parent clock,
   based on the outputs. Just set the correct duty cycle based on the
   output, this reflects at CPG lvl to select the right parent.
 - Updated commit message accordingly.

 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c  | 29 ++++++++++++++++++-
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h  |  3 +-
 .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.c  |  3 +-
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
index 0c08701b1502..8143929ed401 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
@@ -75,6 +75,31 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a08g046_info = {
 	.mode_clock_max = 87000,
 };
 
+static const struct rzg2l_du_device_info rzg2l_du_r9a09g047_info = {
+	.features = RZG2L_DU_FEATURE_CHANNEL_RES,
+	.channels_mask = BIT(0) | BIT(1),
+	.routes = {
+		[RZG2L_DU_OUTPUT_DSI0] = {
+			.possible_crtcs = BIT(0) | BIT(1),
+			.port = 0,
+		},
+		[RZG2L_DU_OUTPUT_DPAD0] = {
+			.possible_crtcs = BIT(1),
+			.port = 1,
+		},
+		[RZG2L_DU_OUTPUT_LVDS0] = {
+			.possible_crtcs = BIT(0),
+			.port = 2,
+		},
+		[RZG2L_DU_OUTPUT_LVDS1] = {
+			.possible_crtcs = BIT(0) | BIT(1),
+			.port = 3,
+		},
+	},
+	.mode_clock_min = 5400,
+	.mode_clock_max = 87000,
+};
+
 static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = {
 	.channels_mask = BIT(0),
 	.routes = {
@@ -102,6 +127,7 @@ static const struct of_device_id rzg2l_du_of_table[] = {
 	{ .compatible = "renesas,r9a07g043u-du", .data = &rzg2l_du_r9a07g043u_info },
 	{ .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info },
 	{ .compatible = "renesas,r9a08g046-du", .data = &rzg2l_du_r9a08g046_info },
+	{ .compatible = "renesas,r9a09g047-du", .data = &rzg2l_du_r9a09g047_info },
 	{ .compatible = "renesas,r9a09g057-du", .data = &rzg2l_du_r9a09g057_info },
 	{ .compatible = "renesas,r9a09g077-du", .data = &rzg2l_du_r9a09g077_info },
 	{ /* sentinel */ }
@@ -114,7 +140,8 @@ const char *rzg2l_du_output_name(enum rzg2l_du_output output)
 	static const char * const names[] = {
 		[RZG2L_DU_OUTPUT_DSI0] = "DSI0",
 		[RZG2L_DU_OUTPUT_DPAD0] = "DPAD0",
-		[RZG2L_DU_OUTPUT_LVDS0] = "LVDS0"
+		[RZG2L_DU_OUTPUT_LVDS0] = "LVDS0",
+		[RZG2L_DU_OUTPUT_LVDS1] = "LVDS1",
 	};
 
 	if (output >= ARRAY_SIZE(names))
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
index 66ebcbaf0687..326293cf9787 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
@@ -27,6 +27,7 @@ enum rzg2l_du_output {
 	RZG2L_DU_OUTPUT_DSI0,
 	RZG2L_DU_OUTPUT_DPAD0,
 	RZG2L_DU_OUTPUT_LVDS0,
+	RZG2L_DU_OUTPUT_LVDS1,
 	RZG2L_DU_OUTPUT_MAX,
 };
 
@@ -35,7 +36,7 @@ enum rzg2l_du_output {
  * @possible_crtcs: bitmask of possible CRTCs for the output
  * @port: device tree port number corresponding to this output route
  *
- * The DU has 3 possible outputs (DPAD0, DSI0, LVDS0). Output routing data
+ * The DU has 4 possible outputs (DPAD0, DSI0, LVDS0/1). Output routing data
  * specify the valid SoC outputs, which CRTC can drive the output, and the type
  * of in-SoC encoder for the output.
  */
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
index a1b48973aa8e..ff3e70227d2a 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
@@ -81,7 +81,8 @@ static void rzg2l_du_encoder_atomic_mode_set(struct drm_encoder *encoder,
 	 * - LVDS path has DUTY H/L=4/3, 4/7 duty cycle.
 	 * - DSI/RGB path has symmetric 50% duty cycle.
 	 */
-	if (renc->output == RZG2L_DU_OUTPUT_LVDS0)
+	if (renc->output == RZG2L_DU_OUTPUT_LVDS0 ||
+	    renc->output == RZG2L_DU_OUTPUT_LVDS1)
 		clk_set_duty_cycle(clk_parent, 4, 7);
 	else
 		clk_set_duty_cycle(clk_parent, 1, 2);
-- 
2.54.0

[PATCH v8 9/9] arm64: dts: renesas: r9a09g047: Add DU node

[Tommaso Merciai]

Add DU node to RZ/G3E SoC DTSI.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
v7->v8
 - New patch.

 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 52 ++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 73757e8e2197..4f95b0d7e8ab 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -2105,6 +2105,58 @@ csi2cru: endpoint@0 {
 			};
 		};
 
+		du: display@16460000 {
+			compatible = "renesas,r9a09g047-du";
+			reg = <0 0x16460000 0 0x10000>,
+			      <0 0x16490000 0 0x10000>;
+			reg-names = "du.0", "du.1";
+			interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "du.0", "du.1";
+			clocks = <&cpg CPG_MOD 0xed>,
+				 <&cpg CPG_MOD 0xee>,
+				 <&cpg CPG_MOD 0xef>,
+				 <&cpg CPG_MOD 0x1a8>,
+				 <&cpg CPG_MOD 0x1a9>,
+				 <&cpg CPG_MOD 0x1aa>;
+			clock-names = "aclk", "pclk", "vclk",
+				      "aclk1", "pclk1", "vclk1";
+			resets = <&cpg 0xdc>, <&cpg 0x11e>;
+			reset-names = "resetn", "resetn1";
+			power-domains = <&cpg>;
+			renesas,vsps = <&vspd0 0>, <&vspd1 0>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					du_out_dsi: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					du_out_rgb: endpoint {
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					du_out_lvds0: endpoint {
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+					du_out_lvds1: endpoint {
+					};
+				};
+			};
+		};
+
 		fcpvd0: fcp@16470000 {
 			compatible = "renesas,r9a09g047-fcpvd",
 				     "renesas,fcpv";
-- 
2.54.0

Re: [PATCH v8 1/9] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3E SoC

[Krzysztof Kozlowski]

On Fri, Aug 28, 2026 at 02:21:04PM +0200, Tommaso Merciai wrote:
> The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> Processor (VSPD), and Display Unit (DU).
> 
>  - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
>  - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> 
> Add new SoC-specific compatible string 'renesas,r9a09g047-du'.
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
> v7->v8:
>  - Rebased on top of RZ/G3L du support [1]
>  - Modelled using ports/port instead of port/ep.
>    [1] https://lore.kernel.org/all/20260826174854.199139-1-biju.das.jz@bp.renesas.com/
>  - Improved commit msg and commit body.
> 
> v6->v7:
>  - Rebased on top of [1]
>    [1] https://lore.kernel.org/all/20260429170012.366537-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>  - Use single DRM device aggregating both DU instances (1 DU dt node),
>    modelling single port for each DU0, DU1 and multiple endpoints for
>    outputs.
> 
> v5->v6:
>  - Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and
>    explicitly disable port@2 and port@3 for existing SoCs that do not expose
>    them.
>  - Reworked ports numbering + improved/fixed ports descriptions in the
>    bindings documentation.
>  - Improved commit body.
> 
> v4->v5:
>  - Dropped renesas,id property and updated bindings
>    accordingly.
> 
> v2->v3:
>  - No changes.
> 
> v2->v3:
>  - No changes.
> 
> v1->v2:
>  - Use single compatible string instead of multiple compatible strings
>    for the two DU instances, leveraging a 'renesas,id' property to
>    differentiate between DU0 and DU1.
>  - Updated commit message accordingly.
> 
>  .../bindings/display/renesas,rzg2l-du.yaml    | 95 ++++++++++++++++++-
>  1 file changed, 91 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> index 5c9b15a09dee..d44c7c0add8d 100644
> --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> @@ -21,6 +21,7 @@ properties:
>            - renesas,r9a07g043u-du # RZ/G2UL
>            - renesas,r9a07g044-du # RZ/G2{L,LC}
>            - renesas,r9a08g046-du # RZ/G3L
> +          - renesas,r9a09g047-du # RZ/G3E
>            - renesas,r9a09g057-du # RZ/V2H(P)
>            - renesas,r9a09g077-du # RZ/T2H
>        - items:
> @@ -35,25 +36,51 @@ properties:
>            - const: renesas,r9a09g077-du # RZ/T2H fallback
>  
>    reg:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: du.0
> +      - const: du.1

du is the name of the device, thus calling items "0" and "1" is pretty
pointless - indices already define that. Please drop the reg-names.

>  
>    interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2
> +
> +  interrupt-names:
> +    items:
> +      - const: du.0
> +      - const: du.1

Same here

>  
>    clocks:
> +    minItems: 3
>      items:
>        - description: Main clock
>        - description: Register access clock
>        - description: Video clock
> +      - description: Main clock for DU1
> +      - description: Register access clock for DU1
> +      - description: Video clock for DU1
>  
>    clock-names:
> +    minItems: 3
>      items:
>        - const: aclk
>        - const: pclk
>        - const: vclk
> +      - const: aclk1
> +      - const: pclk1
> +      - const: vclk1
>  
>    resets:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2
> +
> +  reset-names:
> +    items:
> +      - const: resetn
> +      - const: resetn1

Drop reset-names

>  
>    power-domains:
>      maxItems: 1
> @@ -66,7 +93,7 @@ properties:
>        model-dependent. Each port shall have a single endpoint.
>  
>      patternProperties:
> -      "^port@[0-2]$":
> +      "^port@[0-3]$":
>          $ref: /schemas/graph.yaml#/properties/port
>          unevaluatedProperties: false
>  
> @@ -110,6 +137,7 @@ allOf:
>                description: DPI
>              port@1: false
>              port@2: false
> +            port@3: false

Best regards,
Krzysztof

Re: [PATCH v8 1/9] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3E SoC

[Tommaso Merciai]

Hi Krzysztof,
Thanks for your review.

On Wed, Sep 02, 2026 at 08:37:06AM +0200, Krzysztof Kozlowski wrote:
> On Fri, Aug 28, 2026 at 02:21:04PM +0200, Tommaso Merciai wrote:
> > The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> > Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> > Processor (VSPD), and Display Unit (DU).
> > 
> >  - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> >  - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> > 
> > Add new SoC-specific compatible string 'renesas,r9a09g047-du'.
> > 
> > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > ---
> > v7->v8:
> >  - Rebased on top of RZ/G3L du support [1]
> >  - Modelled using ports/port instead of port/ep.
> >    [1] https://lore.kernel.org/all/20260826174854.199139-1-biju.das.jz@bp.renesas.com/
> >  - Improved commit msg and commit body.
> > 
> > v6->v7:
> >  - Rebased on top of [1]
> >    [1] https://lore.kernel.org/all/20260429170012.366537-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> >  - Use single DRM device aggregating both DU instances (1 DU dt node),
> >    modelling single port for each DU0, DU1 and multiple endpoints for
> >    outputs.
> > 
> > v5->v6:
> >  - Extend patternProperties from "^port@[0-1]$" to "^port@[0-3]$" and
> >    explicitly disable port@2 and port@3 for existing SoCs that do not expose
> >    them.
> >  - Reworked ports numbering + improved/fixed ports descriptions in the
> >    bindings documentation.
> >  - Improved commit body.
> > 
> > v4->v5:
> >  - Dropped renesas,id property and updated bindings
> >    accordingly.
> > 
> > v2->v3:
> >  - No changes.
> > 
> > v2->v3:
> >  - No changes.
> > 
> > v1->v2:
> >  - Use single compatible string instead of multiple compatible strings
> >    for the two DU instances, leveraging a 'renesas,id' property to
> >    differentiate between DU0 and DU1.
> >  - Updated commit message accordingly.
> > 
> >  .../bindings/display/renesas,rzg2l-du.yaml    | 95 ++++++++++++++++++-
> >  1 file changed, 91 insertions(+), 4 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > index 5c9b15a09dee..d44c7c0add8d 100644
> > --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > @@ -21,6 +21,7 @@ properties:
> >            - renesas,r9a07g043u-du # RZ/G2UL
> >            - renesas,r9a07g044-du # RZ/G2{L,LC}
> >            - renesas,r9a08g046-du # RZ/G3L
> > +          - renesas,r9a09g047-du # RZ/G3E
> >            - renesas,r9a09g057-du # RZ/V2H(P)
> >            - renesas,r9a09g077-du # RZ/T2H
> >        - items:
> > @@ -35,25 +36,51 @@ properties:
> >            - const: renesas,r9a09g077-du # RZ/T2H fallback
> >  
> >    reg:
> > -    maxItems: 1
> > +    minItems: 1
> > +    maxItems: 2
> > +
> > +  reg-names:
> > +    items:
> > +      - const: du.0
> > +      - const: du.1
> 
> du is the name of the device, thus calling items "0" and "1" is pretty
> pointless - indices already define that. Please drop the reg-names.

Will drop this in v8.

> 
> >  
> >    interrupts:
> > -    maxItems: 1
> > +    minItems: 1
> > +    maxItems: 2
> > +
> > +  interrupt-names:
> > +    items:
> > +      - const: du.0
> > +      - const: du.1
> 
> Same here

Same, thanks.

> 
> >  
> >    clocks:
> > +    minItems: 3
> >      items:
> >        - description: Main clock
> >        - description: Register access clock
> >        - description: Video clock
> > +      - description: Main clock for DU1
> > +      - description: Register access clock for DU1
> > +      - description: Video clock for DU1
> >  
> >    clock-names:
> > +    minItems: 3
> >      items:
> >        - const: aclk
> >        - const: pclk
> >        - const: vclk
> > +      - const: aclk1
> > +      - const: pclk1
> > +      - const: vclk1
> >  
> >    resets:
> > -    maxItems: 1
> > +    minItems: 1
> > +    maxItems: 2
> > +
> > +  reset-names:
> > +    items:
> > +      - const: resetn
> > +      - const: resetn1
> 
> Drop reset-names

For reset-names, I got the the following comment from Philipp in v7 [1].

Dropping reset-names would force the driver back to an index-based
lookup, which is what that comment explicitly asked me to avoid.

[1] https://lore.kernel.org/all/8382e2b9fd07fb1132c26e228b3899336fc1fdd4.camel@pengutronix.de/

Philipp, Krzysztof, could you agree on which way you'd prefer?
I'll follow whatever you decide.

Kind regards,
Tommaso

> 
> >  
> >    power-domains:
> >      maxItems: 1
> > @@ -66,7 +93,7 @@ properties:
> >        model-dependent. Each port shall have a single endpoint.
> >  
> >      patternProperties:
> > -      "^port@[0-2]$":
> > +      "^port@[0-3]$":
> >          $ref: /schemas/graph.yaml#/properties/port
> >          unevaluatedProperties: false
> >  
> > @@ -110,6 +137,7 @@ allOf:
> >                description: DPI
> >              port@1: false
> >              port@2: false
> > +            port@3: false
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v8 1/9] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3E SoC

[Geert Uytterhoeven]

Hi all,

On Wed, 2 Sept 2026 at 16:03, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> On Wed, Sep 02, 2026 at 08:37:06AM +0200, Krzysztof Kozlowski wrote:
> > On Fri, Aug 28, 2026 at 02:21:04PM +0200, Tommaso Merciai wrote:
> > > The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> > > Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> > > Processor (VSPD), and Display Unit (DU).
> > >
> > >  - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> > >  - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> > >
> > > Add new SoC-specific compatible string 'renesas,r9a09g047-du'.
> > >
> > > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

> > > --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > > +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > > @@ -21,6 +21,7 @@ properties:
> > >            - renesas,r9a07g043u-du # RZ/G2UL
> > >            - renesas,r9a07g044-du # RZ/G2{L,LC}
> > >            - renesas,r9a08g046-du # RZ/G3L
> > > +          - renesas,r9a09g047-du # RZ/G3E
> > >            - renesas,r9a09g057-du # RZ/V2H(P)
> > >            - renesas,r9a09g077-du # RZ/T2H
> > >        - items:
> > > @@ -35,25 +36,51 @@ properties:
> > >            - const: renesas,r9a09g077-du # RZ/T2H fallback
> > >
> > >    reg:
> > > -    maxItems: 1
> > > +    minItems: 1
> > > +    maxItems: 2
> > > +
> > > +  reg-names:
> > > +    items:
> > > +      - const: du.0
> > > +      - const: du.1
> >
> > du is the name of the device, thus calling items "0" and "1" is pretty
> > pointless - indices already define that. Please drop the reg-names.
>
> Will drop this in v8.
>
> > >    interrupts:
> > > -    maxItems: 1
> > > +    minItems: 1
> > > +    maxItems: 2
> > > +
> > > +  interrupt-names:
> > > +    items:
> > > +      - const: du.0
> > > +      - const: du.1
> >
> > Same here
>
> Same, thanks.
>
> >
> > >
> > >    clocks:
> > > +    minItems: 3
> > >      items:
> > >        - description: Main clock
> > >        - description: Register access clock
> > >        - description: Video clock
> > > +      - description: Main clock for DU1
> > > +      - description: Register access clock for DU1
> > > +      - description: Video clock for DU1
> > >
> > >    clock-names:
> > > +    minItems: 3
> > >      items:
> > >        - const: aclk
> > >        - const: pclk
> > >        - const: vclk
> > > +      - const: aclk1
> > > +      - const: pclk1
> > > +      - const: vclk1
> > >
> > >    resets:
> > > -    maxItems: 1
> > > +    minItems: 1
> > > +    maxItems: 2
> > > +
> > > +  reset-names:
> > > +    items:
> > > +      - const: resetn
> > > +      - const: resetn1
> >
> > Drop reset-names
>
> For reset-names, I got the the following comment from Philipp in v7 [1].
>
> Dropping reset-names would force the driver back to an index-based
> lookup, which is what that comment explicitly asked me to avoid.
>
> [1] https://lore.kernel.org/all/8382e2b9fd07fb1132c26e228b3899336fc1fdd4.camel@pengutronix.de/
>
> Philipp, Krzysztof, could you agree on which way you'd prefer?
> I'll follow whatever you decide.

Until we get a variant with a third interrupt (or reset or reg),
which is not related to the number of channels...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v8 1/9] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3E SoC

[Tommaso Merciai]

On Wed, Sep 02, 2026 at 04:20:51PM +0200, Geert Uytterhoeven wrote:
> Hi all,
> 
> On Wed, 2 Sept 2026 at 16:03, Tommaso Merciai
> <tommaso.merciai.xr@bp.renesas.com> wrote:
> > On Wed, Sep 02, 2026 at 08:37:06AM +0200, Krzysztof Kozlowski wrote:
> > > On Fri, Aug 28, 2026 at 02:21:04PM +0200, Tommaso Merciai wrote:
> > > > The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> > > > Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> > > > Processor (VSPD), and Display Unit (DU).
> > > >
> > > >  - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> > > >  - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> > > >
> > > > Add new SoC-specific compatible string 'renesas,r9a09g047-du'.
> > > >
> > > > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> 
> > > > --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > > > +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > > > @@ -21,6 +21,7 @@ properties:
> > > >            - renesas,r9a07g043u-du # RZ/G2UL
> > > >            - renesas,r9a07g044-du # RZ/G2{L,LC}
> > > >            - renesas,r9a08g046-du # RZ/G3L
> > > > +          - renesas,r9a09g047-du # RZ/G3E
> > > >            - renesas,r9a09g057-du # RZ/V2H(P)
> > > >            - renesas,r9a09g077-du # RZ/T2H
> > > >        - items:
> > > > @@ -35,25 +36,51 @@ properties:
> > > >            - const: renesas,r9a09g077-du # RZ/T2H fallback
> > > >
> > > >    reg:
> > > > -    maxItems: 1
> > > > +    minItems: 1
> > > > +    maxItems: 2
> > > > +
> > > > +  reg-names:
> > > > +    items:
> > > > +      - const: du.0
> > > > +      - const: du.1
> > >
> > > du is the name of the device, thus calling items "0" and "1" is pretty
> > > pointless - indices already define that. Please drop the reg-names.
> >
> > Will drop this in v8.
> >
> > > >    interrupts:
> > > > -    maxItems: 1
> > > > +    minItems: 1
> > > > +    maxItems: 2
> > > > +
> > > > +  interrupt-names:
> > > > +    items:
> > > > +      - const: du.0
> > > > +      - const: du.1
> > >
> > > Same here
> >
> > Same, thanks.
> >
> > >
> > > >
> > > >    clocks:
> > > > +    minItems: 3
> > > >      items:
> > > >        - description: Main clock
> > > >        - description: Register access clock
> > > >        - description: Video clock
> > > > +      - description: Main clock for DU1
> > > > +      - description: Register access clock for DU1
> > > > +      - description: Video clock for DU1
> > > >
> > > >    clock-names:
> > > > +    minItems: 3
> > > >      items:
> > > >        - const: aclk
> > > >        - const: pclk
> > > >        - const: vclk
> > > > +      - const: aclk1
> > > > +      - const: pclk1
> > > > +      - const: vclk1
> > > >
> > > >    resets:
> > > > -    maxItems: 1
> > > > +    minItems: 1
> > > > +    maxItems: 2
> > > > +
> > > > +  reset-names:
> > > > +    items:
> > > > +      - const: resetn
> > > > +      - const: resetn1
> > >
> > > Drop reset-names
> >
> > For reset-names, I got the the following comment from Philipp in v7 [1].
> >
> > Dropping reset-names would force the driver back to an index-based
> > lookup, which is what that comment explicitly asked me to avoid.
> >
> > [1] https://lore.kernel.org/all/8382e2b9fd07fb1132c26e228b3899336fc1fdd4.camel@pengutronix.de/
> >
> > Philipp, Krzysztof, could you agree on which way you'd prefer?
> > I'll follow whatever you decide.
> 
> Until we get a variant with a third interrupt (or reset or reg),
> which is not related to the number of channels...

Right, IMHO names keep the driver flexible enough for such a variant,
indices don't.

Kind regards,
Tommaso

> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Re: [PATCH v8 1/9] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3E SoC

[Philipp Zabel]

On Mi, 2026-09-02 at 17:11 +0200, Tommaso Merciai wrote:
> On Wed, Sep 02, 2026 at 04:20:51PM +0200, Geert Uytterhoeven wrote:
> > Hi all,
> > 
> > On Wed, 2 Sept 2026 at 16:03, Tommaso Merciai
> > <tommaso.merciai.xr@bp.renesas.com> wrote:
> > > On Wed, Sep 02, 2026 at 08:37:06AM +0200, Krzysztof Kozlowski wrote:
> > > > On Fri, Aug 28, 2026 at 02:21:04PM +0200, Tommaso Merciai wrote:
> > > > > The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> > > > > Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> > > > > Processor (VSPD), and Display Unit (DU).
> > > > > 
> > > > >  - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> > > > >  - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> > > > > 
> > > > > Add new SoC-specific compatible string 'renesas,r9a09g047-du'.
> > > > > 
> > > > > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > 
> > > > > --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > > > > +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > > > > @@ -21,6 +21,7 @@ properties:
> > > > >            - renesas,r9a07g043u-du # RZ/G2UL
> > > > >            - renesas,r9a07g044-du # RZ/G2{L,LC}
> > > > >            - renesas,r9a08g046-du # RZ/G3L
> > > > > +          - renesas,r9a09g047-du # RZ/G3E
> > > > >            - renesas,r9a09g057-du # RZ/V2H(P)
> > > > >            - renesas,r9a09g077-du # RZ/T2H
> > > > >        - items:
> > > > > @@ -35,25 +36,51 @@ properties:
> > > > >            - const: renesas,r9a09g077-du # RZ/T2H fallback
> > > > > 
> > > > >    reg:
> > > > > -    maxItems: 1
> > > > > +    minItems: 1
> > > > > +    maxItems: 2
> > > > > +
> > > > > +  reg-names:
> > > > > +    items:
> > > > > +      - const: du.0
> > > > > +      - const: du.1
> > > > 
> > > > du is the name of the device, thus calling items "0" and "1" is pretty
> > > > pointless - indices already define that. Please drop the reg-names.
> > > 
> > > Will drop this in v8.
> > > 
> > > > >    interrupts:
> > > > > -    maxItems: 1
> > > > > +    minItems: 1
> > > > > +    maxItems: 2
> > > > > +
> > > > > +  interrupt-names:
> > > > > +    items:
> > > > > +      - const: du.0
> > > > > +      - const: du.1
> > > > 
> > > > Same here
> > > 
> > > Same, thanks.
> > > 
> > > > 
> > > > > 
> > > > >    clocks:
> > > > > +    minItems: 3
> > > > >      items:
> > > > >        - description: Main clock
> > > > >        - description: Register access clock
> > > > >        - description: Video clock
> > > > > +      - description: Main clock for DU1
> > > > > +      - description: Register access clock for DU1
> > > > > +      - description: Video clock for DU1
> > > > > 
> > > > >    clock-names:
> > > > > +    minItems: 3
> > > > >      items:
> > > > >        - const: aclk
> > > > >        - const: pclk
> > > > >        - const: vclk
> > > > > +      - const: aclk1
> > > > > +      - const: pclk1
> > > > > +      - const: vclk1
> > > > > 
> > > > >    resets:
> > > > > -    maxItems: 1
> > > > > +    minItems: 1
> > > > > +    maxItems: 2
> > > > > +
> > > > > +  reset-names:
> > > > > +    items:
> > > > > +      - const: resetn
> > > > > +      - const: resetn1
> > > > 
> > > > Drop reset-names
> > > 
> > > For reset-names, I got the the following comment from Philipp in v7 [1].
> > > 
> > > Dropping reset-names would force the driver back to an index-based
> > > lookup, which is what that comment explicitly asked me to avoid.
> > > 
> > > [1] https://lore.kernel.org/all/8382e2b9fd07fb1132c26e228b3899336fc1fdd4.camel@pengutronix.de/
> > > 
> > > Philipp, Krzysztof, could you agree on which way you'd prefer?
> > > I'll follow whatever you decide.
> > 
> > Until we get a variant with a third interrupt (or reset or reg),
> > which is not related to the number of channels...
> 
> Right, IMHO names keep the driver flexible enough for such a variant,
> indices don't.

I would like to get rid of the reset_control_get_by_index() API
altogether, if possible. Currently there are only users with index ==
0, so this would be the first and so far only valid user. I'd prefer if
we could keep reset lookup aligned with clock lookup, with via clock-
names as well.

That being said, why are the two DU units represented as a single
device tree node at all? Aren't they two completely separate instances
of the same IP core?

regards
Philipp

Re: [PATCH v8 1/9] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3E SoC

[Krzysztof Kozlowski]

On 03/09/2026 10:17, Philipp Zabel wrote:
> On Mi, 2026-09-02 at 17:11 +0200, Tommaso Merciai wrote:
>>>>>> +  reset-names:
>>>>>> +    items:
>>>>>> +      - const: resetn
>>>>>> +      - const: resetn1
>>>>>
>>>>> Drop reset-names
>>>>
>>>> For reset-names, I got the the following comment from Philipp in v7 [1].
>>>>
>>>> Dropping reset-names would force the driver back to an index-based
>>>> lookup, which is what that comment explicitly asked me to avoid.
>>>>
>>>> [1] https://lore.kernel.org/all/8382e2b9fd07fb1132c26e228b3899336fc1fdd4.camel@pengutronix.de/
>>>>
>>>> Philipp, Krzysztof, could you agree on which way you'd prefer?
>>>> I'll follow whatever you decide.
>>>
>>> Until we get a variant with a third interrupt (or reset or reg),
>>> which is not related to the number of channels...
>>
>> Right, IMHO names keep the driver flexible enough for such a variant,
>> indices don't.
> 
> I would like to get rid of the reset_control_get_by_index() API
> altogether, if possible. Currently there are only users with index ==
> 0, so this would be the first and so far only valid user. I'd prefer if
> we could keep reset lookup aligned with clock lookup, with via clock-
> names as well.

...and clk uses indexing partially. clk_get() is the corresponding
interface to get the index 0 and is widely used. I agree though there is
no general get-by-index API. If reset won't provide such API, then fine
for the names, but the order of entries is still fixed thus the names
are NOT allowing to change the order.

> 
> That being said, why are the two DU units represented as a single
> device tree node at all? Aren't they two completely separate instances
> of the same IP core?



Best regards,
Krzysztof

Re: [PATCH v8 1/9] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3E SoC

[Tommaso Merciai]

Hi Geert,

On Wed, Sep 02, 2026 at 04:20:51PM +0200, Geert Uytterhoeven wrote:
> Hi all,
> 
> On Wed, 2 Sept 2026 at 16:03, Tommaso Merciai
> <tommaso.merciai.xr@bp.renesas.com> wrote:
> > On Wed, Sep 02, 2026 at 08:37:06AM +0200, Krzysztof Kozlowski wrote:
> > > On Fri, Aug 28, 2026 at 02:21:04PM +0200, Tommaso Merciai wrote:
> > > > The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> > > > Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> > > > Processor (VSPD), and Display Unit (DU).
> > > >
> > > >  - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> > > >  - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> > > >
> > > > Add new SoC-specific compatible string 'renesas,r9a09g047-du'.
> > > >
> > > > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> 
> > > > --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > > > +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > > > @@ -21,6 +21,7 @@ properties:
> > > >            - renesas,r9a07g043u-du # RZ/G2UL
> > > >            - renesas,r9a07g044-du # RZ/G2{L,LC}
> > > >            - renesas,r9a08g046-du # RZ/G3L
> > > > +          - renesas,r9a09g047-du # RZ/G3E
> > > >            - renesas,r9a09g057-du # RZ/V2H(P)
> > > >            - renesas,r9a09g077-du # RZ/T2H
> > > >        - items:
> > > > @@ -35,25 +36,51 @@ properties:
> > > >            - const: renesas,r9a09g077-du # RZ/T2H fallback
> > > >
> > > >    reg:
> > > > -    maxItems: 1
> > > > +    minItems: 1
> > > > +    maxItems: 2
> > > > +
> > > > +  reg-names:
> > > > +    items:
> > > > +      - const: du.0
> > > > +      - const: du.1
> > >
> > > du is the name of the device, thus calling items "0" and "1" is pretty
> > > pointless - indices already define that. Please drop the reg-names.
> >
> > Will drop this in v8.
> >
> > > >    interrupts:
> > > > -    maxItems: 1
> > > > +    minItems: 1
> > > > +    maxItems: 2
> > > > +
> > > > +  interrupt-names:
> > > > +    items:
> > > > +      - const: du.0
> > > > +      - const: du.1
> > >
> > > Same here
> >
> > Same, thanks.
> >
> > >
> > > >
> > > >    clocks:
> > > > +    minItems: 3
> > > >      items:
> > > >        - description: Main clock
> > > >        - description: Register access clock
> > > >        - description: Video clock
> > > > +      - description: Main clock for DU1
> > > > +      - description: Register access clock for DU1
> > > > +      - description: Video clock for DU1
> > > >
> > > >    clock-names:
> > > > +    minItems: 3
> > > >      items:
> > > >        - const: aclk
> > > >        - const: pclk
> > > >        - const: vclk
> > > > +      - const: aclk1
> > > > +      - const: pclk1
> > > > +      - const: vclk1
> > > >
> > > >    resets:
> > > > -    maxItems: 1
> > > > +    minItems: 1
> > > > +    maxItems: 2
> > > > +
> > > > +  reset-names:
> > > > +    items:
> > > > +      - const: resetn
> > > > +      - const: resetn1
> > >
> > > Drop reset-names
> >
> > For reset-names, I got the the following comment from Philipp in v7 [1].
> >
> > Dropping reset-names would force the driver back to an index-based
> > lookup, which is what that comment explicitly asked me to avoid.
> >
> > [1] https://lore.kernel.org/all/8382e2b9fd07fb1132c26e228b3899336fc1fdd4.camel@pengutronix.de/
> >
> > Philipp, Krzysztof, could you agree on which way you'd prefer?
> > I'll follow whatever you decide.
> 
> Until we get a variant with a third interrupt (or reset or reg),
> which is not related to the number of channels...

Just to make sure I follow: are you referring to variants like R-Car H3
and M3-N, where the position in the array no longer matches the channel
index? From renesas,du.yaml:

[renesas,du-r8a7795: 4 channels, two resets] [1]
  reset-names:
    items:
      - const: du.0
      - const: du.2

[renesas,du-r8a77965: 3 channels, du.2 (channel 2) does not exist] [2]
  clock-names:
    items:
      - const: du.0
      - const: du.1
      - const: du.3
  reset-names:
    items:
      - const: du.0
      - const: du.3

If so, I agree: the names are what makes these unambiguous, and an
index-based lookup could not express them.

Then on RZ/G3E we can keep:

reg-names:
    items:
      - const: du.0
      - const: du.1

interrupt-names:
    items:
      - const: du.0
      - const: du.1

Maybe make sense also for reset-names having:

reset-names:
    items:
      - const: du.0
      - const: du.1

?

Then we can add struct rzg2l_du_channel_res:

struct rzg2l_du_channel_res {
	const char *reg;
	const char *aclk;
	const char *pclk;
	const char *vclk;
	const char *rst;
};

Into struct rzg2l_du_device_info in this way we can cover future cases
du-r8a77965, du-r8a7795 -like using:

static const struct rzg2l_du_channel_res rzg2l_du_r8a7795_channels_res[] = {
	[0] = { "du.0", "aclk",  "pclk",  "vclk",  "du.0" },
	[1] = { "du.1", "aclk1", "pclk1", "vclk1", "du.0" },
	[2] = { "du.2", "aclk2", "pclk2", "vclk2", "du.2" },
	[3] = { "du.3", "aclk3", "pclk3", "vclk3", "du.2" },
};

static const struct rzg2l_du_device_info rzg2l_du_r8a7795_info = {
	.channels_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
	.channels_res = rzg2l_du_r8a7795_channels_res,
	.num_channels_res = ARRAY_SIZE(rzg2l_du_r8a7795_channels_res),
	.routes = {
		[RZG2L_DU_OUTPUT_DPAD0] = {
			.possible_crtcs = BIT(0),
			.port = 0,
		},
		[RZG2L_DU_OUTPUT_DSI0] = {
			.possible_crtcs = BIT(1) | BIT(2),
			.port = 1,
		},
		[RZG2L_DU_OUTPUT_LVDS0] = {
			.possible_crtcs = BIT(3),
			.port = 3,
		},
	},
	.mode_clock_min = 5440,
	.mode_clock_max = 87000,
};

/* Channels 0, 1 and 3: channel 2 does not exist, so [2] is a hole. */
static const struct rzg2l_du_channel_res rzg2l_du_r8a77965_channels_res[] = {
	[0] = { "du.0", "aclk",  "pclk",  "vclk",  "du.0" },
	[1] = { "du.1", "aclk1", "pclk1", "vclk1", "du.0" },
	[3] = { "du.3", "aclk3", "pclk3", "vclk3", "du.3" },
};

static const struct rzg2l_du_device_info rzg2l_du_r8a77965_info = {
	.channels_mask = BIT(0) | BIT(1) | BIT(3),
	.channels_res = rzg2l_du_r8a77965_channels_res,
	.num_channels_res = ARRAY_SIZE(rzg2l_du_r8a77965_channels_res),
	.routes = {
		/*
		 * possible_crtcs is a software channel index: hardware channel
		 * 3 is the third populated one, hence BIT(2) and not BIT(3).
		 */
		[RZG2L_DU_OUTPUT_DPAD0] = {
			.possible_crtcs = BIT(0),
			.port = 0,
		},
		[RZG2L_DU_OUTPUT_DSI0] = {
			.possible_crtcs = BIT(1),
			.port = 1,
		},
		[RZG2L_DU_OUTPUT_LVDS0] = {
			.possible_crtcs = BIT(2),
			.port = 2,
		},
	},
	.mode_clock_min = 5440,
	.mode_clock_max = 87000,
};

And for RZ/G3E we will have:

static const struct rzg2l_du_channel_res rzg2l_du_r9a09g047_channels_res[] = {
	[0] = { "du.0", "aclk",  "pclk",  "vclk",  "du.0" },
	[1] = { "du.1", "aclk1", "pclk1", "vclk1", "du.1" },
};

static const struct rzg2l_du_device_info rzg2l_du_r9a09g047_info = {
	.channels_mask = BIT(0) | BIT(1),
	.channels_res = rzg2l_du_r9a09g047_channels_res,
	.num_channels_res = ARRAY_SIZE(rzg2l_du_r9a09g047_channels_res),
	.routes = {
		[RZG2L_DU_OUTPUT_DSI0] = {
			.possible_crtcs = BIT(0) | BIT(1),
			.port = 0,
		},
		[RZG2L_DU_OUTPUT_DPAD0] = {
			.possible_crtcs = BIT(1),
			.port = 1,
		},
		[RZG2L_DU_OUTPUT_LVDS0] = {
			.possible_crtcs = BIT(0),
			.port = 2,
		},
		[RZG2L_DU_OUTPUT_LVDS1] = {
			.possible_crtcs = BIT(0) | BIT(1),
			.port = 3,
		},
	},
	.mode_clock_min = 5400,
	.mode_clock_max = 87000,
};

What do you think?

[1] https://elixir.bootlin.com/linux/v7.2/source/arch/arm64/boot/dts/renesas/r8a77951.dtsi#L3363
[2] https://elixir.bootlin.com/linux/v7.2/source/arch/arm64/boot/dts/renesas/r8a77965.dtsi#L2819

Kind regards,
Tommaso

> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Re: [PATCH v8 1/9] dt-bindings: display: renesas,rzg2l-du: Document RZ/G3E SoC

[Geert Uytterhoeven]

Hi Tommaso,

On Thu, 3 Sept 2026 at 13:01, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> On Wed, Sep 02, 2026 at 04:20:51PM +0200, Geert Uytterhoeven wrote:
> > On Wed, 2 Sept 2026 at 16:03, Tommaso Merciai
> > <tommaso.merciai.xr@bp.renesas.com> wrote:
> > > On Wed, Sep 02, 2026 at 08:37:06AM +0200, Krzysztof Kozlowski wrote:
> > > > On Fri, Aug 28, 2026 at 02:21:04PM +0200, Tommaso Merciai wrote:
> > > > > The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression
> > > > > Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal
> > > > > Processor (VSPD), and Display Unit (DU).
> > > > >
> > > > >  - LCDC0 supports DSI and LVDS (single or dual-channel) outputs.
> > > > >  - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs.
> > > > >
> > > > > Add new SoC-specific compatible string 'renesas,r9a09g047-du'.
> > > > >
> > > > > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> >
> > > > > --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > > > > +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > > > > @@ -21,6 +21,7 @@ properties:
> > > > >            - renesas,r9a07g043u-du # RZ/G2UL
> > > > >            - renesas,r9a07g044-du # RZ/G2{L,LC}
> > > > >            - renesas,r9a08g046-du # RZ/G3L
> > > > > +          - renesas,r9a09g047-du # RZ/G3E
> > > > >            - renesas,r9a09g057-du # RZ/V2H(P)
> > > > >            - renesas,r9a09g077-du # RZ/T2H
> > > > >        - items:
> > > > > @@ -35,25 +36,51 @@ properties:
> > > > >            - const: renesas,r9a09g077-du # RZ/T2H fallback
> > > > >
> > > > >    reg:
> > > > > -    maxItems: 1
> > > > > +    minItems: 1
> > > > > +    maxItems: 2
> > > > > +
> > > > > +  reg-names:
> > > > > +    items:
> > > > > +      - const: du.0
> > > > > +      - const: du.1
> > > >
> > > > du is the name of the device, thus calling items "0" and "1" is pretty
> > > > pointless - indices already define that. Please drop the reg-names.
> > >
> > > Will drop this in v8.
> > >
> > > > >    interrupts:
> > > > > -    maxItems: 1
> > > > > +    minItems: 1
> > > > > +    maxItems: 2
> > > > > +
> > > > > +  interrupt-names:
> > > > > +    items:
> > > > > +      - const: du.0
> > > > > +      - const: du.1
> > > >
> > > > Same here
> > >
> > > Same, thanks.
> > >
> > > > >    clocks:
> > > > > +    minItems: 3
> > > > >      items:
> > > > >        - description: Main clock
> > > > >        - description: Register access clock
> > > > >        - description: Video clock
> > > > > +      - description: Main clock for DU1
> > > > > +      - description: Register access clock for DU1
> > > > > +      - description: Video clock for DU1
> > > > >
> > > > >    clock-names:
> > > > > +    minItems: 3
> > > > >      items:
> > > > >        - const: aclk
> > > > >        - const: pclk
> > > > >        - const: vclk
> > > > > +      - const: aclk1
> > > > > +      - const: pclk1
> > > > > +      - const: vclk1
> > > > >
> > > > >    resets:
> > > > > -    maxItems: 1
> > > > > +    minItems: 1
> > > > > +    maxItems: 2
> > > > > +
> > > > > +  reset-names:
> > > > > +    items:
> > > > > +      - const: resetn
> > > > > +      - const: resetn1
> > > >
> > > > Drop reset-names
> > >
> > > For reset-names, I got the the following comment from Philipp in v7 [1].
> > >
> > > Dropping reset-names would force the driver back to an index-based
> > > lookup, which is what that comment explicitly asked me to avoid.
> > >
> > > [1] https://lore.kernel.org/all/8382e2b9fd07fb1132c26e228b3899336fc1fdd4.camel@pengutronix.de/
> > >
> > > Philipp, Krzysztof, could you agree on which way you'd prefer?
> > > I'll follow whatever you decide.
> >
> > Until we get a variant with a third interrupt (or reset or reg),
> > which is not related to the number of channels...
>
> Just to make sure I follow: are you referring to variants like R-Car H3
> and M3-N, where the position in the array no longer matches the channel
> index? From renesas,du.yaml:

Not directly, as these don't have any non-"du.X" resets and clocks.
But yes, these cases are similar.

> [renesas,du-r8a7795: 4 channels, two resets] [1]
>   reset-names:
>     items:
>       - const: du.0
>       - const: du.2
>
> [renesas,du-r8a77965: 3 channels, du.2 (channel 2) does not exist] [2]
>   clock-names:
>     items:
>       - const: du.0
>       - const: du.1
>       - const: du.3
>   reset-names:
>     items:
>       - const: du.0
>       - const: du.3
>
> If so, I agree: the names are what makes these unambiguous, and an
> index-based lookup could not express them.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds